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DG401/403/405
Low-Power, High-Speed CMOS Analog Switches
Features
D D D D D D 44-V Supply Max Rating "15-V Analog Signal Range On-Resistance--rDS(on): 20 W Low Leakage--ID(on): 40 pA Fast Switching--tON: 100 ns Ultra Low Power Requirements--PD: 0.35 mW D TTL, CMOS Compatible D Single Supply Capability
Benefits
D D D D Wide Dynamic Range Low Signal Errors and Distortion Break-Before-Make Switching Action Simple Interfacing
Applications
D D D D D D Audio and Video Switching Sample-and-Hold Circuits Battery Operation Test Equipment Hi-Rel Systems PBX, PABX
Description
The DG401/403/405 monolithic analog switches were designed to provide precision, high performance switching of analog signals. Combining low power (0.35 mW, typ) with high speed (tON: 100 ns, typ), the DG401 series is ideally suited for portable and battery powered industrial and military applications. Built on the Siliconix proprietary high-voltage silicon-gate process to achieve high voltage rating and superior switch on/off performance, break-before-make is guaranteed for the SPDT configurations. An epitaxial layer prevents latchup. Each switch conducts equally well in both directions when on, and blocks up to 30 V peak-to-peak when off. On-resistance is very flat over the full "15-V analog range, rivaling JFET performance without the inherent dynamic range limitations. The three devices in this series are differentiated by the type of switch action as shown in the functional block diagrams.
Functional Block Diagrams and Pin Configurations
DG401
Dual-In-Line and SOIC D1 NC NC NC NC NC NC D2 1 2 3 4 5 6 7 8 Top View 16 15 14 13 12 11 10 9 S1 IN1 V- GND VL V+ IN2 S2 NC NC NC NC NC Key 4 5 6 7 8 9 10 11 12 13 LCC NC D1 NC S1 IN1 3 2 1 20 19 18 17 16 15 14 V- GND NC VL V+ Two SPST Switches per Package
DG401
Truth Table Logic
0 1
Switch
OFF ON
Logic "0" v 0.8 V Logic "1" w 2 4 V 2.4
NC D2 NC S2 IN2 Top View
Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70049.
Siliconix S-53748--Rev. E, 05-Jun-97
1
DG401/403/405
Functional Block Diagrams and Pin Configurations (Cont'd)
DG403
LCC Key D3 S3 NC S4 D4 4 5 6 7 8 9 10 11 12 13 NC D1 NC S1 IN1 3 2 1 20 19 18 17 16 V- GND NC Two SPDT Switches per Package 16 S1 15 IN1 14 V- 13 GND 12 VL 11 V+ 10 IN2 9 Top View S2
DG403
Dual-In-Line and SOIC D1 1
NC 2 D3 S3 S4 D4 3 4 5 6
Truth Table Logic
0 1
SW1, SW2
OFF ON
SW3, SW4
ON OFF
NC 7 D2 8
15 V L 14 V+
Logic "0" v 0.8 V 1 Logic "1" w 2.4 V
NC D2 NC S2 IN2 Top View
DG405
Dual-In-Line and SOIC D1 NC D3 S3 S4 D4 NC D2 1 2 3 4 5 6 7 8 Top View 16 S1 15 IN1 14 V- 13 GND 12 VL 11 V+ 10 IN2 9 S2 D3 S3 NC S4 D4 Key 4 5 6 7 8 9 3 2
DG405
LCC NC D1 NC S1 IN1 1 20 19 18 17 16 15 14 10 11 12 Top View 13 V- GND NC VL V+ Two DPST Switches per Package
Truth Table Logic
0 1
Switch
OFF ON
Logic "0" v 0.8 V 1 Logic "1" w 2.4 V
NC D2 NC S2 IN2
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Siliconix S-53748--Rev. E, 05-Jun-97
DG401/403/405
Ordering Information
Temp Range DG401
-40 to 85_C 16-Pin Plastic DIP 16-Pin CerDIP LCC-20 DG401DJ DG401AK DG401AK/883 DG401AZ/883
Package
Part Number
-55 to 125_C
DG403
-40 to 85_C 16-Pin Plastic DIP 16-Pin Narrow SOIC 16-Pin CerDIP LCC-20 DG403DJ DG403DY DG403AK DG403AK/883 5962-8976301M2A
-55 to 125_C
DG405
-40 to 85_C -55 to 125_C 16-Pin Plastic DIP 16-Pin Narrow SOIC 16-Pin CerDIP LCC-20 DG405DJ DG405DY DG405AK/883 5962-89961012A
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V GND to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3 V) to (V+) +0.3 V Digital Inputsa VS, VD . . . . . . . . . . . . . . . . . (V-) -2 V to (V+ plus 2 V) or 30 mA, whichever occurs first Current (Any Terminal) Continuous . . . . . . . . . . . . . . . . . . . . . . 30 mA Current, S or D (Pulsed 1 ms 10% duty) . . . . . . . . . . . . . . . . . . 100 mA Storage Temperature (AK, AZ Suffix) . . . . . . . . . . -65 to 150_C (DJ, DY Suffix) . . . . . . . . . . . -65 to 125_C Power Dissipation (Package)b 16-Pin Plastic DIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW 16-Pin CerDIPd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW 16-Pin SOICe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 mW LCC-20f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Notes: a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC Board. c. Derate 6 mW/_C above 75_C d. Derate 12 mW/_C above 75_C e. Derate 7.6 mW/_C above 75_C f. Derate 13 mW/_C above 75_C
Siliconix S-53748--Rev. E, 05-Jun-97
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DG401/403/405
Specificationsa
Test Conditions Unless Specified Parameter Analog Switch
Analog Signal Rangee Drain-Source On-Resistance D Drain-Source On-Resistance Switch Off Leakage C Lk Current Channel On Leakage Current VANALOG rDS(on) DrDS(on) IS(off) ID(off) ID(on) IS = -10 mA, VD = "10 V V+ = 13.5 V, V- = -13.5 V IS = -10 mA, VD = "5 V, 0 V V+ = 16.5 V, V- = -16.5 V V+ = 16.5, V- = -16.5 V , VD = "15.5 V, VS = #15.5 V 15 5 V 15 5 V+ = 16.5 V, V- = -16.5 V VS = VD = "15.5 V Full Room Full Room Full Room Hot Room Hot Room Hot 20 3 -0.01 -0.01 -0.04 -0.25 -20 -0.25 -20 -0.4 -40 -15 15 35 45 3 5 0.25 20 0.25 20 0.4 40 -0.5 -5 -0.5 -5 -1 -10 -15 15 45 55 3 5 0.5 5 0.5 5 1 10 nA V
A Suffix
-55 to 125_C
D Suffix
-40 to 85_C
Symbol
V+ = 15 V, V- = -15 V VL = 5 V, VIN = 2.4 V, 0.8 Vf
Tempb
Typc
Mind
Maxd Mind Maxd Unit
W
Digital Control
Input Current VIN Low Input Current VIN High IIL IIH VIN under test = 0.8 V All Other = 2.4 V VIN under test = 2.4 V All Other = 0.8 V Full Full 0.005 0.005 -1 -1 1 1 -1 -1 1 mA 1
Dynamic Characteristics
Turn-On Time Turn-Off Time Break-Before-Make Time Delay (DG403) Charge Injection Off Isolation Reject Ratio Channel-to-Channel Crosstalk Source Off Capacitance Drain Off Capacitance Channel On Capacitance tON tOFF tD Q OIRR XTALK CS(off) CD(off) CD, CS(on) f = 1 MHz, VS = 0 V RL = 300 W , CL = 35 pF p S Fi See Figure 2 RL = 300 W , CL = 35 pF CL = 10,000 pF Vgen = 0 V, Rgen = 0 W RL = 100 W , CL = 5 pF f = 1 MHz Room Room Room Room Room Room Room Room Room 100 60 12 60 72 90 12 12 39 pF dB 5 150 100 5 pC 150 100 ns
Power Supplies
Positive Supply Current Negative Supply Current Logic Supply Current Ground Current I+ I- IL IGND Room Full V+ = 16.5 V, V- = -16.5 V , VIN = 0 or 5 V Room Full Room Full Room Full 0.01 -0.01 0.01 -0.01 -1 -5 -1 -5 1 5 -1 -5 1 5 -1 -5 1 5 1 5
mA
Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function.
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Siliconix S-53748--Rev. E, 05-Jun-97
DG401/403/405
Typical Characteristics
Input Switching Threshold vs. Logic Supply Voltage
10 V+ = 15 V V- = -15 V TA = 25_C 3.5 3.0 2.5 VIN (V) 2.0 1.5 1.0 0.5 0 (V+) 5 (V-) -5 VL = 5 V VL = 7 V
Input Switching Threshold vs. Supply Voltages
8
VT (V)
6
4
DG403 SW3, 4
2
0 0 2 4 6 8 10 12 14 16 18 20 VL - Logic Supply (V)
10 -10
15 -15
20 -10
25 -5
30 0
35 0
40 0
rDS(on) vs. VD and Temperature
35 rDS(on) - Drain-Source On-Resistance ( W ) rDS(on) - Drain-Source On-Resistance ( W ) V+ = 15 V, V- = -15 V VL = 5 V 40
rDS(on) vs. VD and Power Supply Voltage
TA = 25_C "6 V
30 125_C 25 85_C 20
30 "10 V "12 V 20 "15 V "20 V "22 V 10 -25 -15 -5 5 15 26
25_C 0_C
15
-40_C -55_C
10 -15 -10 -5 0 5 10 15 VD - Drain Voltage (V)
VD - Drain Voltage (V)
rDS(on) vs. VD and Power Supply Voltage (V- = 0 V)
70 rDS(on) - Drain-Source On-Resistance ( W ) TA = 25_C 60 7.5 V 50 40 30 20 10 0 5 10 15 20 25 VD - Drain Voltage (V) 10 V 12 V 15 V 20 V 22 V Q (pC) 200 180 160 140 120 100 80 60 40 20 0 -15
Charge Injection vs. Analog Voltage
V+ = 15 V, V- = -15 V VL = 5 V CL = 10 k pF 1 k pF
100 pF
-10
-5
0
5
10
15
VS - Source Voltage (V)
Siliconix S-53748--Rev. E, 05-Jun-97
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DG401/403/405
Typical Characteristics (Cont'd)
Leakage Current vs. Temperature
100 nA 10 nA 1 nA I S , I D (pA) I D(off) ID(off) 100 pA ID(on) 10 pA -90 1 pA 0.1 pA -55 -35 -15 -120 -150 5 25 45 65 85 105 125 -15 -10 -5 0 5 10 15 Temperature (_C) VD or VS - Drain or Source Voltage (V) V+ = 15 V, V- = -15 V VL = 5 V, TA = 25_C For ID(off), VS = 0 V For IS(off), VD = 0 V V+ = 15 V V- = -15 V VL = 5 V VD = "14 V 90 60 30 0 -30 ID(on) -60 ID(off), IS(off)
Leakage Current vs. Analog Voltage
Supply Current vs. Temperature
100 n I+ 10 n (A) V+ = 15 V, V- = -15 V VL = 5 V I- IL t ON , t OFF (ns) 1n
L
Switching Time vs. Temperature*
240 210 180 150 VS = 10 V 120 90 60 30 VS = -10 V VS = -10 V VS = 10 V V+ = 15 V, V- = -15 V, VL = 5 V tOFF tON
I+, I-, I
100 p IL I- 1p -55 -35 -15 5 25 45 65 85 105 125
10.0 p
0 -55 -35 -15 5 25 45 65 85 TA - Temperature (_C) 105 125
TA - Temperature (_C)
200 180 160 140 t ON , t OFF (ns) 120 100 80 60 40 20 0
Switching Time vs. Power Supply Voltage*
300 270
Switching Time vs. Positive Supply Voltage*
0V -5 V -15 V VS = 5 V
VS = 5 V t ON , t OFF (ns) VS = -5 V VS = 5 V
240 210 180 150 120 90 VL = 5 V tON 60 tOFF "25 30 0 0
-15 V -5 V 0V 0V -15 V
VS = -5 V
tON 5 10 15 20
tOFF 25
0
"5
"10
"15
"20
V+, V- Positive and Negative Supplies (V) *Refer to Figure 2 for test conditions.
V+ - Positive Supply (V)
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Siliconix S-53748--Rev. E, 05-Jun-97
DG401/403/405
Schematic Diagram (Typical Channel)
V+ S VL V- VIN Level Shift/ Drive V+ GND D V-
Figure 1.
Test Circuits
VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform. tr <20 ns 3V tf <20 ns Logic 50% +5 V +15 V Input 0V VL "10 V S IN GND V- V+ D Switch Input* tOFF VS 90% 0V tON VO -VS 90% VO
VO RL 1 kW CL 35 pF
Switch Output Switch Input*
-15 V CL (includes fixture and stray capacitance) VO = VS RL RL + rDS(on)
*VS = 10 V for tON, VS = -10 V for tOFF Note: Logic input waveform is inverted for switches that have the opposite logic sense control
Figure 2. Switching Time
+5 V VL VS1 VS2 S1 S2 IN GND
+15 V V+ D1 D2 VO2 VO1
Logic Input
3V 50% 0V VS1 VO1
90%
Switch Output RL1 V- RL2 CL2 CL1 Switch Output
0V VS2 VO2 0V
90% tD tD
-15 V CL (includes fixture and stray capacitance)
Figure 3. Break-Before-Make
Siliconix S-53748--Rev. E, 05-Jun-97
7
DG401/403/405
Test Circuits (Cont'd)
+5 V +15 V VL S IN 3V GND V- Q = DVO x CL -15 V V+ D CL 10 nF DVO VO VO IN
Rg
Vg
On
Off
On
Figure 4. Charge Injection
+5 V C VL VS Rg = 50 W 0V, 2.4 V IN GND V- C S
V+
+15 V C
D
VO RL 100 W VS Rg = 50 W 0V, 2.4 V VS VO
+5 V C VL S
+15 V C V+ D VO RL 100 W
IN GND V- C
-15 V Off Isolation = 20 log C = RF bypass
-15 V C = RF bypass
Figure 5. Off Isolation
Figure 6. Insertion Loss
C
+5 V
+15 V
C +5 V C 50 W VL
V+
VS Rg = 50 W VO RL 0.8 V
VL S1
V+ D
+15 V C
S2
S Meter
IN GND V- C
0 V, 2.4 V
IN D GND V- C
HP4192A Impedance Analyzer or Equivalent f = 1 MHz
-15 V XTALK Isolation = 20 log C = RF bypass VS VO -15 V
Figure 7. Crosstalk
Figure 8. Capacitances
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Siliconix S-53748--Rev. E, 05-Jun-97
DG401/403/405
Applications
+5 V +15 V +5 V VL ein Left S1 S3 IN1 D2 D4 Right TTL Integrate/ Reset S2 S4 IN2 C1 D2 D4 C2 +15 V V+ D1 D3
+ -
VL Left Source 1 Right Left Source 2 Right S4 IN2 TTL Channel Select GND S1 S3 IN1 S2
V+ D1 D3
eout
DG403
V- -15 V
Slope Select
DG403
GND V- -15 V
Figure 9. Stereo Source Selector
Figure 10. Dual Slope Integrator
Stereo Source Selector:
+5 V +15 V V+ D1 D3
A single logic signal controls the status of all four switches of the device, simplifying stereo source switching. The low on-resistance (<35 W) minimizes total harmonic distortion.
VL S1 S3 IN1
Dual Slope Integrators:
ein
S2 S4 IN2
D2 D4
The DG403 is well suited to configure a selectable slope integrator. One control signal selects the timing capacitor C1 or C2. Another one selects ein or discharges the capacitor in preparation for the next integration cycle.
Clock GND
DG403
V-
Band-Pass Switched Capacitor Filter:
Single-pole double-throw switches are a common element for switched capacitor networks and filters. The fast switching times and low leakage of the DG403 allow for higher clock rates and consequently higher filter operating frequencies. Siliconix S-53748--Rev. E, 05-Jun-97
-15 V
+
-
eout
Figure 11. Band-Pass Switched Capacitor Filter
9
DG401/403/405
Applications (Cont'd)
Peak Detector:
A3 acting as a comparator provides the logic drive for operating SW1. The output of A2 is fed back to A3 and compared to the analog input ein. If ein > eout the output of A3 is high keeping SW1 closed. This allows C1 to charge up to the analog input voltage. When ein goes below eout A3 goes negative, turning SW1 off. The system will therefore store the most positive analog input experienced.
Reset
SW2
-
SW1
R1
+ -
ein
+
A1 C1
A2
eout
+ -
DG401
A3
Figure 12. Positive Peak Detector
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Siliconix S-53748--Rev. E, 05-Jun-97

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