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Features
* * * * * * * * * * * * * * * * *
Antenna Driver Stage with Adjustable Antenna Peak Current for up to 1.5 A Frequency Tuning Range from 100 kHz to 150 kHz Automatic Antenna Peak Current Regulation Self-tuning Oscillator for Antenna Resonant Frequency Adaption Capable of Driving a High-Q Antenna Integrated 5 V Regulator for External Load up to 10 mA Bi-directional Single Wire Interface for Microcontroller or ECU LF Baud Rates up to 4 kbaud and Amplitude Shift Keying (ASK) Modulation Low Power Standby Mode < 50 A Antenna Driver Diagnosis: Peak Current, Antenna Frequency and Battery Voltage Monitoring Power Supply Range 8 V to 24 V Direct Battery Input Load Dump Protection up to 45 V for 12 V Boards Operation at Temperature -40C to +105C EMI and ESD According to Automotive Requirements Highly Integrated, Fewer External Components Required Driver Overcurrent Protection Overtemperature Protection
125 kHz Transmitter IC for TPM ATA5275 Preliminary
Applications
* Tire Pressure Measurement (TPM)
Benefits
* Self Tuning Capability to Antenna Resonance Frequency * Adjustable Antenna Peak Current Value * Highest Integration Level for Embedded Automotive Systems
Electrostatic sensitive device. Observe precautions for handling.
Description
The ATA5275 is an integrated 1.5 A peak current BCDMOS antenna driver IC dedicated as a 125 kHz wake-up channel transmitter for TPM applications. It includes the full functionality to generate a magnetic LF field in conjunction with an antenna coil to transmit data and power to a receiver. The transmission can be controlled via a one wire I/O-interface by an external unit. The smart power IC is delivered in a QFN20 power package with heat slug.
Rev. 4739C-AUTO-02/05
1. General Description
The ATA5275 is a 125-kHz transmitter IC. It is dedicated to driving 125 kHz LC antenna tanks, specifically for the wake-up channel in Tire Pressure Measurement (TPM) applications. It includes a control logic with VCO which generates the 125 kHz signal for the output driver stage. A phase lock circuit regulates the driver output frequency on the antenna resonance frequency, achieving a maximum field strength on the antenna. The driver duty cycle is regulated and stabilizes the antenna current for a wide supply voltage range. The IC can be controlled by a microcontroller or ECU via the one wire bi-directional interface. It is used for the data transmission and to indicate errors. For the data transmission ASK modulation is used. The antenna signal is modulated by the DIO interface line. The IC has a build in diagnosis function and detects detuning and broken or short wire of the antenna circuitry. If a failure is detected the IC indicates it by an error signal via the DIO line. The integrated 5 V regulator can be used externally for a load up to 10 mA. Figure 1-1. Block Diagram
20 DVCC3 19 BOOST 18 VCC 17 DIO 16 VDIO
1
DVCC2
5V REG
REF
BIAS
KLine
15 TM1
2 DVCC1
ATA5275
125-kHz Transmitter State Machine
14 TM2
Half Bridge
3 DRV3
13 TM3
Gate Drive Control
VCO
XOR
4 DRV2
12 RCR
5 DRV1
11 REXT
6 DVSS3
7 DVSS2
8 DVSS1
9 SENSE
10 VSS
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ATA5275 [Preliminary]
2. Pin Configuration
Figure 2-1. Pinning QFN20
20 19 DVCC3 BOOST 18 VCC 17 DIO 16 VDIO
1
DVCC2 2 DVCC1
15 TM1
14 TM2
3 DRV3
ATA5275
13 TM3
4 DRV2
12 RCR
5 DRV1
11 REXT
6 DVSS3
7 DVSS2
8 DVSS1
9 SENSE
10 VSS
Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
(1)
Pin Description
Symbol DVCC2 DVCC1 DRV3 DRV2 DRV1 DVSS3 DVSS2 DVSS1 SENSE VSS REXT RCR TM3 TM2 TM1 VDIO DIO VCC BOOST Function Battery supply input Battery supply input Antenna driver stage output Antenna driver stage output Antenna driver stage output Power supply ground Power supply ground Power supply ground Current zero crossing sense input Analog and digital ground External reference current input External reference for antenna peak current For test purposes only For test purposes only For test purposes only DIO line interface voltage selection One-wire serial interface line 5 V supply output (for external storage capacitor only) External bootstrap cap
20 DVCC3 Battery supply input Note: 1. Pin numbers valid for all revisions of the ATA5275
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3. Functional Description
3.1 Operation Modes
There are two different operation modes for the ATA5275: * Standby mode * Transmission mode
3.2
Standby Mode and Wake-up
After power-on-reset, the ATA5275 is in standby mode. For minimum power consumption, only the internal 5 V supply and the DIO line interface are active. The IC can be activated by the external control unit via the serial interface. The DIO line is called logic high if it is pulled up to the VDIO voltage level. The DIO line is called logic low if it is pulled down to the VSS voltage level. A low signal at the DIO line wakes-up the IC. The circuit enters the standby mode if either of these three conditions are fulfilled: 1. After power-on-reset and the DIO is high (see Figure 3-1) 2. After a time out of TOUTL(1) during which DIO is permanently low (see Figure 3-3 on page 5) 3. After a time out of TOUTH(2) during which DIO is permanently high and an acknowledge time TACK/TERR(1) (see Figure 3-2)
Notes: 1. Time does not depend on the antenna resonance frequency. 2. Time depends on the antenna resonance frequency.
Figure 3-1.
STBY After POR
STBY
t DIO
t POR
t
Figure 3-2.
STBY After DIO = H
STBY
t
TOUT_H TACK/TERR
DIO
t
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ATA5275 [Preliminary]
Figure 3-3. STBY After DIO = L
TOUT_L
STBY
t DIO
t
3.3
3.3.1
Transmission Mode
ASK Modulation For the transmission of a wake-up signal or data to a receiver, the ATA5275 generates a antenna resonance synchronized signal at the antenna driver output (DRV pin). A connected LC antenna radiates a magnetic field. For the data transmission the field can be 100% amplitude modulated by the DIO interface input. If a low level signal is applied at the DIO pin, the driver generates a square wave signal DRV for the antenna. If a high level signal is applied at the DIO pin the driver is stopped and switched to ground. In this way ASK modulated data can be transmitted (see Figure 3-4). Figure 3-4.
DIO
Data Transmission
DRV
COIL
3.3.2
Anti-bouncing Filter in Transmission Mode The DIO input signal is delayed for a anti-bouncing time. The driver is switched on after a delay time of TDL (typically 64 s) if the DIO is pulled to a low level continuously. The driver is switched-off after a delay time of TDH if the DIO is pulled to high level. The TDH time depends on the antenna resonance frequency, suppressing short disturbance pulses from the DIO Line. Figure 3-5. Anti-bouncing
TD_L TD_H
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3.3.3
Time Out and Time Out Reset The IC has a time out supervisor for the interface line to avoid unintended continuous transmission in case of line errors. The time out timer runs if the DIO pin is pulled to a low level. If the DIO pin is permanently low for more than the time TOUTL the driver is switched off and the IC enters the standby mode. This avoids the discharging of the supply battery if the DIO line has a failure like a body contact or another permanent low level failure. The time TOUTL depends on the antenna resonance frequency. Figure 3-6. Time Out and Time Out Reset Protocol
Transmission Delay
Standby
Time Out TD_L TOUT_L
Standby
Timeout Reset TOR
Time Out Reset Periode TORP TD_H
Transmission Delay
DIO
DRV
For continuous transmission periods the internal time out timer must be reset within the time out reset period TORP with a short high pulse of length TOR at DIO. Any transmission time periods can be made by cyclical resetting of the time out timer (see Figure 3-6). The time TORP and TOR depends on the antenna resonance frequency. 3.3.4 Transmission Acknowledge and Error Signal If no failure is detected during a transmission sequence the IC acknowledges the transmission by pulling the DIO line to low level for time TACK (typically 256 s). The acknowledge signal is generated at the end of a transmission sequence if the DIO line was high for the time TOUTH (typically 16 ms). Their are two types of error detection (see section "Diagnosis and Protection"): * Immediate switch-off of the driver stage * The failure is indicated through the DIO line based on transmission acknowledge and Error signal At the end of transmission the IC indicates the failure by an error signal by pulling the DIO line to a low level for time TERR (typically 128 s) instead of TACK. With the acknowledge and the error signal a connected microcontroller is able to recognize failures of the IC or the antenna module as well as DIO line failures like a broken wire or a short circuit.
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ATA5275 [Preliminary]
Figure 3-7. Transmission Acknowledge and Error Signal
Time Out TOUT_H Acknowledge TACK Failure Detection TDFx Time Out TOUT_H Error Signal TERR
DIO
DRV
Failure
COIL
The various failure types are monitored during transmission in time TFDx (see section "Diagnosis and Protection"). The time TFDx depends on the antenna resonance frequency.
3.4
Internal Voltage Regulator and POR
The IC contains a 5-V regulator. It is used for the supply voltage VCC of the logic circuits and the low voltage analog circuits. Additionally, the VCC can be used externally for loads up to 10 mA. The stabilized voltage is available at pin VCC and must be buffered with an external capacitor.
3.4.1
Reset After power on or after a voltage breakdown the power-on-reset circuit of the IC generates a reset pulse which sets the logic circuit to a defined initial state. A RESET is generated if the VCC is below the reset threshold voltage VPOR and after power on.
3.4.2
DIO Interface The interface can be operated either as a 5-V microcontroller interface or as automotive K-line interface with the car battery voltage. In which mode it operates must be selected with the VDIO pin. If it is connected to 5 V the DIO pin operates as microcontroller interface and if it is connected with the battery voltage it operates as automotive interface according to the K-line specification.
3.5
Oscillator and Carrier Frequency Generation
A Voltage Controlled Oscillator (VCO) is used to clock the interface logic and the gate driver logic. The antenna driver output signal DRV is derived from this clock. The VCO operates in two modes: the self-oscillation mode with clock CLKSO and the resonance tracking mode with clock CLKRT.
3.5.1
Self-oscillating Mode If the antenna half-bridge is not activated the VCO is in self-oscillating mode. It runs at a center frequency CLKSO of typically 125 kHz with an accuracy of 8%. For that purpose, an external reference resistor has to be applied to pin REXT. The resistor at pin REXT determines the VCO frequency proportionally. The recommended value is 100 k achieving 125 kHz oscillator frequency.
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3.5.2
Resonance Tracking Mode In case the antenna half-bridge is activated the VCO is tracked by the antenna current by means of it zero crossing detection. The VCO runs at the antenna resonance frequency stationary. The clock CLKRT deviates 1.4% from the antenna resonance frequency, depending on the antenna quality and resonance frequency (see section "Application Hints"). For that purpose, an antenna current shunt resistor has to be applied to the SENSE pin. The shunt resistance is used internally for the zero crossing detection of the antenna current only. By this feature the antenna operates with the maximum voltage, current and field strength. It is recommended specially for systems with high antenna Q-factors and low LC tolerances.
3.6
Coil Driver Output and Antenna Peak Current Control
The driver circuit consists on a DMOS half-bridge designed for 1.5 A peak current with low onresistance RDSON. It is short-circuit and overtemperature protected (see section "Diagnosis and Protection"). The half-bridge is switched on by a low level signal at DIO and generates a square wave voltage for the antenna RLC circuitry. A very useful function of the driver stage is the build-in antenna current control loop. The IC senses the current through the antenna internally and controls the peak value IAPEAK by controlling the duty cycle DCDRV of the driver output. So the antenna can be designed for maximum antenna current with the typical or even the minimum supply voltage. For higher supply voltages the current is controlled by reducing the driver duty cycle. The reference value for the antenna current IAPEAK can be adjusted externally with a resistor RCR at the RCR pin. 50 k IA PEAK = 750 mA x -------------R CR
Note: Applying the formula above, the right driver current for the antenna has to be adjusted for the worst supply voltage case. The IC operates from 14% up to 86% duty cycle for that case and reduces the duty cycle for higher voltages (for the definition of the duty cycle DCDRV, see "Application Hints" on page 13).
This feature allows the user to operate the IC in a wide field of operational voltage field and protects the driver stage and the antenna from antenna overcurrent. The driver out square wave starts with a duty cycle of 50%. After tree or four cycles the duty cycle can reach its maximum. As far as the peak current will stay smaller than IApeak this duty cycle maximum is really 100%. If during the ramp up of the antenna current the envelope of the peak current will be greater than IApeak + 20% a pulse skipping function will suppress the next driver output pulse to minimize the antenna current overshoot.
3.7
Diagnosis and Protection
The IC supervises several parameters of IC operation for transmission diagnosis and circuit protection. In any case of circuit protection mode or error detection the IC indicates this states according to the transmission protocol via the DIO line (see chapter "Transmission Acknowledge and Error Signal" on page 6).
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3.7.1 Circuit Protection Cases The circuit protection is activated in normal mode. It is switched off in standby mode. In case a protection switch-off occurs the half-bridge is set in tri-state mode. For all cases, there is a filter implemented to debounce half-bridge switch-off for a time of TDEB (typically 20 s). This debounce filter is activated in case the half-bridge is activated. Otherwise it is RESET. These are the following circuit protection cases: 1. Load dump protection: In case the voltage at DVCC exceeds a voltage VBATLD (typically 31 V). 2. Overcurrent protection: In case the current through the high side DMOS of the halfbridge exceeds a value of IOCH or the current through the low side DMOS of the halfbridge exceeds a value of IOCL (typically 2 A). 3. Overtemperature protection: In case the junction temperature exceeds a value of TSD (typically 165C). 3.7.2 Error Diagnosis During the transmission the diagnosis function of the IC supervises the antenna current and frequency and the half-driver bridge supply voltage. If any error is detected at the end of the transmission cycle the error indication is set (as in circuit protection case). There are the following diagnosis cases: 1. Under-voltage detection: Monitors if DVCC is below VBATUV (typically 6.5 V). 2. Antenna frequency error: Diagnosis if the oscillation frequency during transmission is outside the typical tracking range 90 kHz to 160 kHz. 3. Antenna peak current error: Diagnosis if the peak current is greater than the adjusted IAPEAK + 15% typically.
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4. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Ground Power ground Reverse protected battery voltage Half-bridge driver output Bootstrap 5-V regulator output Analog reference input Digital test mode DIO interface supply DIO interface Zero crossing analog input Electromagnetic Interference Minimum ESD protection (100 pF through 1.5 k) Power dissipation Junction temperature Storage temperature Ambient temperature range under bias Ptot Symbol VSS DVSS1,2,3 DVCC1,2,3 DRV1,2,3 BOOST VCC REXT RCR TM1,2,3 VDIO DIO SENSE EMI Min. 0 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -2 Max. 0 +0.3 +44 DVCC + 0.3 DVCC + 6 +7 VCC + 0.3 VCC + 0.3 VCC + 0.3 DVCC + 0.3 DVCC + 0.3 DVCC + 0.3 250 2 (on PCB) 2(1) 150 -55 -40 +125 +105 220 + 5
(2)
Unit V V V V V V V V V V V V V/M kV W C C C C
j STORE
ambient
Soldering temperature (10 s) SOLDERING Notes: 1. May be limited by external thermal resistance.
2. If the low side driver is switched on, it is not allowed to connect a voltage source to pin BOOST.
5. Thermal Resistance
Parameters Thermal resistance, junction ambient Symbol RthJA Value 35 Unit K/W
6. Operating Range
The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied if not otherwise stated explicitly. Parameters Operating supply voltage Operating temperature range Symbol VVBAT1 amb Value 8 to 24 -40 to +105 Unit V C
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ATA5275 [Preliminary]
7. Electrical Characteristics(1)
No. 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2 2.1 2.2 2.3 2.4 Parameters Power Supply Main supply voltage Supply current Standby current Power-on-reset threshold voltage Load dump protection voltage Under voltage detection Thermal shut down Protection debounce filter Half-bridge Driver Stage Coil driver resistance low side driver Coil driver resistance high side driver Overcurrent protection threshold low side Overcurrent protection threshold high side 10% to 90% slope time, 0% = DVSS, 100% = DVCC DVCC = 12 V (smooth edges) 10% to 90% slope time, 0% = DVSS, 100% = DVCC DVCC = 12 V (smooth edges) DRV, DVSS DVCC, DRV DRV, DVSS DVCC, DRV RDSONL RDSONH IOCL IOCH 1.5 1.5 0.3 0.3 1.9 1.75 0.7 0.7 2.2 2.2 A A A A A A I(VCC) = 10 mA, including load and line regulation without antenna load Pin DVCC = 13.5 V, Tamb = 90C VCC DVCC DVCC VCC DVCC DVCC VCC ISUPP ISTBY VPOR VBATLD VBATUV TSD TDEB 4.7 2 20 3.5 29 6.0 150 5 5.0 10 35 4 31 6.5 165 15 5.3 20 60 4.5 35 7.0 180 25 V mA A V V V
o
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
A A B A A A B C, D
C
s
2.5
Driver output rise time
DRV
TDRV,RISE
50
100
150
ns
D
2.6
Driver output fall time
DRV
TDRV,FALL
50
100
150
ns
D
3 3.1 3.2 3.3
Antenna Peak Current Control Duty cycle control range Peak current control reference Peak current control accuracy RCR = 25 k DRV RCR DCDRV(2) VRCR IApeak 15 1.15 1.0 1.215 1.3 85 1.28 1.8 % V A B A B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. 8 V < V(DVCC) < 24 V; -40 C < amb < 105 C, unless otherwise specified; all values refer to GND 2. Definition of DCDRV see "Application Hints" on page 13
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7. Electrical Characteristics(1) (Continued)
No. 3.4 3.5 4 4.1 Parameters Antenna peak under current threshold Antenna peak overcurrent threshold Test Conditions 0% NOM value = IAacc RCR = 25 k 0% NOM value = IAacc RCR = 25 k Self oscillating mode = half-bridge not activated Tracking frequency mode = half-bridge activated Antenna resonance frequency range = 100 kHz to150 kHz, antenna quality = 5 to 50 -240 ns A +240 ns Pin Symbol IAUC IAOV Min. -30 30 Typ. -20 20 Max. -10 10 Unit % % Type* A A
Oscillator and Phase Control VCO initial frequency CLKSO 115 125 135 kHz A
4.2
VCO frequency tracking range Phase shift between voltage at DRV and zero crossing of current through SENSE Phase control set-up time High frequency failure threshold Low frequency failure threshold DIO Interface VDIO leakage current
CLKTR
80
200
kHz
B
4.3
DRV, SENSE
A
-120
0
+120
ns
B
4.4 4.5 4.6 5 5.1
DRV, SENSE DRV DRV
Tsetup fVCOH fVCOL 150 80 160 90
160 200 105
s kHz kHz
D A A
Pin VDIO = 13.5 V, Pin DIO = 13.5 V Tamb = 90C Pin VDIO = 13.5 V, Pin DIO = 13.5 V Tamb = 90C IDIO = 20 mA 100% = DVCC 100% = DVCC
VDIO
IVDIO,STBY
2
4
5
A
A
5.2 5.3 5.4 5.5 5.6 6 6.1 6.2 6.3 6.4
DIO leakage current DIO sink current Output low level Input low level threshold Input high level threshold Transmission Protocol LF data baud rate Anti-bouncing time for activate half-bridge Anti-bouncing time for de-activate half-bridge Acknowledge pulse width
DIO DIO DIO DIO DIO
IDIO,LEAK IDIO,LIMIT VDIOL VDIO,THL VDIO,TLH
2 36
4 44 1.2
200 52 1.5 70 70
A mA V %V (VDIO) %V (VDIO) kbit/s s s s
A A A A A
30 30
45 50
BdRF DIO = H L, for fVCO = 125 kHz DIO = L H, for fVCO = 125 kHz TDL TDH TACK
1 64 64 256
4
C, D B B B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. 8 V < V(DVCC) < 24 V; -40 C < amb < 105 C, unless otherwise specified; all values refer to GND 2. Definition of DCDRV see "Application Hints" on page 13
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ATA5275 [Preliminary]
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ATA5275 [Preliminary]
7. Electrical Characteristics(1) (Continued)
No. 6.5 Parameters Error signal pulse width Transmission time out de-activated halfbridge Transmission time out activated half-bridge Time out reset pulse width Time out reset pulse period Test Conditions Pin Symbol TERR TOUTL TOUTH TOR TORP Min. Typ. 128 Max. Unit s Type* B
6.6
16
ms
B
6.7 6.8 6.9
16 32 15
ms s ms
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. 8 V < V(DVCC) < 24 V; -40 C < amb < 105 C, unless otherwise specified; all values refer to GND 2. Definition of DCDRV see "Application Hints" on page 13
8. External Components
The following external components have to be applied to the circuit for functional operation. Component Rext RCR C0 CRF CB RS RDIO Notes: 1. For EMC reasons only. 2. Sensitivity at input SENSE is proportional to resistor Rs times antenna peak current. 3. For antenna peak value 1.5 A. 4. Recommended range: RCR = 25 to 100 k. Pin REXT RCR
(4)
Min. 25
Typ. 100
Max. 200
Unit k k F nF
VCC VCC(1) BOOST SENSE DIO
(2)
22 100 0.68 0.1
(3)
1 0.5 1
2 1 6
nF k
0.6
9. Application Hints
A typical application of ATA5275 is shown in Figure 9-1 on page 14. The peak value of the antenna current can be estimated by the formula: 2 V DVCC I A = -- x ----------------- x sin -- x DC DRV x cosA 2 RA Here RA denotes the equivalent series resistance of the driver load, i.e., the external coil series resistance in series with the shunt resistance and the internal drain-source-on-resistance of the NDMOS. The duty cycle DCDRV is the ratio of the driver high-side on-time with respect to the half of the oscillation period. The phase difference A is measured as the time difference between the point of mass of VDRV and the peak value of the antenna current.
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Figure 9-1.
14
D1 C1 C2 DRV 20 DVCC3 19 BOOST 18 VCC CDIO 17 DIO 16 VDIO C3 RDIO L1
VBATT
8 to 24 V
Application Circuit
GND
1 DVCC2 Refe5V Reg. rences RefExt KLine 14 TM2 State Machine BUS Cursa 3 DRV3 Gate Driver Control Half Bridge 125 kHz Transmitter Current CLK Sense DRV 15 TM1
ATA5275 [Preliminary]
2 DVCC1 Microcontroller or ECU 13 TM3 CAnt 4 DRV2 Duty ON/ Cycle Regu OFF lator VCO 11 REXT 12 RCR RCR LAnt 5 DRV1 RS 6 DVSS3 RSHUNT 7 DVSS2 8 DVSS1 9 SENSE 10 VSS REXT
LF Receiver
Note: For the typical values of the external components, see table "Electrical Components" on page 13.
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ATA5275 [Preliminary]
10. Ordering Information
Extended Type Number ATA5275-PGQ Package QFN20, 5 mm x 5 mm Remarks -
11. Package Information
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4739C-AUTO-02/05

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