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| Semiconductor MSM5718B70 Semiconductor 18-Megabit RDRAM (2M 9) MSM5718B70 E2G1033-17-54 DESCRIPTION The 18-Megabit RambusTM DRAM (RDRAMTM) is an extremely high-speed CMOS DRAM organized as 2M words by 9 bits. It is capable of bursting up to 256 bytes of data at less than 2 nanoseconds per byte. The use of Rambus Signaling Logic (RSL) technology makes transfer rates greater than 500 MHz achievable while using conventional system and board design methodologies. Lower effective latency is attained by operating the dual 2KByte sense amplifiers as high speed caches, and by using random access mode to facilitate large block transfers. RDRAMs are general purpose high-performance memory devices suitable for use in a broad range of applications including PC and consumer main memory, graphics, video, and any other application where high-performance is required. FEATURES * Rambus Interface: Over 500 MB/sec peak transfer rate per RDRAM Rambus Signaling Logic (RSL) interface Synchronous protocol for fast block-oriented transfers Direct connection to Rambus ASICs, MPUs, and Peripherals 15 active signals require just 32 total pins on the controller interface (including power) 3.3 V operation Additional/multiple Rambus Channels provide an additional 500 MB/second band-width each * Dual 2KByte sense amplifiers may be operated as caches for low latency access * Random Access mode enables any burst order at full band width * Features for graphics include random-access mode, write-per-bit and mask-per-bit operations * Control and refresh logic entirely self-contained * On-chip registers for flexible addressing and timing * Available in horizontal surface mount plastic package (SHP32-P-1125-0.65-K) 1 MSM5718B70 Semiconductor RDRAMs RModule RSocket Rambus Channel Controller Fig. 1 Rambus Subsystem SYSTEM BENEFITS * Fully engineered solution includes clock chips, memory expansion sockets and simple layout * For graphics subsystems addressing display resolutions of 1024 768 8 or above, it provides high performance, fewest controller pins, and ease of memory expansion * For Pentium(R) processor class main memory, it provides fast memory subsystem, fewer components, and 2 MB granularity * Sufficient performance for unified memory system architectures in consumer applications PART NUMBERS The 18-Megabit RDRAMs are available in horizontal surface mount plastic package (SHP), with a 500 MHz clock rate, a 533 MHz clock rate and a 600 MHz clock rate. The part numbers for the various options are shown in Table 1. 2 Semiconductor Table 1 Part Numbers 500 MHz 533 MHz 600 MHz MSM5718B70 MSM5718B70-50GS-K MSM5718B70-53GS-K MSM5718B70-60GS-K Controller Vdd SIn RDRAM 1 SOut SIn RDRAM n SOut NC Vterm BusData [8:0] BusCtrl, BusEnable ClkFromMaster ClkToMaster Vref Gnd, GndA Vdd, VddA Rambus Channel = 9 bits every 2 ns Fig. 2 Controller and RDRAMs Connect to Terminated Transmission Lines RAMBUS SYSTEM OVERVIEW A typical Rambus memory system has three main elements: the Rambus Controller, the channel, and the RDRAMs. The logical representation of this is shown in Fig. 2. The Rambus channel is a high-speed, byte-wide, synchronous bus used to connect Rambus devices together. The channel carries all address, data, and control information to and from devices. Transfer of data on the Rambus channel is managed through the use of a high level block-oriented protocol. 3 MSM5718B70 Semiconductor Bank 7 Bank 5 Bank 3 Bank 1 Bank 8 Bank 6 Bank 4 Bank 2 RDRAM 4 RDRAM 3 Sense Amp Cache page 1 Sense Amp Cache page 2 RDRAM 2 RDRAM 1 Registers Address Comparators Clocking Byte h Byte g Byte f Byte e Byte d Byte c Byte b Byte a Rambus Channel 9 bits every 2 ns Rambus Interface Cell * Macrocell in embedded array and standard cell libraries * Converts Rambus channel small swing signals to ASICcore-compatible CMOS levels * Converts 9 bits every 2 ns to 72 bits (X2) every 16 ns * Contains PLLs abcdefgh Fig. 3 Data Transfer on the Rambus Channel The Rambus channel has thirteen high-speed Rambus Signaling Logic (RSL) I/O signals that are used to transfer information at 2 nanosecond intervals. These signals use low voltage swings (logic 0 = 2.25 V, logic 1 = 1.55 V) to achieve high bus speeds. Two TTL level signals are used for initialization and powerdown operation. Fourteen signals supply power and DC voltage references to the RDRAM, and the remaining pins are No Connects (reserved for future expansion). The Rambus interface is implemented on both master and slave devices. Rambus masters (ASIC devices, memory controllers, graphics engines, peripheral chips, or microprocessors) are the only devices capable of generating transaction requests. RDRAMs are slave devices and can respond to requests from master devices. Fig. 1 shows a typical physical implementation of a Rambus system. It includes a controller ASIC that acts as the Channel master and a base set of RDRAMs soldered directly to the board. An RSocketTM is included on the Channel for memory upgrade using RModuleTM expansion cards. 4 Semiconductor MSM5718B70 RDRAM PACKAGES AND PINOUTS RDRAMs are available in horizontal surface mount plastic package (SHP). The package has 32 signal pins and four mechanical pins that provide support for the device. The mechanical pins are located on the opposite side from the signal leads in the SHP. VDD Gnd BusData8 Gnd BusData7 (NC) BusEnable VDD BusData6 Gnd BusData5 VDDA RxClk GndA TxClk VDD BusData4 Gnd BusCtrl SIn VREF SOut BusData3 Gnd BusData2 (NC) BusData1 Gnd BusData0 (NC) Gnd VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Fig. 4 SHP Pin Numbering 5 MSM5718B70 Table 2 Pin Descriptions Signal I/O Description Semiconductor BusData [8-0] I/O Signal lines for request, write data, and read data packets. The request packet contains the address, operation codes, and the count of the bytes to be transferred. These are low-swing active-low signals referenced to Vref. Receive clock. Incoming request and write data packets are aligned to this clock. This is a low-swing active-low signal referenced to Vref. Transmit clock. Outgoing acknowledge and read data packets are aligned with this clock. This is a low-swing active-low signal referenced to Vref. Logic threshold reference voltage for low swing signals. Control signal to frame packets transmit part of the operation code to acknowledge requests, and to interrupt (terminate) pending transactions. This is a low-swing active-low signal referenced to Vref. Control signal to manage the operating modes of the RDRAMs and to transfer column addresses for random-access (non-sequential) transactions. This is a low-swing active-low signal referenced to Vref. +3.3V power supply. VddA is a separate analog supply for clock recovery in the RDRAM. Circuit ground. GndA is a separate analog ground for clock generation in the RDRAM. Initialization daisy chain input. TTL levels. Active high. Initialization daisy chain output. TTL levels. Active high. RxClk TxClk Vref BusCtrl I I I I/O BusEnable Vdd, VddA Gnd, GndA SIn SOut I I O Mechanical Pins Pin 1 Mechanical Pins Pin 32 Fig. 5 SHP Package 6 Semiconductor MSM5718B70 PROTOCOL The transaction protocol used in Rambus systems is built from several types of information packets. These include the request, acknowledge, serial mode, and data packets. Request Packet A master device initiates a transaction by generating a six-byte request packet containing address, control, and byte count information as shown in Fig. 6. The Op and OpX fields in the Request packet contain a command that is used to instruct the RDRAM which operation is being requested. A summary of these commands is shown in Table 3. Clock Cycle Number even [1] odd [2] even [2] odd Time Bus- BusEnable Ctrl [0] -- Start Op[0] even [0] -- Op[1] Op[3] odd [1] -- OpX[1] -- -- -- Op[2] OpX[0] ReqUnimp[5:4] ReqUnimp[8:6] BusData (8:0) Adr[9:2] Adr[17:10] Adr[26:18] Adr[35:27] Count[6, 4, 2] Count[7, 5, 3] ReqUnimp[3:0] Count[1:0] Adr[1:0] Fig. 6 Request Packet 1 Note: 1. A -- in this diagram signifies that this pin is not used by this packet. If it is not used by another packet, it is pulled to a logic zero value. 7 MSM5718B70 Table 3 Command Summary Op[3:0] 0000 0000 0100 0100 OpX[1:0] 00 01 00 01 Name Rseq Rnsq WseqNpb WseqDpb Description Read sequential data from memory space. Semiconductor Read random-access (non-sequential) data from memory space. Write sequential data to memory space with no per-bit mask application. Write sequential data to memory space with data-per-bit masking. Static bit masks are supplied by the MDReg while write data is supplied in the data packet. Write sequential data to memory space with mask-per-bit masking. Both write data and dynamic bit masks are supplied in the data packet. Write sequential data to memory space with mask-per-bit masking. Static write data is supplied by the MDReg while dynamic bit masks are supplied in the data packet. Read data from register space. Write data to register space. Write random-access (non-sequential) data to memory space with no perbit mask application. Write random-access (non-sequential) data to memory space with data-perbit masking. Static bit masks are supplied by the MDReg while write data is supplied in the data packet. Write random-access (non-sequential) data to memory space with maskper-bit masking. Both write data and dynamic bit masks are supplied in the data packet. 0100 0100 0110 0111 1000 1000 10 11 00 00 00 WseqBpb WseqMpb Rreg Wreg WnsqNpb 01 WnsqDpb 1000 10 WnsqBpb 1000 11 Write random-access (non-sequential) data to memory space with maskWnsqMpb per-bit masking. Static write data is supplied by the MDReg while dynamic bit masks are supplied in the data packet. WbnsNpb Write random-access (non-sequential) data to memory space with byte masking and no per-bit mask application. Both byte masks and write data are supplied in the data packet. Write random-access (non-sequential) data to memory space with byte masking and data-per-bit masking. Static bit masks are supplied by the MDReg while byte masks and write data are supplied in the data packets. 1100 00 1100 01 WbnsDpb 1100 11 Write random-access (non-sequential) data to memory space with byte masking and mask-per-bit masking. Static write data is supplied by the WbnsMpb MDReg while byte masks and dynamic bit masks are supplied in the data packets. WregB Broadcast write to register space of all responding devices with no acknowledge permitted. 1111 00 8 Semiconductor Acknowledge Packet MSM5718B70 Each RDRAM monitors the channel for a request to access its assigned memory range. The device matching the address range requested then drives an acknowledge packet back to the master. Clock Cycle Number Bus- BusEnable Ctrl [0] -- Ack[0] even [0] -- Ack[1] BusData (8:0) -- -- odd Time Fig. 7 Acknowledge Packet1 Note: 1. A -- in this diagram signifies that this pin is not used by this packet. If it is not used by another packet, it is pulled to a logic zero value. The Ack[1:0] field in the Acknowledge packet carries the RDRAM's response to the request. If the RDRAM is able to complete the operation as requested, it returns an okay response. If the RDRAM is unable to complete the operation as requested, it returns a negative acknowledge response (Nack). The encoding of the Ack[1:0] bits is shown in Table 4. Table 4 Ack[1:0] Encodings Ack [1:0] 00 01 10 11 Name Nonexistent Okay Nack Ack3 Description Indicates passive acceptance of the request (WregB), or indicates that the addressed device did not respond (all other commands). Indicates that the request was accepted by the addressed (responding) device. Indicates that the request could not be accepted because the state of the responding device prevented an access at the fixed timing slot. This should not be returned by this responding device. Initiating devices will, when presented with this combination, have an undefined response. In response to an acknowledged command, the RDRAM either drives a data packet back to the master in the case of a read, or accepts a data packet from the master in the case of a write. Fig. 8 shows an example of 16 byte read and write transactions. The actual timing from the end of a request packet to data and acknowledge packets is adjustable through RDRAM register settings. 9 MSM5718B70 Semiconductor 1tCYCLE 3tCYCLE 7tCYCLE 3tCYCLE Read Request 1tCYCLE Ack Read Data Write Request Ack Write Data Fig. 8 Sample 16-Byte Read and Write Transactions 10 Semiconductor Serial Address Packet MSM5718B70 The non-sequential (Random Access) commands specify the eight column address bits needed to access random octbytes within the open page. These address bits are provided using a Serial Address packet. Bus- BusEnable Ctrl SAdr -- [1][3] -- SAdr [1][4] SAdr -- [1][5] -- SAdr [1][6] SAdr -- [1][7] -- SAdr [1][8] SAdr -- [1][9] -- SAdr [1][10] BusData (8:0) -- -- -- -- -- -- -- -- [4] even [4] odd [5] even [5] odd [6] even [6] odd [7] even [7] odd Clock Cycle Number [4*n] even [4*n] odd [4*n+1] even [4*n+1] odd [4*n+2] even [4*n+2] odd [4*n+3] even [4*n+3] odd Time SAdr [n][3] SAdr [n][4] SAdr [n][5] SAdr [n][6] SAdr [n][7] SAdr [n][8] SAdr [n][9] SAdr [n][10] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Fig. 9 Serial Address Packet Format1 Note: 1. A -- in this diagram signifies that this pin is not used by this packet. If it is not used by another packet, it is pulled to a logic zero value. 11 MSM5718B70 Serial Control Packet Semiconductor The protocol also allows the channel master to issue an early termination instruction for a memory read or write transaction. This is done using a Serial Control packet. Bus- BusEnable Ctrl SCtrl -- [0] -- SCtrl [1] SCtrl -- [2] -- SCtrl [3] SCtrl -- [4] -- SCtrl [5] SCtrl -- [6] -- SCtrl [7] BusData (8:0) -- -- -- -- -- -- -- -- [0] even [0] odd [1] even [1] odd [2] even [2] odd [3] even [3] odd Time Clock Cycle Number Fig. 10 Serial Control Packet Format1 Note: 1. A -- in this diagram signifies that this pin is not used by this packet. If it is not used by another packet, it is pulled to a logic zero value. The value of the Serial Control field specifies whether the instruction should continue or terminate. This is shown in the table below. Table 5 Serial Control Field Serial Control Field SCtrl[7:0] SCtrl[7:0] Description Continue Terminate Value 00000000 00100000 12 Semiconductor Serial Mode Packet MSM5718B70 Serial Mode Packets are used to instruct the RDRAM to perform a operating mode change. A Serial Mode Packet is simply a pulse on the BusEnable line. 1tCYCLE 3tCYCLE 19tCYCLE 3tCYCLE 7tCYCLE Read Request (Miss) Nack Read Request (Hit) Ack Read Data Fig. 11 Sample 32-Byte Read Miss and Read Hit Transactions Clock Cycle Number [0] even [0] odd Time Bus- BusEnable Ctrl SMode -- [0] SMode -- [1] BusData (8:0) -- -- Fig. 12 Serial Mode Packet1 Note: 1. A -- in this diagram signifies that this pin is not used by this packet. If it is not used by another packet, it is pulled to a logic zero value. RDRAM OVERVIEW The figure on the next page is a block diagram of the RDRAM device. The Rambus channel interface consists of a clock generator, a receiver, and a transmitter. The clock generator uses the external clock signals RxClk and TxClk (tapped off the channel traces ClockFromMaster and ClockToMaster) and creates the internal signals RClk and TClk. These are used by the receiver and transmitter, respectively, to transfer a bit every 2 nanoseconds on each wire between the RDRAM and the master device. The receiver and transmitter blocks also contain multiplexing and storage hardware to permit the internal RDRAM data paths to operate at the slower clock rate (but equivalent bandwidth) of eight bytes transferred every 15 or 16 nanoseconds (four clock cycles). The RDRAM also contains control logic and configuration registers. The registers are read and written using special register space commands and control various aspects of RDRAM operation as described on page 19. The remaining logic consists of a standard DRAM memory core and row sense amplifier caches. 13 MSM5718B70 Rambus Channel Semiconductor ClockToMaster ClockFromMaster BusEnable, BusCtrl, BusData[8:0] 1 SIn 11 Receiver 11 RClk RxClk 1 SOut 1 TxClk TClk 10 Transmitter 10 1 Clock Generator Request, SMode, SAdr, SCtrl WriteData[7:0][8:0] Ack[1:0] ReadData[7:0][8:0] 72 72 37 25 8 Adr[10:3] Op[3:0] Internal Data Bus OpX[1:0] Adr[35:11] Adr[2:0] Count[7:0] Address Mapping Start, Close Logic SMode[1:0] SAdr[31:1][10:3] SCtrl[7:0] AddressSelect[3:0][8:0] Device Id Compare Deviceld[3:0][8:0] DeviceType[3:0][8:0] Delay[3:0][8:0] Mode[3:0][8:0] DeviceManufacture[3:0][8:0] Row[3:0][8:0] RefRow[3:0][8:0] MinInterval[3:0][8:0] RasInterval[3:0][8:0] 2 CoreAccess CoreRestore 8 CoreColAddr 72256 RowSenseAmpLatch 72256 72256512 DRAM Array - Bank 0 1 CoreBankAddr 9 CoreRowAddr 72 MDReg[7:0][8:0] 72 72 72 Command and Control Logic RowAddres Compare CoreAddres Compare Column Decoder 72 72256 RowSenseAmpLatch 72256 72256512 DRAM Array - Bank 1 Fig. 13 RDRAM Block Diagram 14 Row Decoder Semiconductor MSM5718B70 RDRAM OPERATION The RDRAM is composed of two independent banks of memory with each bank storing a full 1 Mbyte of data (see Fig. 13). Each of these banks has a 2KByte open page associated with it that is built out of sense amplifier arrays. These sense amplifiers hold the last accessed row of their associated bank in the sense amplifiers. This allows further accesses to the same row of memory to result in page hits. With the row already stored in the sense amplifiers, subsequent data can be accessed with very low latency. Each RDRAM added to a system adds two open pages to the memory system helping to increase hit rates. A page miss results when a row is accessed that is not currently stored as one of the open pages. When this happens, the requesting master is sent a NACK Acknowledge packet indicating the requested row is not yet available. The RDRAM then loads the requested row into the sense amplifiers and waits for the master to submit a retry of the previous request. Fig. 11 shows an example of a read miss followed by a read hit for a 32 byte memory read operation. The amount of time that is needed before the retry can be serviced depends on whether the data in the open page is clean or dirty. The sense amplifiers act as a "write back" cache in that data written to the open page is not written into the actual DRAM cells until the page is closed. If the data in an open page is clean (not previously written) when a new page is requested, the open page does not need to be written back into the DRAM. If the data in an open page is dirty, then additional time must be added to the miss retry delay to account for the writeback operation. ADDRESS MAPPING Address mapping hardware is provided to increase page hit rates by allowing system designers to easily perform n-way RDRAM interleaving. In a non-interleaved memory system, contiguous blocks of addresses follow each other in sequence in one RDRAM, which is then followed by the next RDRAM. Using address mapping, adjacent blocks of data (2K or greater) can be separated across several RDRAMs, and therefore across several open pages. This allows a more optimal mapping of the pages as caches and creates higher effective page hit rates. In a typical system containing, for example eight RDRAMs, hit rates could be expected to be as high as 95%. Address mapping is easily adjusted by writing a control register in each RDRAM. TRANSACTION CONCURRENCY Concurrent transactions can be used to optimize RDRAM utilization in high performance applications by taking advantage of available channel bandwidth during page miss latency periods. When a miss in one RDRAM takes place, that device will be busy loading a new row into one of its sense amp caches. The channel and all other RDRAMs will still be available for use. While waiting for the first RDRAM to finish loading its open page, a transaction to another RDRAM can be initiated. In systems where memory accesses can be queued, a tansaction can take place for any pending access residing in a different RDRAM. Pretouching can be used in systems where certain memory accesses are predictable, such as video applications. This is done when an application is finished with a particular RDRAM and about to access a different one. If the next access to an RDRAM is known in advance, a transaction can be first generated that will cause a row miss and prepare the RDRAM for its next access. When the device is next accessed, the required row of data will already be loaded in the open page and a page hit will take place. 15 MSM5718B70 Semiconductor RANDOM ACCESS MODE Non-contiguous blocks of memory can be accessed through the use of the read and write nonsequential (Random Access) operations. With these commands multiple eight-byte blocks (octbytes) of data within an open page can be accessed in any order. To do this, the master device sends a request packet specifying a non-sequential operation along with the address of the first octbyte to be accessed. The master device also generates a serial address packet (see Fig. 9) on the BusEnable signal that specifies the address of the next octbyte. Successive serial address packets continue to specify new addresses within the open page while data is continuously transferred until the access is complete. Random access mode can be used to satisfy the burst order of processors like the IntelTM PentiumTM at full RDRAM bandwidth. BIT MASKING Three forms of bit masking are available for memory write operations. These operations are referred to as data-per-bit (Dpb), mask-per-bit (Mpb), and both-per-bit (Bpb) masking. An eight-byte Mask Data register (MDReg) within the RDRAM is used to hold the static value of either mask or data information for these operations. The Mask Data register is an RDRAM internal register that is written by the Bpb commands, and is used by the Mpb and Dpb commands. With the Dpb operation, the MDReg is used to hold a static mask that is applied to all octbytes of data written to the RDRAM core. With the Mpb operation, the MDReg is used to hold an octbyte of static data that is masked by dynamic bit masks supplied in the data packets before being written to the RDRAM core. The Bpb operation requires data packets to alternate between mask and data octbytes. The even data packets (starting with data packet 0) carry bit masking information which is placed in the MDReg while the odd data packets carry the data to be masked by the latest contents on the MDReg. This type of operation is also used to set the MDReg for later use in Dpb and Mpb operations. Table 6 shows the source of the mask and data for each of the write commands. The first eight columns show the Wseq and Wnsq sequential and non-sequential (fandom-access) write commands. Each has four bit mask sub-commands: Npb, Dpb, Mpb, and Bpb. A write command consists of writing from one to 32 octbytes of data W[31:0]. Each octbyte of data is masked by an octbyte of bitmask Bit[31:0]; that is, if the bitmask bit is set, then the corresponding bit of write data is written. If the bitmask bit is clear, then the bit in memory is left unchanged. Each of the first eight columns of Table 6 shows the source of the up-to-32 octbytes of write data and bitmask for the eight write commands. The Npb commands use no bitmask at all - effectively the bitmask is all ones. The Dpb command takes a single octbyte of bitmask from the MDReg and applies it to all data octbytes that are written. The Dpb command does the reverse and takes a single octbyte of write data from the MDReg and writes it to each octbyte of memory using a different bitmask from the data packet. The Bpb commands take an octbyte of bitmask and an octbyte of write data alternately, and writes them to a single octbyte of memory. 16 Semiconductor MSM5718B70 BYTE MASKING Contiguous byte masking is supported by the WseqNpb command. This command uses the Adr[2:0] and Count[2:0] fields of the request packet (Fig. 6) to specify the byte masks of the first and last octbytes of a data packet. The RDRAM also supports a more general form of byte masking called non-contiguous byte masking. This is available with the Wbns write commands. As can be seen in column nine of Table 6 for the WbnsNpb command, the first data packet, and every ninth thereafter, contain byte masking information that is applied to the eight data packets that follow. This means data packets 0, 9, 19, and 27 (gray boxes in the table) are not written to memory, but are instead used as byte masks for the eight octbytes of data that follow. This means that the data packet Data [35:0] may consist of up to 36 octbytes of information: 4 octbytes of byte mask information and 32 octbytes of data that is actually written to memory. Each bit of the 64-bit byte mask (one octbyte) controls whether a byte of the following 64 bytes of data (eight octbytes) is written (one) or not written (zero) to memory. Static bit masking is also available with non-contiguous byte masking. This is shown in the last two columns of Table 6 labeled WbnsDpb and WbnsMpb. The WbnsDpb command applies a static bit held in the MDReg to each octbyte of data W[31:0]. Each bit of the data octbyte is written if the corresponding bits of both the bitmask and bytemask are a one, and is not written if either is a zero. The WbnsMpb command applies a different bitmask Bit[31:0] to a static data octbyte held in the MDReg. Each bit of the data octbyte is written if the corresponding bits of both the bitmask and bytemask are a one, and is not written if either is a zero. Figure 14 shows how the bits of each Data[i][[7:0][8:0] octbyte are flow through the wire circuitry as a function of the operation type. The data W[i][j][8:0] is written if the corresponding Bit[i][j][8:0] and Byte [i][j] mask bits are set. Write data to RDRAM sense amplifier MDreg 0 1 mux W[i][j][8:0] 9 0 1 Mpb mux 9 Bit[i][j][8:0] Data[i][j][8:0] Bpb Even octbyte 9 ByteMask 1 63 used by other bytes 9x Npb 9x Byte[i][j] 9x Wbns i = {0, 1, ..., n-1} Data octbyte index j = {0, 1, ..., 7} Byte index k = {0, 1, ..., 8} Bit index Wbns 0,9,18,27 octbyte DQ[i][j][8:0] 9 Fig. 14 MDReg with BitMask and ByteMask Logic - one byte slice 17 MSM5718B70 Semiconductor Table 6 WriteData, BitMask, and ByteMask Sources2 Data Wseq Wseq Wseq Wseq Wnsq Wnsq Wnsq Wnsq Octbyt Npb Dpb Mpb Bpb Npb Dpb Mpb Bpb MDReg Data[0] Data[1] Data[2] Data[3] Data[4] Data[5] Data[6] Data[7] Data[8] Data[9] -- W[0] W[1] W[2] W[3] W[4] W[5] W[6] W[7] W[8] W[9] Bit [35:0] W[0] W[1] W[2] W[3] W[4] W[5] W[6] W[7] W[8] W[9] W [35:0] Bit[0] Bit[1] Bit[2] Bit[3] Bit[4] Bit[5] Bit[6] Bit[7] Bit[8] Bit[9] -- Bit[0] W[0] Bit[1] W[1] Bit[2] W[2] Bit[3] W[3] Bit[4] W[4] Bit[5] W[5] Bit[6] W[6] Bit[7] W[7] Bit[8] W[8] Bit[9] W[9] -- W[0] W[1] W[2] W[3] W[4] W[5] W[6] W[7] W[8] W[9] Bit [35:0] W[0] W[1] W[2] W[3] W[4] W[5] W[6] W[7] W[8] W[9] W [35:0] Bit[0] Bit[1] Bit[2] Bit[3] Bit[4] Bit[5] Bit[6] Bit[7] Bit[8] Bit[9] -- Wbns Npb -- Wbns Dpb Bit [35:0] W[0] W[1] W[2] W[3] W[4] W[5] W[6] W[7] W[8] W[9] W[10] W[11] W[12] W[13] W[14] W[15] W[16] W[17] W[18] W[19] W[20] W[21] W[22] W[23] W[24] W[25] W[26] W[27] W[28] W[29] W[30] W[31] Wbns Mpb W [35:0] Bit[0] Bit[1] Bit[2] Bit[3] Bit[4] Bit[5] Bit[6] Bit[7] Bit[8] Bit[9] Bit[10] Bit[11] Bit[12] Bit[13] Bit[14] Bit[15] Bit[16] Bit[17] Bit[18] Bit[19] Bit[20] Bit[21] Bit[22] Bit[23] Bit[24] Bit[25] Bit[26] Bit[27] Bit[28] Bit[29] Bit[30] Bit[31] Bit[0] ByteM[7:0] ByteM[7:0] ByteM[7:0] W[0] Bit[1] W[1] Bit[2] W[2] Bit[3] W[3] Bit[4] W[4] Bit[5] W[5] Bit[6] W[6] Bit[7] W[7] Bit[8] W[8] W[9] W[0] W[1] W[2] W[3] W[4] W[5] W[6] W[7] W[8] W[9] W[10] W[11] W[12] W[13] W[14] W[15] W[16] W[17] W[18] W[19] W[20] W[21] W[22] W[23] W[24] W[25] W[26] W[27] W[28] W[29] W[30] W[31] ByteM[15:8] ByteM[15:8] ByteM[15:8] Data[10] W[10] W[10] Bit[10] Data[11] W[11] W[11] Bit[11] Data[12] W[12] W[12] Bit[12] Data[13] W[13] W[13] Bit[13] Data[14] W[14] W[14] Bit[14] Data[15] W[15] W[15] Bit[15] Data[16] W[16] W[16] Bit[16] Data[17] W[17] W[17] Bit[17] Data[18] W[18] W[18] Bit[18] Data[19] W[19] W[19] Bit[19] W[10] W[10] Bit[10] W[11] W[11] Bit[11] W[12] W[12] Bit[12] W[13] W[13] Bit[13] W[14] W[14] Bit[14] W[15] W[15] Bit[15] W[16] W[16] Bit[16] W[17] W[17] Bit[17] W[18] W[18] Bit[18] W[19] W[19] Bit[19] Bit[9] ByteM[23:16] ByteM[23:16] ByteM[23:16] Data[20] W[20] W[20] Bit[20] Bit[10] Data[21] W[21] W[21] Bit[21] W[10] Data[22] W[22] W[22] Bit[22] Bit[11] Data[23] W[23] W[23] Bit[23] W[11] Data[24] W[24] W[24] Bit[24] Bit[12] Data[25] W[25] W[25] Bit[25] W[12] Data[26] W[26] W[26] Bit[26] Bit[13] Data[27] W[27] W[27] Bit[27] W[13] Data[28] W[28] W[28] Bit[28] Bit[14] Data[29] W[29] W[29] Bit[29] W[14] Data[30] W[30] W[30] Bit[30] Bit[15] Data[31] W[31] W[31] Bit[31] W[15] Data[32] Data[33] Data[34] Data[35] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W[20] W[20] Bit[20] Bit[10] W[21] W[21] Bit[21] W[10] W[22] W[22] Bit[22] Bit[11] W[23] W[23] Bit[23] W[11] W[24] W[24] Bit[24] Bit[12] W[25] W[25] Bit[25] W[12] W[26] W[26] Bit[26] Bit[13] W[28] W[28] Bit[28] Bit[14] W[29] W[29] Bit[29] W[14] W[30] W[30] Bit[30] Bit[15] W[31] W[31] Bit[31] W[15] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W[27] W[27] Bit[27] W[13] ByteM[31:24] ByteM[31:24] ByteM[31:24] Note: 2. The shaded data packet contains byte masking information that is applied to the eight data packets that follow. 18 Semiconductor MSM5718B70 RDRAM REGISTERS The 18M RDRAM contains ten registers. These are read and written with the Rreg, Wreg, and WregB commands. They are used to provide configuration information to the RDRAM controller (DeviceType, MinInterval, and DeviceManufacture), to control device, bank, and row addressing (DeviceId, AddressSelect, and Row), to control refresh (RefRow), to control RDRAM timing (Delay and RasInterval), and to control RDRAM operation (Mode). The following table summarizes these functions: Table 7 Register Summary Register Name DeviceType[3:0][8:0] Deviceld[3:0][8:0] Delay[3:0][8:0] Mode[3:0][8:0] RefRow[3:0][8:0] RasInterval[3:0][8:0] MinInterval[3:0][8:0] AddressSelect[3:0][8:0] DeviceManufacturer[3:0][8:0] Row[3:0][8:0] Reg. # 0 1 2 3 5 6 7 8 9 128 Description Read-only register that defined the size and configuration of the RDRAM. Used to specify the base address for the RDRAM. Used to specify CAS timing parameters. Used to initialize the RDRAM and set the IOL output current. Used to specify the next row and bank of the RDRAM to be refreshed. Used to specify RAS timing parameters. Read-only register defining minimum timing parameters for CAS accesses. Used to specify address bit swapping to maximize RDRAM cache hit rate. Read-only register containing a manufacturer code. Used to specify the currently sensed row in each bank. The following diagrams show the individual fields of the RDRAM registers. The color of a field denotes its usage: dark-gray is unimplemented, light-gray is read-only, and white is read-write. The arrow within each multi-bit field points from the least-significant bit to the most-significant bit. Bit and byte numbering use little-endien notation. Fig. 15 Registers DeviceType Register - 0 8 Byte[0] 7 6 5 4 3 2 Bns RowBits 1 0 Bns (Bonus) - 9 (1) bit bytes ColumnBits - 1011 (number of column addr bits)1 RowBits - 1001 (number of row addr bits)2 BankBits - 0001 (number of bank addr bits)3 - - Version Type Type - 0000 (RDRAM device) Version - 0001 (extended architecture) Read-only register that defines the size and configuration of an RDRAM. ColumnBits Byte[1] BankBits Byte[2] Byte[3] 1. This value specifies the number of bytes per row (1011=1110=211=2048 bytes). This is the address range over which accesses may be made without causing a row miss. 2. This value specifies the number of rows per bank (1001=910=29=512 rows). 3. This value specifies the number of banks per RDRAM (1=110=21=2 banks). 19 MSM5718B70 Semiconductor Read-write register for setting the base address of the RDRAM. 4 3 2 1 0 IdField [35:21] - Compared to Adr[35:21] of request packet to select RDRAM. - - - - - - Deviceld Register - 1 8 Byte[0] 7 6 5 IdField[35:21] Byte[1] Byte[2] Byte[3] Delay Register -2 8 Byte[0] 7 6 5 4 3 2 1 0 Read-write and read-only register to program the CAS access delays. AckWinDelay AckWinBits AckWinBits - 011 (Number of AckWinDelay bits) AckWinDelay - Normally set to 101 (5 busclocks) ReadDelay ReadBits ReadBits - 011 (Number of ReadDelay bits) ReadDelay - Normally set to 111 (7 busclocks) AckBits - 010 (Number of AckDelay bits) AckDelay - Normally set to 011 (3 busclocks) WriteBits - 011 (Number of WriteDelay bits) WriteDelay - Normally set to 001 (1 busclocks) Byte[1] Byte[2] AckDelay AckBits Byte[3] WriteDelay WriteBits AckWinDelay adjusts the size of the acknowledge window. ReadDelay, WriteDelay, and AckDelay adjust the time from the end of the packet to the start of read data, write data, and the acknowledge packets, respectively. Mode Register - 3 8 Byte[0] 7 6 5 4 3 2 1 0 Read-write register for initializing the RDRAM and for controlling operating modes. AS DE DE (DevEn) - Selects RDRAM at initialization AS - Set to one PL (PwrLng) - Selects powerdown wake-up time X2 (CCMult) - Set to one. CE (CCEnable) - Set to one. - - C[5:0] (CCValue) - Specifies IOL * 63 = minimum 0 = maximum CE X2 PL Byte[1] C5 C2 Byte[2] C4 C1 Byte[3] C3 C0 20 Semiconductor Read-write register for setting the next row refreshed by SetRR burst refresh. 4 3 2 1 0 RowField - Next row to be refreshed by SetRR - BankField - Next bank to be refreshed by SetRR - - - - - MSM5718B70 RefRow Register - 5 8 Byte[0] 7 6 5 RowField Bank Field Byte[1] Byte[2] Byte[3] RasInterval Register - 6 8 Byte[0] 7 6 5 4 3 2 1 0 Read-write register to program the RAS access intervals. Note that fields are in bit-reversed order. RowPrecharge - Set the precharge interval (Program to 01000) RowSense - Set the sense interval (Program to 01100) RowImpRestore - Set the implicit restore interval (Program to 10010) RowExpRestore - Set the explicit restore interval (Program to 00100) RowPrecharge Byte[1] RowSense RowImpRestore Byte[2] Byte[3] RowExpRestore MinInterval Register - 7 8 Byte[0] 7 6 5 4 3 2 1 0 Read-only register (configuration info) and write-only register (special control). MinWriteDelay - 0001 (minimum WriteDelay of RDRAM) MinWriteDly MinReadDly MinAckDly Byte[1] MinReadDelay - 0111 (minimum ReadDelay of RDRAM) MinAckDelay - 0011 (minimum AckDelay of RDRAM) SpecFunc SpecFunc - Performs SetRR burst refresh and SetPD powerdown entry Byte[2] Byte[3] MinWriteDelay, MinReadDelay, and MinAckDelay specify the minimum number of cycles allowed between a request packet and a write data, read data, and acknowledge packet, respectively. SpecFunc is a write-only field that is used to initiate a SetRR burst refresh or to place the RDRAM into powerdown mode. 21 MSM5718B70 Semiconductor Read-write register for swapping subfields of the Adr field of request packet. This maximizes the row hit rate for many applications. SwapField - Each bit swaps a pair of bits from Adr[28:20] and Adr[19:11] - - - - - - AddressSelect Register - 8 8 Byte[0] 7 6 5 4 3 2 1 0 SwapField Byte[1] Byte[2] Byte[3] DeviceManufacture Register - 9 8 Byte[0] 7 6 5 4 3 2 1 0 Read-only register with configuration information for RDRAM. ManufactureCode - See RDRAM Design Guide for more information. - - Manufacturer - Contains code specifying the manufacturing company. - - ManufactureCode Byte[1] ManufactureCode Byte[2] Manufacturer Byte[3] Manufacturer Row Register - 128 8 Byte[0] 7 6 5 4 3 2 1 0 Read-write register with address of currentlysensed row in each bank of RDRAM. SensedRow[0] - Address of currently sensed row of bank 0. - - SensedRow[0] Byte[1] Byte[2] SensedRow[1] SensedRow[1] - Address of currently sensed row of bank 1. - - Byte[3] 22 Semiconductor MSM5718B70 REFRESH The RDRAM is a dynamic device, and the memory array must be refreshed every 17 ms (tREF). The RDRAM includes all of the logic necessary to support three refresh modes to support this need. These refresh modes are: * Manual Refresh: The Rambus channel master uses a register write transaction (SetRR) to initiate a single burst refresh of four rows. * Touching: A single row is refreshed each time that a read or write request is made to that row in the RDRAM. * PowerDown Mode Refresh: A single row is refreshed with each pulse on the SIn/SOut pins. When the RDRAM is in PowerDown mode, it can be refreshed by passing a periodic pulse at a frequency of 60.2 kHz or greater through the SIn/SOut pins. This minimum frequency is equal to 1024/tREF. OPERATING MODES The RDRAM has three operating modes; Active, Standby and PowerDown. The three modes are distinguished by two factors, their power consumption, and the time that it will take the RDRAM to service a request from that mode. The control logic within the RDRAM includes a counter that counts Serial Mode packets. It takes a specific number of packets to cause the RDRAM to transition from a low-power mode to the Active state. This counter is active in all three operating modes. In Active mode, the RDRAM is active and ready to immediately service a request packet. Power consumption is also highest in Active mode. An RDRAM automatically transitions to Standby mode at the end of a transaction. While in this low power state, each RDRAM monitors the BusEnable signal for a serial mode packet while ignoring other activity on the remaining channel signals. The channel master sends a serial mode packet to bring all RDRAMs temporarily out of Standby and into Active mode so they can respond to a request packet. Once the request packet is acknowledged, all of the RDRAMs return to Standby mode with the exception of the one responding to the request. That device returns to Standby mode once the read or write operation is complete. Unlike conventional DRAM memory systems where each device in an entire bank of memory must be kept active and consumes power through an entire access, Rambus memory systems use only one active device while all others remain in a lower power state. Power consumption may be greatly reduced by using the PowerDown mode. This mode is entered manually by setting the Special Function bit SetPD in the MinInterval register. Entering this mode causes the device to write back and precharge both cache lines, disable the internal clock generator, and disable most DC current sources. The BusEnable receiver is kept active to detect serial mode packets used to exit powerdown mode. The only significant power consumption in powerdown mode is due to refresh. 23 MSM5718B70 Semiconductor Since the RDRAM's internal clocks are disabled while in powerdown mode, refresh must be maintained manually by the master device. This is done by supplying a low frequency square wave on the SIn TTL signal. This propagates through each RDRAM and is used to initiate asynchronous refresh operations in each device. Each RDRAM may be placed in either low or high threshold powerdown mode. Threshold refers to the number of serial mode packets required to wake up the RDRAM. A low threshold requires relatively few serial mode packets while a high threshold requires a larger number. The actual power dissipation is identical in both modes. An example of where these modes are used is in a portable computer application, as shown below. The sleep mode is implemented by placing a majority of the RDRAMs in high threshold powerdown while the RDRAM that contains the frame buffer is placed in low threshold powerdown. This permits screen refresh to take place without powering up the entire memory system. Reset Mode (place device in known state) Count < tMODEAR,MIN PowerOn PowerDown Mode (minimum power dissipation) Count tMODEPA {1/0}, MIN Standby Mode (reduced power dissipation) Count tMODESA, MIN Count tMODEDELAY, MAX Count tMODEAR,MIN Active Mode (ready to receive request) Write SetPD in MinInterval register Transaction complete BusCtrleven = 1 (Start Bit) Transaction Processing States Count = # SMode Packets Fig. 16 RDRAM Operating Modes 24 Semiconductor MSM5718B70 INITIALIZATION The channel master resets the RDRAM devices on the channel by asserting the BusEnable signal for TMODEAR, MIN clock cycles. After the RDRAM has been reset, the base address and register space registers revert to their default values. Because the default address of all devices is zero until initialization is complete, individual devices cannot be addressed from the channel, although the devices can and will respond to broadcast commands. In a typical system application, the SIn pin of the first RDRAM is tied to VDD (refer to Figure 2). The SIn pin of the next RDRAM is connected to the SOut pin of the first RDRAM, and so on. SOut of the last device is left unconnected. An RDRAM will not respond to a write command (other than a broadcast write) until its SIn pin is set to 1. Note that if PowerDown mode is to be used by the application, it must be possible to connect a 60.2 kHz pulse source to SIn of the first RDRAM to provide refresh. To start the initialization sequence, The RAC cell in the controller is reset, its DLL is allowed to lock, and its current control register is loaded. Next, the RDRAMs are put into Reset state by asserting the BusEnable wire for tMODEAR, MIN cycles. The tLOCK, RESET interval is observed to allow the RDRAM DLLs to lock. After the RDRAMs have been placed in Reset state, broadcast writes are made to all control registers needing values different from their Reset values. Next, SIn is asserted high on the first RDRAM in the chain. This enables it. The channel master then writes the desired device address to the DeviceID register and sets the DevEn bit. This asserts the SOut pin (and the SIn pin on the next device in the chain) to 1. Before proceeding to the next RDRAM, these additional steps are taken on the current RDRAM: 1. Current control calibration. The value written into the CCValue field of the Mode register is finetuned to maximize signal margin. This calibration process must take place before the controller performs any register or memory reads or any acknowledge responses. 2. Check read-only fields of control registers. This confirms which type of Base RDRAMs are present. This also provides an indication of when the end of the channel is reached. 3. Set the RasInterval register fields. 4. Touch the RDRAM with eight successive memory read transactions. This settles timing circuitry. This process continues until all of the RDRAMs have been initialized. When these steps have been completed for every device in the chain, all of the RDRAM devices will have unique, contiguous DeviceID values, and will have DevEn bits set. 25 MSM5718B70 Semiconductor ABSOLUTE MAXIMUM RATINGS The following table represents stress ratings only, and functional operation at the maximum ratings is not guaranteed. Extended exposure to the maximum ratings may affect device reliability. Although these devices contain protective circuitry to resist damage from static electric discharge, always take precautions to avoid high static voltages or electric fields. Symbol VI,ABS VI,TTL,ABS VDD,ABS TJ,ABS TSTORE Parameter Voltage applied to any RSL pin with respect to Gnd Voltage applied to any TTL pin with respect to Gnd Voltage on VDD with respect to Gnd Junction temperature under bias Storage temperature Min. -0.5 -0.5 -0.5 -55 -55 Max. VDD,MAX+0.5 VDD+0.5 VDD,MAX+1.0 125 125 Unit V V V C C THERMAL PARAMETERS Symbol TJ TC QJC Parameter and Conditions Junction operating temperature Package surface temperature Junction-to-Case thermal resistance Min. 0 -- -- Max. 100 90 5 Unit C C C/Watt CAPACITANCE Symbol CI CI,TTL Parameter and Conditions Low-swing input parasitic capacitance TTL input parasitic capacitance Min. -- -- Max. 2 8 Unit pF pF POWER CONSUMPTION Mode Powerdown Standby Active Read Write Device shut down Device inactive Device evaluating request packet Data being transferred from device (@Burst Length = 256) Data being transferred to device (@Burst Length = 256) Description Min. -- -- -- -- -- a (Ta = 0C to 70C) Max. Unit 20a/20b/30c 330 /340 /360 1.4 /1.5 /1.6 a b b c mW mW W W W 0.9a/0.95b/1.0c c 1.3a/1.4b/1.5c Notes: a. 500 MHz rank b. 533 MHz rank c. 600 MHz rank 26 Semiconductor MSM5718B70 RECOMMENDED ELECTRICAL CONDITIONS Symbol VDD, VDDA VREF VIL VIH VIL,TTL VIH,TTL Parameter and Conditions Supply voltage Reference voltage Input low voltage Input high voltage TTL input low voltage TTL input high voltage Min. 3.15 1.9 VREF-0.8 VREF+0.35 -0.5 1.8 (Ta = 0C to 70C) Max. Unit 3.45 VDD-0.8 VREF-0.35 VREF+0.8 0.8 VDD+0.5 V V V V V V ELECTRICAL CHARACTERISTICS Symbol IREF IOH IOL,0 IOL,20 IOL,40 II,TTL VOL,TTL VOH,TTL Parameter and Conditions VREF CURRENT @ VREF,MAX Output high current @ (0 VOUT VDD) Output low current @ VOUT=1.6 V @ C[5:0]=111111 (6310)a Output low current @ VOUT=1.6 V @ C[5:0]=110001 (4910)a Output low current @ VOUT=1.6 V @ C[5:0]=011111 (3110)a TTL input leakage current @ (0 VI,TTL VDD) TTL output voltage @ IOL,TTL=1.0 mA TTL output high voltage @ IOH,TTL= -0.25 mA Min. -10 -10 0.0 18.0 36.0 -10.0 0.0 2.0 (Ta = 0C to 70C) Max. Unit 10 10 4.0 22.0 44.0 10.0 0.4 VDD mA mA mA mA mA mA V V Note: a. This is the value written into the C[5:0] field of the Mode register. Values of IOL in between the IOL,0, IOL,20, and IOL,40 values are produced by interpolating C[5:0] to intermediate values. For example, C[5:0] = 101000 (4010) produces an IOL in the range of 27.0 to 33.0 mA. 27 MSM5718B70 Semiconductor RECOMMENDED TIMING CONDITIONS Symbol tCR, tCF tCYCLE tTICK tCH, tCL tTR tDR, tDF tQR, tQF tS tH tREF tLOCK,RESET tLOCK,POWERUP Parameter TxClk and RxClk input rise and fall times TxClk and RxClk cycle times Transport time per bit per pin (this timing interval is synthesized by the RDRAM's internal clock generator) TxClk and RxClk high and low times TxClk-RxClk differential Data/Control input rise and fall times Data/Control output rise and fall times Data/Control-to-RxClk setup time RxClk-to-Data/Control hold time Refresh interval RDRAM internal clock generator lock time from Reset mode RDRAM internal clock generator lock time from PowerUp mode Min. 0.3 3.33/3.75/4.0 (Ta = 0C to 70C) Max. Unit 0.8 4.5 ns ns 0.5 (2 ns @ 0.5 (2.25 ns @ tCYCLE tCYCLE = 4ns) tCYCLE = 4.5ns) 45% 55% tCYCLE 0 0.3 0.3 0.35 0.35 -- -- -- 0.7 0.6 0.5 -- -- 17 tCYCLE ns ns ns ns ms 750 (3 ms @ tCYCLE tCYCLE = 4ns) 750 (3 ms @ tCYCLE tCYCLE = 4ns) 28 Semiconductor MSM5718B70 TIMING CHARACTERISTICS Symbol tPIS tQ Parameter SIn-to-SOut propagation delay @ CLOAD,TTL = 40 pF TClk-to-Data/Control output time Min. 1 (Ta = 0C to 70C) Max. Unit 25 ns ns tCYCLE tCYCLE - 0.4 + 0.4 4 4 RAMBUS CHANNEL TIMING The next table shows important timings on the Rambus channel for common operations. All timings are from the point of view of the channel master, and thus have the bus overhead delay of 4 ns per bus transversal included where appropriate. Symbol tRESPONSE tREADHIT tWRITEHIT tRETRYSENSED CLEAN (no restore) tRETRYSENSED DIRTY (restore) tRETRYREFRESH CLEAN (no restore) Parameter Start of request packet to start of acknowledge packet Start of request packet to start of read data packet for row hit (Okay) Start of request packet to start of write data packet for row hit (Okay) Start of request packet for row miss (Nack) to start of request packet for row hit (Okay). The previous row had not been written Start of request packet for row miss (Nack) to start of request packet for row hit (Okay). The previous row had been written Start of request that performs a burst refresh (SetRR) until the start of a request that will not have a Nack acknowledge due to the pending refresh. The previously sensed row had not been written Start of request that performs a burst refresh (SetRR) until the start of a request that will not have a Nack acknowledge due to the pending refresh. The previously sensed row had been written Min. 6a 10a 4a 22b (Ta = 0C to 70C) Max. Unit 9a 17a 11a -- tCYCLE tCYCLE tCYCLE tCYCLE 30b -- tCYCLE 209 -- tCYCLE tRETRYREFRESH DIRTY (restore) 217 -- tCYCLE 29 MSM5718B70 Semiconductor Symbol tREADBURST32 tREADBURST256 tWRITEBURST32 tWRITEBURST256 tREADDELAY tWRITEDELAY tACKDELAY tACKWINDELAY tSERIALREADOFFSET Parameter Start of request packet to end of 32 byte read data packet for row hit (Okay) Start of request packet to end of 256 byte read data packet for row hit (Okay) Start of request packet to end of 32 byte write data packet for row hit (Okay) Start of request packet to end of 256 byte write data packet for row hit (Okay) End of request packet to beginning of read data packet End of request packet to beginning of write data packet End of request packet to beginning of acknowledge packet Window in which an acknowledge packet will be sent Delay from the beginning of a serial address packet or serial control packet to the beginning of the corresponding read data subpacket Delay from the beginning of a serial address packet or serial control packet to the beginning of the corresponding write data subpacket Min. 26c 138 20d 132 7a 1 3 a a Max. -- -- -- -- 14 8 6 12 13 Unit tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE 5a 13 tSERIALWRITEOFFSET 5 5 tCYCLE Delay from the end of the current memory space transtPOSTMEMWRITEDELAY action to the beginning of the next memory space transaction tPOSTREGWRITEDELAY tMODEOFFSET tMODESA tMODEPA[0] tMODEPA[1] tMODEAR tMODEDELAY tINTERREQUEST tRAS, MAX Delay from the end of the current register space transaction to the beginning of the next register space transaction Offset from the beginning of SMode packet to request packet for standby to active transaction Number of SMode packets to cause a transition from StandbyMode to ActiveMode Number of SMode packets to cause a transition from PowerDownMode[0] to ActiveMode Number of SMode packets to cause a transition from PowerDownMode[1] to ActiveMode Number of SMode packets necessary to cause a transition from ActiveState to ResetState Delay time after a transaction is complete for the RDRAM to enter the StandbyState Offset from the beginning of the request of the current transaction to the beginning of the request packet of the next transaction. Time that a row may remained sensed within a bank. 2 -- tCYCLE 4 4 1 20 176 254 -- 6 -- -- 4 4 -- -- -- 20 -- 125 tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE ms Notes: a. Programmable - All RDRAMS will operate across the full programming range. b. Minimum at tCYCLE,MIN. The delay is programmable to give equivalent timings at longer tCYCLE. c. Calculated with tREADHIT,MIN d. Calculated with tWRITEHIT,MIN 30 Semiconductor MSM5718B70 RISE/FALL TIMING VIH,MIN 80% 20% VIL,MAX tCF tCR VIH,MIN 80% 20% VIL,MAX tDF tDR VOH,MIN 80% 20% VOL,MAX tQF tQR Where: VOH,MIN = VTERM,MIN VOL,MAX = VTERM - ZO* (IOL,MAX* programmed value) VRxClk VTxClk VData,in VControl,in VData,out VControl,out CLOCK TIMING VTxClk tCL tCYCLE tTR tCYCLE tCL VRxClk tCH tCH Logic 0, VIH VREF Logic 1, VIL Logic 0, VIH VREF Logic 1, VIL 31 MSM5718B70 Semiconductor RECEIVE DATA TIMING VRxClk VData,in VControl,in * tTICK is defined as one-half tCYCLE. TRANSMIT DATA TIMING VTxClk VData,out VControl,out * tTICK is defined as one-half tCYCLE. ,,, ,,, tCYCLE tTICK (even) tTICK (odd) Logic 0, VIH VREF Logic 1, VIL tS tH tS tH Logic 0, VIH VREF Logic 1, VIL tCYCLE tTICK (even) tTICK (odd) Logic 0, VIH VREF Logic 1, VIL tQ,MAX tQ,MAX Logic 0, VIH VREF tQ,MIN Logic 1, VIL tQ,MIN 32 Semiconductor SERIAL CONFIGURATION PIN TIMING VSIn VSOut VSIn , tPIO,MAX tPIO,MIN tSL tSCYCLE tSH Request tINTERREQUEST, MIN Request MSM5718B70 Logic 1 VSW,TTL Logic 0 Logic 1 VSW,TTL Logic 0 Logic 1 VSW,TTL Logic 0 VSW,TTL=1.5 V STANDBY MODE TO ACTIVE MODE TIMING tCYCLE RxClk BusData tMODEOFFSET,MIN BusEn 11 Request tACKDELAY tMODESA,MIN BusCtrl Standby Mode Ack Active Mode 33 MSM5718B70 Semiconductor RESET TIMING tCYCLE RxClk BusData tMODEAR,MIN BusEn 11 tLOCK,RESET,MIN Request tACKDELAY Ack BusCtrl Reset Mode Request Active Mode READ HIT TIMING DIAGRAM tCYCLE RxClk tREADHIT tREADDELAY BusData Request Data Data(n-3) Data(n-2) Data(n-1) Data(n) tSERIALREADOFFSET BusEn SAdr(1) tACKDELAY tRESPONSE BusCtrl Ack(1:0) SCtrl(n+1) SAdr(2) SAdr(3) SAdr(n) 34 Semiconductor MSM5718B70 WRITE HIT TIMING DIAGRAM tCYCLE RxClk tWRITEHIT BusData Request Data(0) tWRITEDELAY BusEn SAdr(1) SAdr(2) tACKDELAY tRESPONSE BusCtrl Ack(1:0) SCtrl(n+1) SAdr(n) Data(n-1) Data(n) tSERIALWRITEOFFSET READ MISS TIMING DIAGRAM tCYCLE RxClk BusData Request Request tREADHIT Data(0) BusEn tRESPONSE BusCtrl Ack(1:0) = Nack tRETRYSENSEDCLEAN or tRETRYSENSEDDIRTY Ack(1:0) = Ack tRESPONSE 35 MSM5718B70 Semiconductor WRITE MISS TIMING DIAGRAM tCYCLE RxClk BusData Request Request tWRITEHIT Data(0) Data(1) BusEn tRESPONSE BusCtrl Ack(1:0) = Nack tRETRYSENSEDCLEAN or tRETRYSENSEDDIRTY Ack(1:0) = Ack tRESPONSE REGISTER READ TIMING DIAGRAM tCYCLE RxClk BusData Request tREADDELAY Data BusEn tACKDELAY Request Ack BusCtrl 36 Semiconductor MSM5718B70 REGISTER WRITE TIMING DIAGRAM tCYCLE RxClk tWRITEDELAY BusData Request Data Request BusEn tACKDELAY tPOSTREGWRITEDELAY BusCtrl Request Ack Request MANUAL REFRESH USING SETRR tCYCLE RxClk tWRITEDELAY BusData Request Data tRETRYREFRESH BusEn tACKDELAY Request BusCtrl Ack REFRESH TIMING FOR POWERDOWN MODE USING SIN, SOUT tREF/1024 SIn 37 MSM5718B70 Semiconductor POWER DOWN TIMING (REGISTER WRITE) tCYCLE RxClk BusData Request Data BusEn tACKDELAY BusCtrl Request Active Mode Ack PowerDown Mode POWER UP TIMING tCYCLE RxClk BusData tMODEPA[0/1],MIN tLOCK,POWERUP,MIN BusEn 11 Request tACKDELAY BusCtrl PowerDown Mode Request Active Mode Ack 38 Semiconductor MSM5718B70 MECHANICAL DRAWINGS The RDRAM is available in a horizontal surface mount plastic package. Dimensions for the horizontal surface mount plastic package are shown below. Pkg D Pkg E Pkg A Pin e Pin 1 Pin 32 Fig. 17 SHP-32 Package The next figure shows the footprint of the SHP-32 package. Plane R-R is the electrical reference plane of the device on the center line of the SMT pads. Sup D1 Pin e Pad 0 1 Pin e Pad b3 Pad l1 32 R-R All pins on 0.65 horizontal grid Fig. 18 SHP-32 Footprint 39 MSM5718B70 Semiconductor This table summarizes the values of the package and footprint dimensions. Table 8 SHP-32 Package Dimensions Symbol Pin e Pkg D Pkg A Pkg E Pad b3 Pad l1 Sup D1 Pad O Pin pitch Package width Package total height Package thickness SMT pad width SMT pad length Support pad outer pitch SMT pad offset Parameter Min. -- 24.9 12.8 -- 0.30 1.2 -- -- Typ. 0.65 25.0 13.0 -- -- -- 22.75 12.5 Max. -- 25.1 13.2 1.75 0.40 1.4 -- -- Unit mm mm mm mm mm mm mm mm 40 |
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