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Product Specification
PE3291
Product Description
The PE3291 is a dual fractional-N FlexiPowerTM phase-lock loop (PLL) IC designed for frequency synthesis. Each PLL includes a FlexiPowerTM prescaler, phase detector, charge pump and onboard fractional spur compensation. The FlexiPower prescalers are supplied power on dedicated pins and can operate at a substantial power savings at voltages as low as 0.8 volts, while allowing a 3 volt charge pump supply. For 3 volt only systems, on-chip voltage regulation may be used to generate the prescaler power supplies. Figure 1 illustrates the implementation of the FlexiPower technology. The prescaler power supply may be provided externally or internally regulated down from VDD. In a typical 950 MHz application the total current consumed by the PLL is 2.1 mA. Operation at reduced current levels provides significant battery life extension. The PE3291 allows the system designer to minimize power consumption by controlling the voltage on the prescaler. For additional operating speeds and current consumptions refer to Figures 5 and 6. PE3291 provides fractional-N division with power-of-two denominator values up to 32. This allows comparison frequencies up to 32 times the channel spacing, providing a lower phase noise floor than integer PLLs. The 32/33 RF prescaler (PLL1) operates up to 1200 MHz and the 16/17 IF prescaler (PLL2) operates up to 550 MHz. The PE3291 Phase Locked-Loop is manufactured on Peregrine's UltraCMOSTM process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. 1200 MHz / 550 MHz Dual Fractional-N FlexiPowerTM PLL for Frequency Synthesis Features
* Ultra-Low Power via FlexiPower
variable supply voltages
* Modulo-32 fractional-N main counters * On-board fractional spur compensation:
No tuning required, stable over temperature
* Improved phase noise compared to
integer-N architectures Applications
* CDMA handsets * CDMA base stations * Analog Cordless phones * One and two way pagers
Figure 1: FlexiPower technology enables the prescaler to operate at voltages down to 0.8 volts. This significantly reduces the total power.
To Loop Filter 3 Volts 0.8 3 Volts
Ref. Input
Phase Comparator and Charge pump
Regulator
Low Speed Counters
Prescaler PE3291
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PE3291
Product Specification
Figure 2. Pin Configurations (Top View)
N/C VDD CP1 GND fin1 Dec1 VDD1 fr GND 1 2 3 4 5 6 7 8 9 20 VDD 19 VDD 18 CP2 17 GND 16 fin2 15 Dec2 14 VDD2 13 LE 12 Data 11 Clock
Figure 3. Package Type
20-lead TSSOP
foLD 10
Table 1. Pin Descriptions
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Name
N/C VDD CP1 GND fin1 Dec1 VDD1 fr GND foLD Clock Data LE VDD2 Dec2 Fin2 GND CP2 VDD VDD
Type
No connect. (Note 1) Output
Description
Power supply voltage input. Input may range from 2.7 V to 3.3 V. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Internal charge-pump output from PLL1 for connection to a loop filter for driving the input of an external VCO. Ground.
Input
Prescaler input from the PLL1 (RF) VCO. Maximum frequency is 1.2 GHz. Power supply decoupling pin for PLL1. A capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. PLL1 prescaler power supply (FlexiPower 1).
Input
Reference frequency input. Ground.
Output Input Input Input Output Output Input
Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect signals, and data out of the shift register. CMOS output (see Table 11, foLD Programming Truth Table). CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the 21-bit shift register. Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits. Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is loaded into one of the four appropriate latches (as assigned by the control bits). PLL2 prescaler power supply (FlexiPower 2). Power supply decoupling pin for PLL2. A capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Prescaler input from the PLL2 (IF) VCO. Maximum frequency is 550 MHz. Ground.
Output (Note 1) (Note 1)
Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of an external VCO. Same as pin 2. Same as pin 2.
Note 1: VDD pins 2, 19, and 20 are connected by diodes and must be supplied with the same voltage level.
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Document No. 70-0009-04 UltraCMOSTM RFIC Solutions
PE3291
Product Specification
PE3291 Description The PE3291 is intended for such applications as the local oscillator for the RF and first IF of dualconversion transceivers. The RF PLL (PLL1) includes a 32/33 prescaler with a 1200 MHz maximum frequency of operation, where the IF PLL (PLL2) incorporates a 16/17 prescaler with a 550 MHz maximum frequency of operation. Using an advanced fractional-N phase-locked loop technique, the PE3291 can generate a stable, very low phase-noise signal. The dual fractional architecture allows fine resolution in both PLLs, with no degradation in phase noise performance. Data is transferred into the PE3291 via a threewire interface (Data, Clock, LE). Supply voltage can range from 2.7 to 3.3 volts for VDD and from 0.8 to 3.3 volts for the FlexiPower supply. PE3291 features very low power consumption and is available in a 20-lead TSSOP (JEDEC MO-153AC) package.
FlexiPower Operation Each FlexiPower PLL prescaler can be supplied its own dedicated supply voltage as low as 0.8 volts for substantial power savings. The maximum frequency of operation scales with the FlexiPower supply voltage. If voltages less than VDD are not available, the FlexiPower supplies can be internally generated, but the power savings will not be as great as when using external FlexiPower supplies. Spurious Response A critical parameter for synthesizer designs is spurious output. Spurs occur at the integer multiples of the step size away from center tone. An important feature of fractional synthesizers is their ability to reduce these spurious sidebands. The PE3291 has a built-in method for reducing these spurs, with no external components or tuning required. In addition, this circuitry works over the full commercial temperature range.
Figure 4. PE3291 Block Diagram
fin1
32/33 Prescaler
19-bit Fractional-N Main Divider
Fractional Spur Compensation
fr
Ref. Amp.
9-bit Reference Divider
Phase Detector
Charge Pump
CP1
Clock Data LE 21-bit Serial Control Interface Multiplexer foLD
9-bit Reference Divider
Phase Detector
Charge Pump
CP2
fin2
16/17 Prescaler
18-bit Fractional-N Main Divider
Fractional Spur Compensation
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PE3291
Product Specification
Table 2. Absolute Maximum Ratings
Symbol
VDD VI II IO Tstg
Table 3. Operating Ratings
Units
V V mA mA C
Parameter/Conditions
Supply voltage Voltage on any input DC into any input DC into any output Storage temperature range
Min
-0.3 -0.3 -10 -10 -65
Max
4.0 VDD + 0.3 +10 +10 150
Symbol
VDD TA
Parameter/Conditions
Supply voltage Operating ambient
Min
2.7 -40
Max
3.3 85
Units
V C
Table 4. ESD Ratings
Symbol
VESD Note 1:
Parameter/Conditions
ESD voltage human body model
Level
1000
Units
V
Absolute Maximum Ratings are those values listed in the above table. Exceeding these values may cause permanent device damage. Functional operation should be restricted to the limits in the DC and AC Characteristics table. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Periodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up.
Table 5. DC Characteristics: VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified
Symbol
IDD
Parameter
3 V supply current when VDD1 and VDD2 are internally regulated down from VDD (note 1)
Conditions
(10 MHz Ref. Freq.) P2, P1 = 01 RF RF PLL1 low speed P2, P1 = 1X C10, C20 = 01 P2, P1 = 01 C10, C20 = 00 P2, P1 = 10 C10, C20 = 00 P2, P1 = 11 C10, C20 = 00 P2, P1 = 00 RF PLL1 high speed IF PLL2 off RF PLL1 low speed IF PLL2 low speed RF PLL1 high speed IF PLL2 low speed RF PLL1 high speed IF PLL2 high speed 2 PLL's enabled 1 PLL enabled
Min
Typ
1.4 2.0 2.1 2.7 3.1 1.0 0.7
Max
Units
mA mA mA mA mA mA mA
IDD
3 V supply current when VDD1 and VDD2 are externally supplied (note 1) PLL1 FlexiPower Prescaler supply current (see fig. 5)
IDD1
P2, P1 = 00 VDD1 = 1/0 volt VDD1 = 1.8 volts VDD1 = 2.7 volts P2, P1 = 00 VDD2 = 1.0 volt VDD2 = 1.8 volts VDD2 = 2.7 volts
PLL1 enabled 0.5 1.5 4.0 PLL2 enabled 0.4 1.2 2.0 5 0.7 x VDD 0.3 x VDD -1 -1 +1 +1 mA mA mA mA V V mA mA mA mA mA
IDD2
PLL2 FlexiPower Prescaler supply current (see fig. 5)
Istby Total standby current Digital inputs: Clock, Data, LE VIH High level input voltage VIL Low level input voltage IIH IIL High level input current Low level input current
50
VDD = 2.7 to 3.3 volts VDD = 2.7 to 3.3 volts VIH = VDD = 3.3 volts VIL = 0, VDD = 3.3 volts
Note 1: The total current consumed by the device is IDD when internal regulation is employed and IDD + IDD1 + IDD2 when VDD1 and VDD2 are externally supplied. When VDD1 and VDD2 are internally generated, pins 7 and 14 should be left floating. (c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 15 Document No. 70-0009-04 UltraCMOSTM RFIC Solutions
PE3291
Product Specification
Table 5. DC Characteristics (continued): VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified
Symbol
Reference Divider input: fr IIHR IILR VOLD VOHD ICP - Source ICP - Sink ICPL ICP - Source vs. ICP vs. TA ICP vs. VCP Sink vs. Source mismatch Output current vs. temperature Output current magnitude variation vs. voltage VCP = VDD / 2, TA = 25 C VCP = VDD / 2 0.5 V < VCP < VDD - 0.5 volt, TA = 25 C 10 10 10 % % % Input current Input current Output voltage LOW Output voltage HIGH VIH = VDD = 3.6 volts VIL = 0, VDD = 3.6 volts Iout = 1 mA Iout = -1 mA VDD-0.4 -70 70 -5 5 -25 +25 mA mA V V mA mA nA
Parameter
Conditions
Min
Typ
Max
Units
Digital output: foLD
Charge Pump outputs: CP1, CP2 Drive current Leakage current VCP = VDD / 2 0.5 V < VCP < VDD-0.5 volt
Figure 5. Prescaler Current vs. FlexiPower Voltage (VDD1 and VDD2 externally supplied)
40 .0
3.0 0
PL L1
PL 2 L Typic al Cur r ent ( mA)
20 .0
1.0 0
00 .0 0.8 1.2 1 .6 2 2 .4
DD 1
2.8
D D2
3.2
FlexiPow r vo ge (V e lta
,V
)
Table 6. AC Characteristics: VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified
Symbol
fClk tClockH tClockL tDSU tDHLD tLEW tCLE tLEC tData Out
Parameter
Serial data clock frequency Serial clock HIGH time Serial clock LOW time Data set-up time to Clock rising edge Data hold time after Clock rising edge LE pulse width Clock falling edge to LE rising edge LE falling edge to Clock rising edge Data Out delay after Clock falling edge (foLD pin) CL = 50 pf
Conditions
Min
Max
10
Units
MHz ns ns ns ns ns ns ns
Control Interface and Latches (see figure 8) 50 50 50 10 50 50 50 90
ns
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PE3291
Product Specification
Table 6. AC Characteristics (continued): VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified
Symbol Parameter Conditions
P2, P1 = 00 VDD1 = 1.0 volts VDD1 = 1.8 volts VDD1 = 2.7 volts P2, P1 = 01 VDD1 = internally generated (low speed) P2, P1 = 1X = (10 or 11) VDD1 = internally generated (high speed) fin2 Operating frequency (see figure 6) P2, P1 = 00 VDD1 = 1.0 volts VDD1 = 1.8 volts VDD1 = 2.7 volts P2, P1 = 01 or 10 VDD2 = internally generated (low speed) P2, P1 = 11 VDD1 = internally generated (high speed) Pfin1 Pfin2 fc fr Vfr Note 1: Input level range Input level range Comparison frequency Operating frequency Input sensitivity CMOS logic levels may be used if DC coupled External AC coupling (note 1) 0.5 External AC coupling External AC coupling
Min
Max
Units
Main Divider (Including Prescaler) fin1 Operating frequency (see figure 6)
300 300 300
450 900 1200
MHz MHz MHz
300
800
MHz
300
1100
MHz
45 45 45
300 550 550
MHz MHz MHz
45
300
MHz
45 -10 -10
550 5 5 10 50
MHz dBm dBm MHz MHz VP-P
Reference Divider
Figure 6. PLL Maximum Frequency vs. FlexiPower Voltage
1400 1200 1000 800 600 P LL2 PLL1
Typic al Freque ncy (MHz)
400 200
2.4 2.8 3.2 0.8 1.2 1.6 2 FlexiPower voltage (VDD1 ,VDD2 )
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PE3291
Product Specification
Functional Description The Functional Block Diagram in Figure 7 shows a 21-bit serial control register, a multiplexed output, and PLL sections PLL1 and PLL2. Each PLL contains a fractional-N main counter chain, a reference counter, a phase detector, and an internal charge pump with on-chip fractional spur compensation. Each fractional-N main counter chain includes an internal dual modulus prescaler, supporting counters, and a fractional accumulator. Serial input data is clocked on the rising edge of Clock, MSB first. The last two bits are the address bits that determine the register address. Data is transferred into the counters as shown in Table 8, PE3291 Register Set. If the foLD pin is configured as data out, then the contents of shift register bit S20 are clocked on the falling edge of Clock onto the foLD pin. This feature allows the PE3291 and compatible devices to be connected in a daisychain configuration. The PLL1 (RF) VCO frequency fin1 is related to Figure 7. Functional Block Diagram
A1 5
the reference frequency fr by the following equation: fin1 = [(32 x M1) + A1 + (F1/32)] x (fr/R1) (1) Note that A1 must be less than M1. Also, fin1 must be greater than or equal to 1024 x (fr/R1) to obtain contiguous channels. The PLL2 (IF) VCO frequency fin2 is related to the reference frequency fr by the following equation: fin2 = [(16 x M2) + A2 + (F2/32)] x (fr/R2) (2) Note that A2 must be less than M2. Also, fin2 must be greater than or equal to 256 x (fr/R2) to obtain contiguous channels. F1 sets PLL1 fractionality. If F1 is an even number, the PE3291 automatically reduces the fraction. For example, if F1 = 12, then the fraction 12/32 is automatically reduced to 3/8. In this way, fractional denominators of 2, 4, 8, 16 and 32 are available. F2 sets the fractionality for PLL2 in the same manner.
A1 Counter 0P1 P2 M1 9
Prescaler Control Logic
F1 5
fin1
32/33 Prescaler
M1 Counter 3F1 Counter 0Fractional Spur Compensation
fr
Ref. Amp.
9-bit Reference Divider
R1 9
Phase Detector
C11
Charge Pump
C12 C22 C22 C22 C22
CP1
Clock Data LE 21-bit Serial Control Interface
R2 9
Multiplexer
C21 C22
foLD
9-bit Reference Divider
Phase Detector
Charge Pump
CP2
fin2
16/17 Prescaler
M2 Counter 3M2 9
F2 Counter 0F2 5
Fractional Spur Compensation
P1
P2
A2 Counter 0A2 4
Prescaler Control Logic
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PE3291
Product Specification
Table 7. Register Set
S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Reserved
Test 0 C24
PLL2 Synthesizer control C23 C22 C21 C20 R28 R 27
PLL2 Reference counter R2 divide ratio R 26 R 25 R 24 R 23 R 22 R 21 R 20
Address 0 0
PLL2 Main counter M2 divide ratio
Res.
M28 M27 M26 M25 M24 M23 M22 M21 M20
PLL2 Swallow counter A2 divide ratio A23 A22 A21 A20
PLL2 Fractional counter F2 numerator value F24 F23 F22 F21 F20
Address 0 1
Res.
FlexiPower voltage regulation P2
PLL1 Synthesizer control C14 C13 C12 C11 C10 R18 R17
PLL1 Reference counter R1 divide ratio R16 R15 R14 R13 R12 R11 R10
Address 1 0
Res.
P1
PLL1 Main counter M1 divide ratio M18 M17 M16 M15 M14 M13 M12 M11 M10 A14
PLL1 Swallow counter A1 divide ratio A13 A12 A11 A10
PLL1 Fractional counter F1 numerator value F14 F13 F12 F11 F10
Address 1 1
MSB (first in)
(last in) LSB
Figure 8. Serial Interface Mode Timing Diagram
Data tDSU tDHLD tClockL tClockH
Clock tCLE tLEW tLEC
LE tData Out Data Out (foLD pin)
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Document No. 70-0009-04 UltraCMOSTM RFIC Solutions
PE3291
Product Specification
Programmable Divide Values
(R1, R2, F1, F2, A1, A2, M1, M2)
Table 8. PE3291 Counter Programming Example
Divide Value MSB
S11 A14 0 1 2 31 0 0 0 1 S10 A13 0 0 0 1 S9 A12 0 0 0 1 S8 A11 0 0 1 1
LSB
S7 A10 0 1 0 1
Address
S1 1 1 1 1 1 1 S0 1 1 1 1 1 1
Data is clocked into the 21-bit shift register, MSB first. When LE is asserted HIGH, data is latched into the registers addressed by the last two bits shifted into the 21-bit register, according to Table 7. For example, to program the PLL1 (RF) swallow counter, A1, the last two bits shifted into the register (S0, S1) would be (1,1). The 5-bit A1 counter would then be programmed according to Table 8. For normal operation, S16 of address (0,0) (the Test bit) must be programmed to 0 even if PLL2 (IF) is not used. Program Modes
Several modes of operation can be programmed with bits C10 - C14 and C20 - C24, including the phase detector polarity, charge pump high impedance, output of the foLD pin and power-down modes. The PE3291 modes of operation are shown on Table 9. The truth table for the foLD output is shown in Table 10. Table 9. PE3291 Program Modes
S15
C24 See Table 10 C23 See Table 10
S14
C22
S13
C21 (Note 2)
S12
S11
C20 (Note 1) 0 = PLL2 on 1 = PLL2 off C10 (Note 1) 0 = PLL1 on 1 = PLL1 off
S1
0
S0
0
0 = PLL2 CP normal 1 = PLL2 CP High Z
0 = PLL2 Phase Detector inverted 1 = PLL2 Phase Detector normal C11 (Note 2) 0 = PLL1 Phase Detector inverted 1 = PLL1 Phase Detector normal
C14 See Table 10
C13 See Table 10
C12 0 = PLL1 CP normal 1 = PLL1 CP High Z
1
0
Note 1:
The PLL1 power-down mode disables all of PLL1's components except the R1 counter and the reference frequency input buffer, with CP1 (pin 3) and fin1 (pin 5) becoming high impedance. The power down of PLL2 has similar results with CP2 (pin 18) and fin2 (pin 16) becoming high impedance. Power down of both PLL1 and PLL2 further disables counters R1 and R2, the reference frequency input, and the foLD output, causing fr (pin 8) and foLD (pin 10) to become high impedance. The Serial Control Interface remains active at all times. The C11 and C21 bits should be set according to the voltage versus frequency slope of the VCO as shown in Figure 9. This relationship presumes the use of a passive loop filter. If an inverting active loop filter is used the relationship is also inverted.
Note 2:
Figure 9. VCO Characteristics
VCO Output Frequency
(1) Positive slope VCO
* * * *
When VCO1 (RF) slope is positive like (1), C11 should be set HIGH. When VCO1 (RF) slope is negative like (2), C11 should be set LOW. When VCO2 (IF) slope is positive like (1), C21 should be set HIGH. When VCO2 (IF) slope is negative like (2), C21 should be set LOW.
(2) Negative slope VCO VCO Input voltage
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PE3291
Product Specification
Table 10. foLD Programming Truth Table
X = don't care condition foLD Output State
Disabled1 PLL 1 Lock detect (LD1) PLL2 Lock detect (LD2) PLL1 / PLL2 Lock detect
2 2 2
C14 (PLL1F0)
0 0 0 0 1 0 1 0 1 1 1 1
C13 (PLL1LD)
0 1 0 1 X X X X 0 0 1 1
C24 (PLL2F0)
0 0 0 0 0 1 0 1 1 1 1 1
C23 (PLL2LD)
0 0 1 1 0 0 1 1 0 1 0 1
PLL1 Reference divider output (fc1) PLL2 Reference divider output (fc2) PLL1 Programmable divider output (fp1) PLL2 Programmable divider output (fp2) Serial data out Reserved Reserved Counter reset3
Note: 1. When the foLD is disabled the output is a CMOS LOW. 2. Lock detect indicates when the VCO frequency is in "lock". When PLL1 is in lock and PLL1 lock detect is selected, the foLD pin will be HIGH with narrow pulses LOW. When PLL2 is in lock and PLL2 lock detect is selected, the foLD pin will be HIGH with narrow pulses LOW. When PLL1 / PLL2 lock detect is selected the foLD pin will be HIGH with narrow pulses LOW only when both PLL1 and PLL2 are in lock. 3. The counter reset state when activated resets all counters. Upon removal of the reset, counters M, A, and F resume counting in close alignment with the R counter (the maximum error is one prescaler cycle). The reset bits can be activated to allow smooth acquisition upon powering up.
Programming the FlexiPower voltage The PE3291 can be programmed to internally regulate down from the VDD voltage to supply the FlexiPower voltage, as shown in Table 11. This is implemented by programming P2, P1 (S18 & S16 - address 1,0). When programmed with 0,0 external voltage supplies must be provided to the part at pins VDD1 and VDD2. When using internal regulation, the FlexiPower supply pins should be left grounded. Table 11. FlexiPower Voltage Regulation Programming
P2
0 0 1 1
P1 FlexiPower 1 voltage (RF PLL1)
0 1 0 1
FlexiPower 2 voltage (IF PLL2)
No regulation (FlexiPower externally provided) Low power High speed High speed Low power Low power High speed
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Document No. 70-0009-04 UltraCMOSTM RFIC Solutions
PE3291
Product Specification
Phase Comparator Characteristics PLL1 has the timing relationships shown below for fc1, fp1, LD1, UP1, and DOWN1. When C11 = HIGH, UP1 directs the internal PLL1 charge pump to source current and DOWN1 directs the PLL1 internal charge pump to sink current. If C11 = LOW, UP1 and DOWN1 are interchanged. PLL2 has the timing relationships shown below for fc2, fp2, LD2, UP2, and DOWN2. When C21 = HIGH, UP2 directs the internal PLL2 charge pump to source current and DOWN2 directs the PLL2 internal charge pump to sink current. If C21 = LOW, UP2 and DOWN2 are interchanged.
Figure 10. Phase Comparator Timing Diagram
fc1 (2) (Note 1) fp1 (2) (Note 1) LD1 (2) (Note 1)
UP1 (2)
DOWN1 (2) fc leads fp fc = fp fc lags fp fc lags fp fc lags fp
Note 1: fc1(2), fp1(2), and LD1(2) are accessible via the foLD pin per programming in Table 11.
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PE3291
Product Specification
Loop Filter Second/Third Order Loops Choosing the optimum loop filter for a design encompasses many trade offs. The rule of thumb for choosing the loop filter bandwidth is 10 percent of the step size. A second order loop (C1 C2 R2 and C4 C5 R5 in Figure 11 omitting C3 R3 C6 and R6) will provide the least amount of components and the fastest lock times. If lock time is an issue, one might try opening up the loop filter, although if it is too wide, instability will dominate and worsen lock time. If lock time is not an issue, a narrower second order filter will minimize residual FM without requiring additional components. Third Order loop filters (C1 C2 R2 C3 R3 and C4 C5 R5 C6 R6 in Figure 11) provide a good compromise between lock time and residual FM. We have found using a third order loop with 20 dB of rejection at the step size will halve the Residual FM as measured with a similar second order loop, with minimum effect on lock time. Loop Filter Bandwidth Design Considerations As part of the spur compensation circuitry, the PE329x series PLLs contain capacitors to ground internal to the charge pump. PLL1 contains a 50 pF capacitor and PLL2 contains a 100 pF capacitor. To ensure accurate loop filter calculations, it is critical that the calculated value of the first shunt capacitor (C1 & C4 in Figure 11) be at least 100 pF for PLL1 and 200 pF for PLL2. With this requirement satisfied, the remaining loop components can be calculated. For a stable loop, it is also important that the loop bandwidth be less than or equal to one tenth of the step size.
Digital Control Lines Control Line Noise We have noticed frequency jitter during programming when a low impedance, such as a capacitor to ground, is placed next to any control line pin (clock, data, and load enable). The use of a 51 k ohm resistor in series with the control line will eliminate the problem with no effect to programming time. Enable Line Voltage The PE329x series PLLs use a level sensitive load enable. Therefore the digital controller must provide an active low to the part at all times except when the data is to be loaded into the shift register. If the PLL controller does not hold the voltage low, a high impedance resistor to ground should be added to the enable line to ensure stable operation. 5 Volt Operation: The PE329x series PLLs are not capable of accepting control voltages greater than 3.3 volts. Interface to 5 volt controllers requires the addition of resistor dividers to comply with the 3.3 volt maximum operation voltage.
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Document No. 70-0009-04 UltraCMOSTM RFIC Solutions
PE3291
Product Specification
Figure 11. Application Example
Note 1:
For optimum fractional spur and lock-time performance C2 and C5 should be polyester (or poly propylene). In addition, the loop filter components must be free from contamination. Contamination will result in poor spur performance. For accurate loop bandwidth, C1 must be greater than or equal to 100 pF, and C4 must be greater than or equal to 200 pF.
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PE3291
Product Specification
Figure 12. Package Drawing
20-lead TSSOP (JEDEC MO-153-AC)
12o REF 0.20 R 0.90 MIN TOP VIEW 0.65BSC 20 19 18 17 16 15 14 13 12 11 GAGE PLANE 0.25 12o REF R 0.90 MIN 0o 8o +.15 0.60 -.10 1.0 REF 3.20 2X
4.400.10 O1.000.10
1.00 -B-
1.00
1
2
3
4
5
6
7
8
9
10
.20 C B A 6.40
0.325
SIDE VIEW -A6.500.10 0.900.05
1.10 MAX -C0.10 C 0.10 0.30 MAX CBA 0.100.05
S Y M B O L
COMMON DIMENSION(MILLIMETERS)
0.65mm LEAD PITCH MIN --0.05 0.85 0.50 0.09 0.09 0.19 0.19 0.09 0.09 0 NOM ----0.90 0.60 ------0.22 ------1.0 REF 0.10 0.10 0.05 0.20 0.65 BSC 12 REF 12 REF MAX 1.10 0.15 0.95 0.75 ----0.30 0.25 0.20 0.16 8
A A1 A2 L R
FRONT VIEW
S Y M B O L
R1 b
AC MIN 6.40 4.30 NOM 6.50 4.40 6.4 BSC 0.65 BSC 20 1,2 A MAX 6.60 4.50
N O T E
b1 c c1 01 L1 aaa bbb ccc
D E1 E e N
3,8 4,8
6
NOTE ISSUE
ddd e 02 03
Table 12. Ordering Information
Order Code
3291-11 3291-12 3291-00
Part Marking
PE3291 PE3291 PE3291EK
Description
PE3291-20TSSOP-74A PE3291-20TSSOP-2000C PE3291-20TSSOP-Eval Kit
Package
20-lead TSSOP 20-lead TSSOP Evaluation Kit
Shipping Method
74 units / Tube 2000 unit / T&R 1 / Box
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 14 of 15
Document No. 70-0009-04 UltraCMOSTM RFIC Solutions
PE3291
Product Specification
Sales Offices
The Americas Peregrine Semiconductor Corporation
9450 Carroll Park Drive San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499
North Asia Pacific Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213
Europe Peregrine Semiconductor Europe
Batiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: +33-1-47-41-91-73 Fax : +33-1-47-41-91-73
Peregrine Semiconductor, Korea
#B-2402, Kolon Tripolis, #210 Geumgok-dong, Bundang-gu, Seongnam-si, Gyeonggi-do, 463-480 S. Korea Tel: +82-31-728-4300 Fax: +82-31-728-4305
South Asia Pacific Peregrine Semiconductor, China
Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652
Space and Defense Products
Americas: Tel: 505-881-0438 Fax: 505-881-0443 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence cedex 3, France Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp.
Preliminary Specification
The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice).
Document No. 70-0009-04 www.psemi.com
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 15 of 15

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