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| AP2309N Advanced Power Electronics Corp. Simple Drive Requirement Small Package Outline Surface Mount Device S D P-CHANNEL ENHANCEMENT MODE POWER MOSFET BVDSS RDS(ON) ID -30V 75m - 3.7A Description SOT-23 G D The Advanced Power MOSFETs from APEC provide the designer with the best combination of fast switching, , low on-resistance and cost-effectiveness. The SOT-23 package is universally preferred for all commercialindustrial surface mount applications and suited for low voltage applications such as DC/DC converters. G S Absolute Maximum Ratings Symbol VDS VGS ID@TA=25 ID@TA=70 IDM PD@TA=25 TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current 1,2 3 3 Rating - 30 20 - 3.7 -3 -12 1.38 0.01 -55 to 150 -55 to 150 Units V V A A A W W/ Continuous Drain Current Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 90 Unit /W Data and specifications subject to change without notice 200513041 AP2309N Electrical Characteristics@Tj=25oC(unless otherwise specified) Symbol BVDSS BVDSS/Tj Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=-250uA Min. -30 -1 - Typ. -0.02 5 5 1 3 8 5 20 7 412 91 62 Max. Units 75 120 -3 -1 -25 100 8 660 V V/ m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25, ID=-1mA RDS(ON) Static Drain-Source On-Resistance VGS=-10V, ID=-3A VGS=-4.5V, ID=-2.6A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=55 C) o o VDS=VGS, ID=-250uA VDS=-10V, ID=-3A VDS=-30V, VGS=0V VDS=-24V, VGS=0V VGS=20V ID=-3A VDS=-24V VGS=-4.5V VDS=-15V ID=-1A RG=3.3,VGS=-10V RD=15 VGS=0V VDS=-25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 Source-Drain Diode Symbol VSD trr Qrr Parameter Forward On Voltage 2 2 Test Conditions IS=-1.2A, VGS=0V IS=-3A, VGS=0V, dI/dt=100A/s Min. - Typ. 20 15 Max. Units -1.2 V ns nC Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board ; 270/W when mounted on min. copper pad. AP2309N 45 45 40 T A =25 o C -10V -7.0V -ID , Drain Current (A) 40 T A = 150 o C -10V -7.0V 35 35 -ID , Drain Current (A) 30 30 25 25 20 -5.0V -4.5V 20 -5.0V -4.5V 15 15 10 V G = - 3 .0V 10 V G = - 3 .0V 5 5 0 0 0 2 4 6 8 10 0 2 4 6 8 10 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 105 1.6 I D =-2.6A 95 T A =25 C Normalized RDS(ON) o 1.4 I D =3A V G =10V RDS(ON) (m ) 85 1.2 75 1.0 65 0.8 55 0.6 3 5 7 9 11 -50 0 50 100 150 -V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 1.3 3 2 Normalized -VGS(th) (V) 1.2 1.1 -IS(A) T j =150 o C 1 T j =25 o C 0.9 0 0 0.2 0.4 0.6 0.8 1 0.7 -50 0 50 100 150 -V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode Fig 6. Gate Threshold Voltage v.s. Junction Temperature AP2309N f=1.0MHz 12 1000 -VGS , Gate to Source Voltage (V) 10 ID= -3A V DS = -24V C iss 8 6 C (pF) 100 C oss C rss 4 2 0 0 2 4 6 8 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) -V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Duty factor=0.5 Normalized Thermal Response (Rthja) 0.2 10 0.1 0.1 -ID (A) 0.05 1 1ms PDM t 0.01 T Single Pulse 10ms 0.1 0.01 Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja = 270/W T A =25 C Single Pulse 0.01 0.1 1 10 o 100ms 1s DC 100 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 -V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG -4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Circuit Fig 12. Gate Charge Circuit |
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