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January 1998 Features NS ESIG WD NE at OR nt e r E D F 02 ND t Ce m/tsc E or I2 3 OMM See H al Supp rsil.co REC ic te c h n w w .in N OT A/D w r Te t o u S I L or c onta INTER c 81-88 (R) HI2301 8-Bit, 30 MSPS, Video Converter with Amplifier/Clamp Description The HI2301 is an 8-bit CMOS analog-to-digital converter for video use that features a sync clamp function and on-chip amplifier. The adoption of a 2-step parallel method realizes low power consumption and a maximum conversion speed of 30 MSPS. * Resolution . . . . . . . . . . . . . . . . . . .8-Bit 0.5 LSB (DNL) * Maximum Sampling Frequency . . . . . . . . . . . 30 MSPS * Low Power Consumption, 120mW (Including Reference Current) * Standby Function * Amplifier Functions - Built-In 3x Amplifier (15MHz Band) - 2-Input Selector Function Provided * Built-In Input Clamp Function (DC Restore) * Clamp ON/OFF Function * Internal Voltage Reference * Three-State TTL Compatible Output * Power Supply . . . . . . . . . +5V Single or +4.75/3.3V Dual * Direct Replacement for Sony CXD2301 Ordering Information PART NUMBER HI2301JCQ TEMP. RANGE ( oC) -20 to 75 PACKAGE 32 Ld MQFP PKG. NO. Q32.7x7-S Applications * Desktop Video * Multimedia * Video Digitizing * Image Scanners Pinout HI2301 (MQFP) TOP VIEW VIN2 AVDD AVSS ADIN AVSS CCP OPO VIN1 VRB AVSS AVSS SEL CE CLE AVSS DVSS 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 VREF VRT ADV ADV CLP TEST CLK DVDD D7 D6 D5 D4 D3 D2 D1 D0 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 4-1 File Number 4104.2 HI2301 Functional Block Diagram VIN2 VIN1 27 25 3R OPO 30 ADV 21 ADV 22 AVDD 26 R TEST (DVSS) 19 SEL CE 4 5 R + VBI REFERENCE SUPPLY - RTS 23 VRT 1 VRB D0 (LSB) 16 D1 15 D2 14 D3 13 D4 12 D5 11 D6 10 D7 (MSB) 9 CLOCK GENERATOR UPPER DATA LATCH LOWER DATA LATCH LOWER ENCODER (4-BIT) LOWER SAMPLING COMPARATOR (4-BIT) LOWER ENCODER (4-BIT) LOWER SAMPLING COMPARATOR (4-BIT) 29 ADIN 2 AVSS 3 AVSS UPPER ENCODER (4-BIT) UPPER SAMPLING COMPARATOR (4-BIT) ADV 7 AVSS 28 AVSS 31 AVSS CLK 18 DVDD 17 DVSS 8 A/D CONVERTER BLOCK + - 24 VREF 6 20 32 CLE CLP CCP Pin Descriptions PIN NO. 1 SYMBOL VRB EQUIVALENT CIRCUIT AVDD DESCRIPTION Reference voltage (bottom) connect to AVSS for normal use. When another external voltage is input, connect an external 0.1F capacitor and retain a 1.5V differential compared to the top reference voltage. Reference voltage (top) by setting VRB to AVSS , outputs approximately 1.5V. Connect only a 0.1F external by-pass capacitor for normal use. When another external voltage is input, it must be 2.2V or lower. 23 V RT 23 RTS RREF 1 AVSS 2, 3, 7, 28, 31 AVSS Analog GND. 4-2 HI2301 Pin Descriptions PIN NO. 4 (Continued) EQUIVALENT CIRCUIT AVDD 4 5 19 AVSS DVSS SYMBOL SEL DESCRIPTION Switches the input of the 3x amplifier. When SEL is at Low level, VIN1 is selected. When SEL is at High level, VIN2 is selected. Standby function ON/OFF selector. In standby state when High. Fix to VSS for normal use. 5 19 CE TEST 6 CLE 6 18 AVDD When CLE = Low: Clamp function is enabled. When CLE = High: Clamp function is disabled, and only the normal A/D converter function is enabled. Clock Input. 18 20 8 9 to 16 CLK CLP DV SS D7 to D 0 20 AVSS CE Inputs the clamp pulse to Pin 20 (CLP). Clamps the High interval signal voltage. Digital GND. D7 (MSB) to D 0 (LSB) output. Outputs Low level in standby. In operation, the phase of D7 to D0 output is inverted against the phase of ADIN. DI 17 21 DVDD ADV AVDD 5V or 3.3V Short Pins 21 and 22, and connect 0.1F external capacitor. CE 21 AVSS 22 ADV AVDD 22 AVSS 24 V REF AVDD Clamp reference voltage input. Clamps so that the reference voltage and the clamp interval ADIN input signal are equal. The reference voltage is more than 0.5V. 24 AVSS 4-3 HI2301 Pin Descriptions PIN NO. 25 27 (Continued) EQUIVALENT CIRCUIT AVDD R11 200 25 27 AVSS R12 R SYMBOL VIN1 VIN2 DESCRIPTION Amplifier input pin. Biased internal at 1.9V (when AVDD = 5V) or at 1.8V (when AVDD = 4.75V). When standby as well. When SEL is at Low level, VIN1 is selected for input; when SEL is at High level, VIN2 is selected for input. 26 29 AVDD ADIN AVDD 5V or 4.75V A/D converter block analog input. 29 AVSS 30 OPO AVDD Amplifier Output. The phase of this output is inverted against the phase of VIN1 , 2 . In standby mode, it becomes high-impedance output condition. 30 AVSS 32 CCP AVDD Integrates the clamp control voltage. The relationship between the CCP voltage variation and the ADIN voltage is positive phase. 32 AVSS The following table shows the status of the digital output pins when the TEST pin is used with the CE and SEL pins. TEST L L H H H CE L H L H H SEL X X X L H H L L H H L D1 D1 L D2 D2 L D3 D3 L D4 D4 L D5 D5 L D6 D6 L D7 D7 L D8 D8 L ADIN INPUT SIGNAL VOLTAGE VRT * * STEP 0 * * * 127 128 * * * 255 1 0 1 DIGITAL OUTPUT CODE MSB 0 0 0 0 * * * 1 0 1 0 1 0 * * * 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0 LSB 0 0 TEST MODE L H H L L H H L L H * * * * * * V RB Digital Output The following table shows the correlation between the ADIN input voltage and the digital output code. Take notice that the phase of ADIN input signal voltage is inverted against the phase of the digital output. 4-4 HI2301 Absolute Maximum Ratings TA = 25oC Supply Voltage (V DD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Reference Voltage (VRT , VRB) . . . . . . . . . . . VDD 0.5 to VSS -0.5V Input Voltage, Analog (VIN) . . . . . . . . . . . . . . VDD 0.5 to VSS -0.5V Input Voltage, Digital (VIH , VIL) . . . . . . . . . . . VDD 0.5 to VSS -0.5V Output Voltage, Digital (V OH , VOL) . . . . . . . . VDD 0.5 to VSS -0.5V Thermal Information Thermal Resistance (Typical, Note 1) JA (oC/W) Operating Conditions Supply Voltage (IDVSS - AVSSI) . . . . . . . . . . . . . . . . . . 0 to 100mV Single Power Supply (AVDD , DVDD) . . . . . . . . . . . . . . . . 5.0 0.25V Dual Power Supply (AVDD) . . . . . . . . . . . . . . . . . . . . . . 4.75 0.25V (DVDD) . . . . . . . . . . . . . . . . . . . . . . . . 3.3 0.3V Reference Input Voltage (V RB) . . . . . . . . . . . . . . . . . . . . 0V to 2.2V (VRT) . . . . . . . . . . . . . . . . . . . . 0V to 2.2V Analog Input (ADIN) . . . . . . . . . . . . . . . . . . . . . . More than 1.2VP-P Clock Pulse width, tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . 16ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . 16ns (Min) Temperature Range (TOPR). . . . . . . . . . . . . . . . . . . . . . -20 to 75oC MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (Lead Tips Only) CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER Supply Current Standby Supply Current Max Conversion Rate Min Conversion Rate ADIN Input Band (At -1dB) ADIN Input Capacitance Electrical Specifications; When using a single power supply (fC = 30 MSPS, AV DD = DVDD = +5V, VRB = 0V, VRT = 1.5V, TA = 25oC SYMBOL TEST CONDITIONS MIN 30 VIN = 0.75V + 0.07VRMS 230 VRB = AVSS 1.38 -40 +25 3.5 DV DD = Max VIH = VDD VIL = 0V DV DD = Min VOH = VDD - 0.5V VOL = 0.4V With TTL 1 Gate and 10pF Load fC = 30 MSPS, VIN = 0V To 1.5V NTSC 40 IRE Mod Ramp, fC = 14.3 MSPS -1.1 3.7 7 VADIN = DC PWS = 3 VREF = 0.5V VREF = 1.5V 0 -40 TYP 27 130 20 8 330 1.52 -20 +45 -2.5 6.5 13 +0.5 1 0.5 30 2 +20 -20 MAX 35 200 0.5 440 1.66 0 +65 0.5 5 5 25 +1.3 +40 0 UNITS mA A MSPS MSPS MHz pF V mV mV V V A A mA mA ns LSB % Degrees ps ns mV mV IAD + IDD fC = 35 MSPS, NTSC Ramp Wave Input ISTB fC Max fC Min BW CADIN R REF V RT EOT EOB CE = DVDD VIN = 0V to 1.5V, fIN = 1kHz Ramp Reference Resistance (V RT to VRB) Self Bias Offset Voltage Digital Input Voltage V IH VIL Digital Input Current IIH IIL Digital Output Current IOH IOL Output Data Delay Integral Nonlinearity Error Differential Gain Error Differential Phase Error Aperture Jitter Sampling Delay Clamp Offset Voltage tDL EL DG DP tAJ tSD EOC 4-5 HI2301 Electrical Specifications PARAMETER Clamp Pulse Delay Amplifier Gain VIN1 and V IN2 Bias Voltage VIN1 and V IN2 Input Resistance VIN1 and V IN2 Input Capacitance VBI1, 2 RI1, 2 CI1, 2 Electrical Specifications; When using a single power supply (fC = 30 MSPS, AV DD = DVDD = +5V, VRB = 0V, VRT = 1.5V, TA = 25oC (Continued) SYMBOL tCPD DC To 15MHz When Open TEST CONDITIONS MIN 8.5 19 TYP 25 9.5 1.9 27 15 MAX 10.5 35 UNITS ns dB V kW pF Electrical Specifications When Using a Dual Power Supply (fC = 30 MSPS, AV DD = DVDD = +5V, VRT = 1.5V, VRT = 1.5V, TA = 25oC (2) When Using A Dual Power Supply fC = 30 MSPS, AVDD = 4.75V, DVDD = 0V, VRT = 1.5V, TA = 25oC Analog Supply Current Digital Supply Current Standby Supply Current Maximum Conversion Rate Minimum Conversion Rate ADIN Input Band (at -1dB) ADIN Input Capacitance Referenced Resistance (VRT to VRB ) Self Bias Offset Voltage IAD IDD ISTB fC Max fC Min BW CADIN RREF VRT EOT EOB Digital Input Voltage VIH VIL Digital Input Current IIH IIL Digital Output Current IOH IOL Output Data Delay Integral Nonlinearity Error Differential Nonlinearity Error Differential Gain Error Differential Phase Error Aperture Jitter Sampling delay Clamp Offset Voltage tDL EL ED DG DP tAJ tSD E OC VIN = DC PWS = 3s VREF = 0.5V V REF = 1.5V DVDD = Min DVDD = Max VIH = DVDD VIL = 0V VOH = VDD -0.5V VOL = 0.4V With TTL 1 Gate and 10pF Load fC = 30 MSPS, VIN = 0 to 1.5V fC = 30 MSPS, VIN = 0 to 1.5V NTSC 40 IRE Mod Ramp, fC = 14.3 MSPS VRB = AVSS VIN = 0.75V + 0.07VRMS fC = 30 MSPS, NTSC Ramp Wave Input fC = 30 MSPS, NTSC Ramp Wave Input CE = DVDD VIN = 0 to 1.5V fIN = 1kHz Ramp 30 230 1.44 -40 +25 2.5 -1.1 3.7 7 0 -40 DC to 15MHz VBI1, 2 RI1, 2 CI1, 2 When Open 8.5 19 24 1 130 20 8 330 1.52 -20 +45 -2.5 6.5 13 +0.5 0.3 1 0.5 30 2 +20 -20 25 9.5 1.8 27 15 32 2 200 0.5 440 1.6 0 +65 0.5 5 5 25 +1.3 0.5 +40 0 10.5 35 mA mA A MSPS MSPS MHz pF V mV mV V V A A mA mA ns LSB LSB % deg ps ns mV mV ns dB V k pF Clamp Pulse Delay 3x Amplifier Gain VIN1 and V IN2 Bias Voltage VIN1 and V IN2 Input Resistance VIN1 and V IN2 Input Capacitance tCPD 4-6 HI2301 Timing Chart tPW1 tPW0 CLOCK 2V ADIN INPUT N N+1 N+2 N+3 N+4 DATA OUTPUT N-3 tD N-2 N+1 N N-1 Application Circuits AC04 CLOCK IN LATCH CK (NOTE 2) Q +3.3V CLAMP PULSE IN +4.75V 0.1 0.1 0.1 20K VREF 0.1 25 0.1 26 27 75 28 29 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 D0 D1 D2 D3 D4 D5 D6 D7 VIDEO IN 0.1 10p 30 31 32 0.1 GND (ANALOG) GND (DIGITAL) NOTE: 2. Although the ADC sampling clock latches the clamp pule, it is not needed for basic clamp operation. However, depending on the relationship between the sampling frequency and the clamp pulse frequency, a small beat might be generated as VSAG . The latch circuit is valid at this time. FIGURE 1. CLAMP USAGE EXAMPLE (USING SELF BIAS, CIRCUIT WHEN USING THE INTERNAL AMPLIFIER) 4-7 HI2301 Application Circuits CLOCK IN +4.75V (Continued) ACO4 IN 0.1 0.1 +3.3V 0.1 VIDEO IN1 25 VIDEO IN2 0.1 26 27 0.1 75 28 29 30 0.1 31 32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 SUBTRACTER, COMPARATOR, ETC. CLAMP LEVEL SETTING DATA 1 2 3 4 5 6 7 8 DAC, PWM, ETC. GND (ANALOG) GND (DIGITAL) HIGH IMPEDANCE FOR ALL INFORMATION OUTSIDE THE CLAMP INTERVAL NOTES: 3. The relationship between the CCP voltage (Pin 32) variation and the ADIN voltage variation is position phase. 4. ADIN/VCCP = 3.0 (fS = 30 MSPS). FIGURE 2. DIGITAL CLAMP USAGE EXAMPLE (USING SELF BIAS), CIRCUIT WHEN USING THE INTERNAL AMPLIFIER 4-8 HI2301 Application Circuits (Continued) +3.3V (DIGITAL) ACO4 CLOCK IN 24 25 26 VIDEO IN 0.1 0.1 27 28 75 29 30 10p 31 32 1 2 23 0.1 0.1 0.1 22 21 20 19 18 17 16 15 14 13 12 11 10 9 3 4 5 6 7 8 GND (DIGITAL) GND (ANALOG) +3.3V (DIGITAL) D0 D1 D2 D3 D4 D5 D6 D7 +4.75V 0.1 0.1 FIGURE 3. WHEN NOT USING THE CLAMP, CIRCUIT WHEN USING THE INTERNAL AMPLIFIER 4-9 HI2301 Application Circuits (Continued) +4.75V ACO4 CLOCK IN CK Q 0.1 20K 0.1 0.1 +3.3V (DIGITAL) CLAMP PULSE IN LATCH (NOTE 5) +4.75V (ANALOG) 25 26 0.1 VIDEO IN (NOTE 6) 10 75 27 28 29 10p 30 31 32 0.01 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 GND (ANALOG) GND (DIGITAL) NOTES: 5. Although the ADC sampling clock latches the clamp pulse, it is not needed for basic clamp operation. However, depending on the relationship between the sampling frequency and the clamp pulse frequency, a small abeat might be generated as VSAG . The latch circuit is valid at this time. 6. Take care that the phase of ADIN input is inverted against the phase of the digital output, because the use of the built-in inverting amplifier is standard. (Refer to "Digital Output".) FIGURE 4. CLAMP USAGE EXAMPLE WHEN NOT USING THE INTERNAL AMPLIFIER 4-10 HI2301 Application Circuits (Continued) 0.1 0.1 +3.3V (DIGITAL) AC04 CLOCK IN 0.1 +4.75V (ANALOG) 25 26 0.1 VIDEO IN (NOTE 9) 10 75 27 28 29 10p 30 31 32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 CLAMP LEVEL SUBTRACTER, SETTING DATA COMPARATOR, ETC. 1 0.01 2 3 4 5 6 7 8 DAC, PWM, ETC. HIGH IMPEDANCE FOR ALL INFORMATION OUTSIDE THE CLAMP INTERVAL GND (ANALOG) GND (DIGITAL) NOTES: 7. The relationship between the CCP voltage (Pin 32) variation and the ADIN voltage variation is positive phase. 8. VADIN /VCCP = 3.0 (fS = 20 MSPS). 9. Take care that the phase of ADIN input is inverted against the phase of the digital output, because the use of the built-in inverting amplifier is standard. (Refer to "Digital Output.") FIGURE 5. DIGITAL CLAMP USAGE EXAMPLE 4-11 Application Circuits (Continued) 0.1 0.1 +3.3V (DIGITAL) ACOA CLOCK IN 0.1 +4.75V (ANALOG) 25 26 0.1 VIDEO IN (NOTE 10) 27 28 75 29 10P 30 31 32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 GND (DIGITAL) GND (ANALOG) +3.3V (DIGITAL) NOTE: 10. Take care that the phase of ADIN input is inverted against the phase of the digital output, because the use of the built-in inverting amplifier is standard. (Refer to "Digital Output".) FIGURE 6. WHEN NOT USING THE CLAMP Typical Performance Curves -10 CURRENT CONSUMPTION (mA) -20 -30 -40 -50 -60 -70 -80 VDD = 4.75V VIN = 150mVRMS VIN1 = GND VDD = 5V INPUT WAVEFORM IS RAMP WAVE VIN = 150mVRMS 40 CROSSTALK (dB) 30 1 5 10 fIN , INPUT FREQUENCY (MHz) 50 20 0.1 0.5 1 5 10 50 fIN , INPUT FREQUENCY (MHz) FIGURE 7. INPUT FREQUENCY OF VIN2 vs CROSSTALK VIN2 VIN1 FIGURE 8. INPUT FREQUENCY vs CURRENT CONSUMPTION 4-12 Typical Performance Curves CURRENT CONSUMPTION (mA) fIN = NTSC RAMP WAVE VIN = 150mVRMS 30 20 0.1 0.5 1 5 10 fS , SAMPLING FREQUENCY (MHz) FIGURE 9. SAMPLING FREQUENCY vs CURRENT CONSUMPTION 4-13 |
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