 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| RF2192 0 Typical Applications * 3V CDMA/AMPS Cellular Handsets * 3V JCDMA Cellular Handsets * 3V CDMA2000 Cellular Handsets Product Description The RF2192 is a high-power, high-efficiency linear amplifier IC targeting 3V handheld systems. The device is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been designed for use as the final RF amplifier in dual-mode 3V CDMA/AMPS and CDMA2000 handheld digital cellular equipment, spread-spectrum systems, and other applications in the 800MHz to 960MHz band. The RF2192 has a low power mode to extend battery life under low output power conditions. The device is packaged in a 16-pin, 4mmx4mm QFN. 0.10 C B -B- 3V 900MHz LINEAR POWER AMPLIFIER RoHS Compliant & Pb-Free Product * 3V TDMA/GAIT Cellular Handsets * 3V CDMA 450MHz Band Handsets * Portable Battery-Powered Equipment 4.00 0.10 C B 2 PLCS 3.75 2 PLCS 2.00 0.80 TYP 2 A 1.60 2 PLCS 3.75 0.75 0.50 INDEX AREA Dimensions in mm. 1.50 SQ. 4.00 0.10 C A 2 PLCS 0.45 0.28 3.20 2 PLCS 2.00 0.10 C A 2 PLCS Shaded pin is lead 1. 12 MAX 0.05 0.00 0.10 M C A B 1.00 0.90 0.75 0.65 C 0.05 Optimum Technology Matching(R) Applied Si BJT Si Bi-CMOS InGaP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS Package Style: QFN, 16-Pin, 4x4 Features * Single 3V Supply * 29dBm Linear Output Power VCC BIAS VCC1 VCC1 * 37% Linear Efficiency 2F0 GND * Low Power Mode * 45 mA idle current * 47% Peak Efficiency 31dBm Output 1 GND 2 GND 3 RF IN 4 5 VREG1 16 15 14 13 12 RF OUT 11 RF OUT 10 RF OUT Ordering Information RF2192 3V 900MHz Linear Power Amplifier RF2192PCBA-41X Fully Assembled Evaluation Board 6 VMODE 7 VREG2 8 BIAS GND 9 GND Functional Block Diagram RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Rev A8 060918 2-327 RF2192 Absolute Maximum Ratings Parameter Supply Voltage (RF off) Supply Voltage (POUT 31dBm) Mode Voltage (VMODE) Control Voltage (VREG) Input RF Power Operating Case Temperature Storage Temperature Rating +8.0 +5.2 +4.2 +3.0 +10 -30 to +110 -40 to +150 Unit VDC VDC VDC VDC dBm C C Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. RoHS marking based on EUDirective2002/95/EC (at time of this printing). However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Parameter Usable Frequency Range High Power StateUS-CDMA (VMODE Low) Frequency Range Linear Gain Second Harmonic Third Harmonic Maximum Linear Output Power (CDMA Modulation) Total Linear Efficiency Adjacent Channel Power Rejection Input VSWR Output VSWR Noise Power Specification Min. Typ. Max. 400 960 Unit MHz Condition Case T=25C, VCC =3.4V, VREG = 2.85V, VMODE =0V to 0.5V, Freq=824MHz to 849MHz (unless otherwise specified) 824 27 849 30 -33 <-60 29 37 -48 -58 2:1 MHz dB dBc dBc dBm % dBc dBc POUT =29dBm ACPR@885kHz ACPR@1980kHz No damage. No oscillations. >-70dBc At 45MHz offset Case T=25C, VCC =3.4V, VREG =2.85V, VMODE =1.8V to 3V, Freq=824MHz to 849MHz (unless otherwise specified) -44 -56 10:1 6:1 -133 dBm/Hz Low Power StateUS-CDMA (VMODE High) Frequency Range Linear Gain Second Harmonic Third Harmonic Maximum Linear Output Power (CDMA Modulation) Max ICC Adjacent Channel Power Rejection Input VSWR Output VSWR 824 19 849 22 -33 <-60 20 150 -48 <-60 2:1 MHz dB dBc dBc dBm mA dBc dBc 16 -46 -58 10:1 6:1 POUT =+16dBm (all currents included) ACPR@885kHz ACPR@1980kHz No damage. No oscillations. >-70dBc 2-328 Rev A8 060918 RF2192 Parameter High Power State CDMA 2000 1x (VMODE LOW) Frequency Range Linear Gain Pilot+DCCH 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection Pilot+FCH 9600+SCHO 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection 824 29 26.5 -47 <-60 29 -47 <-60 849 MHz dB dBm dBc dBc dBm dBc dBc 2.5dB Backoff included in IS98D CCDF 1% 5.4dB Peak Average Ratio at CCDF 1% ACPR@885kHz ACPR@1.98MHz 4.5dB Peak Average Ratio at CCDF 1% ACPR@885kHz ACPR@1.98MHz Case T=25oC, VCC =3.4V, VREG =2.85V. VMODE =1.8V to 3V, Freq=824MHz to 849MHz 824 22 16 20 -48 <-85 15 16 20 <-50 <-65 849 MHz dB dBm dBc dBc % dBm dBc dBc 5.4dB Peak to Average Ratio at CCDF 1% ACPR@885kHz ACPR@1.98MHz POUT =20dBm 4.5dB Peak to Average Ratio at CCDF 1% ACPR@885kHz ACPR@1.98MHz Case T=25C, VCC =3.4V, VREG =2.85V, VMODE =0V to 0.5V, Freq=824MHz to 849MHz (unless otherwise specified) Specification Min. Typ. Max. Unit Condition Case T=25oC, VCC =3.4V, VREG =2.85V. VMODE =0V to 0.5V, Freq=824MHz to 849MHz (unless otherwise specified) Low Power State CDMA 2000 1x (VMODE HIGH) Frequency Range Linear Gain Pilot+DCCH 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection Efficiency Pilot+FCH 9600+SCHO 9600 Maximum Linear Output Power (CDMA 2000 Modulation) Adjacent Channel Power Rejection FM Mode Frequency Range Gain Second Harmonic Third Harmonic Max CW Output Power Total Efficiency (AMPS mode) Input VSWR Output VSWR 824 30 -33 <-60 32 47 2:1 10:1 6:1 849 MHz dB dBc dBc dBm % 31 POUT =31dBm (room temperature) No damage. No oscillations. >-70dBc Note: DCCH: Dedicated Control Channel FCH: Fundamental Channel CCDF: Complementary Cumulative Distribution Function Rev A8 060918 2-329 RF2192 Parameter High Power StateCDMA450 (VMODE Low) Frequency Range Linear Gain Second Harmonic Third Harmonic Maximum Linear Output Power (CDMA Modulation) Total Linear Efficiency Adjacent Channel Power Rejection Input VSWR Output VSWR 452 31 30 -60 29 35 -49 -56 2:1 10:1 6:1 458 MHz dB dBc dBc dBm % dBc dBc POUT =29dBm ACPR @ 885kHz ACPR @ 1980kHz No damage. No oscillations. > -70dBc Case T=25oC, VCC =3.4V, VREG =2.85V, VMODE =2.85V, Freq=452MHz to 458MHz (unless otherwise specified) 452 23 16 160 -52 -70 2:1 10:1 6:1 3.0 3.4 160 45 4.2 V mA mA mA mA s 458 MHz dB dBm mA dBc dBc POUT =+16dBm (all currents included) ACPR @ 885kHz ACPR @ 1980kHz No damage. No oscillations. > -70dBc The maximum power out for VCC =3.0V is 28dBm. VMODE =Low VMODE =High Specification Min. Typ. Max. Unit Condition Case T=25oC, VCC =3.4V, VREG =2.85V, VMODE =0V to 0.5V, Freq=452MHz to 458MHz (unless otherwise specified) Low Power StateCDMA450 (VMODE High) Frequency Range Linear Gain Maximum Linear Output Power (CDMA Modulation) Max ICC Adjacent Channel Power Rejection Input VSWR Output VSWR DC Supply Supply Voltage Quiescent Current VREG Current VMODE Current Turn On/Off Time 70 10 1 <40 Total Current (Power Down) VREG "Low" Voltage VREG "High" Voltage VMODE "Low" Voltage VMODE "High" Voltage 0 2.75 0 1.8 2.85 2.85 10 0.5 2.95 0.5 3.0 A V V V V Time between VREG turned on and PA reaching full power. Turn on/off time can be reduced by lowering the bypass capacitor value on the VREG line. VREG =Low 2-330 Rev A8 060918 RF2192 Pin 1 2 3 4 Function GND GND GND RF IN Description Ground connection. Ground connection. Ground connection. RF input. An external 100pF series capacitor is required as a DC block. In addition, shunt inductor and series capacitor are required to provide 2:1VSWR. RF IN From Bias GND1 Stages VCC1 100 pF Interface Schematic 5 6 7 8 9 10 VREG1 VMODE VREG2 BIAS GND GND RF OUT Power Down control for first stage. Regulated voltage supply for amplifier bias. In Power Down mode, both VREG and VMODE need to be LOW (<0.5V). For nominal operation (High Power Mode), VMODE is set LOW. When set HIGH, the driver and final stage are dynamically scaled to reduce the device size and as a result to reduce the idle current. Power Down control for the second stage. Regulated voltage supply for amplifier bias. In Power Down mode, both VREG and VMODE need to be LOW (<0.5V). Bias circuitry ground. See application schematic. Ground connection. RF output and power supply for final stage. This is the unmatched collector output of the second stage. A DC block is required following the matching components. The biasing may be provided via a parallel L-C set for resonance at the operating frequency of 824MHz to 849MHz. It is important to select an inductor with very low DC resistance with a 1A current rating. Alternatively, shunt microstrip techniques are also applicable and provide very low DC resistance. Low frequency bypassing is required for stability. Same as pin 10. Same as pin 10. Harmonic trap. This pin connects to the RF output but is used for providing a low impedance to the second harmonic of the operating frequency. An inductor or transmission line resonating with an on chip capacitor at 2fo is required at this pin. Power supply for bias circuitry. A 100pF high frequency bypass capacitor is recommended. Power supply for first stage. Same as Pin 15. Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. The pad should have a short thermal path to the ground plane. RF OUT From Bias Stages 11 12 13 RF OUT RF OUT 2FO See pin 10. 14 15 16 Pkg Base VCC BIAS VCC1 VCC1 GND Note: This schematic is a preliminary schematic. This 450MHz band CDMA tune is done by modifying the existing 800MHz band CDMA evaluation board. Rev A8 060918 2-331 RF2192 Evaluation Board Schematic US-CDMA (Download Bill of Materials from www.rfmd.com.) VCC C2 4.7 uF C6 100 pF C28 10 nF C4 100 pF C25 4.7 F C30 TL3 L5 1 nH TL5 1 C9 100 pF R2 510 C24 12 pF C27 100 pF R3 0 R4 0 C26 4.7 F VREG VMODE R1 0 C13 100 pF L4 39 nH Board C30 (pF) CDMA (US) 100 Transmission Line Length CDMA (US) C1 (pF) 9.1 L1 (nH) 20 C14 (pF) 9.1 2 3 4 L2 5.6 nH 5 6 7 8 16 15 14 13 12 11 10 9 * L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). **C1 and C14 are High Q capacitors (i.e., Johanson C-series). L1* C17 2.4 pF C3 100 pF TL1 TL2 C1** J1 RF IN C5 100 pF J4 RF OUT C14** TL1 15 mils TL2 350 mils TL3 105 mils TL5 85 mils 2-332 Rev A8 060918 RF2192 Application Schematic CDMA-450MHz Band P1-1 4.7 F 100 pF 470 pF 6.8 nH 10 nF 6.8 nH TL4 TL5 100 pF 4.7 uF 1 100 pF 2 3 4 12 nH 27 pF 5 16 15 14 13 12 11 10 TL1 L1* 7.5 pF C140** TL2 1.2 nH TL6 RF OUT C14** C3 100 pF 100 pF RF IN 510 C1** C100** 6 7 8 9 * L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). **C1, C100, C14, and C140 are High Q capacitors (i.e., Johanson C-series). 0 100 pF 0 100 pF 39 nH Board CDMA (450 MHz) Transmission Line Length C100 (pF) C140 (pF) C1 (pF) 15 13 15 L1 (nH) 20 C14 (pF) 13 4.7 F TL1 15 mils TL2 125 mils TL6 220 mils TL4 L=40 mils TL5 L=75 mils P2-1 P2-2 0 Rev A8 060918 2-333 RF2192 Evaluation Board Layout - US-CDMA 2.0" x 2.0" Board Thickness 0.031", Board Material FR-4, Multi-Layer, Ground Plane at 0.015" 2-334 Rev A8 060918 RF2192 PCB Design Requirements PCB Surface Finish The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land Pattern A = 0.51 x 0.89 (mm) Typ. B = 0.89 x 0.51 (mm) Typ. C = 1.52 (mm) Sq. 3.20 Typ. 0.81 Typ. Dimensions in mm. Pin 1 A 1.73 Typ. 0.81 Typ. B B 0.94 Typ. A A A A A B C B 0.81 Typ. B B 1.60 Typ. A A A A 1.60 Typ. 1.73 Typ. Figure 1. PCB Metal Land Pattern (Top View) Rev A8 060918 2-335 RF2192 PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB Metal Land Pattern with a 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier. A = 0.71 x 1.09 (mm) Typ. B = 1.09 x 0.71 (mm) Typ. C = 1.73 (mm) Sq. 3.20 Typ. 0.81 Typ. Pin 1 Dimensions in mm. A 1.73 Typ. 0.81 Typ. B B 0.94 Typ. A A A A A B C B B B 0.81 Typ. 1.60 Typ. A A A A 1.60 Typ. 1.73 Typ. Figure 2. PCB Solder Mask (Top View) Thermal Pad and Via Design The PCB metal land pattern has been designed with a thermal pad that matches the exposed die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. 2-336 Rev A8 060918 |
Price & Availability of RF2192PCBA-41X
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |