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| 33LV408 4 Megabit (512K x 8-Bit) CMOS SRAM 33LV408 Memory Logic Diagram FEATURES: * RAD-PAK(R) Technology radiation-hardened against natural space radiation * 524,288 x 8 bit organization * Total dose hardness: - > 100 krad (Si), depending upon space mission * Excellent Single Event Effect * - SELTH: > 101 MeV/mg/cm2 * - SEUTH: = 3 MeV/mg/cm2 * * * * * * * - SEU saturated cross section: 6E-9 cm2/bit Package: - 32-Pin RAD-PAK(R) flat pack Fast access time: - 20, 25, 30 ns maximum times available Single 3.3V + 10% power supply Fully static operation - No clock or refresh required Three state outputs TTL compatible inputs and outputs Low power: - Standby: 60 mA (TTL); 10 mA (CMOS) - Operation: 150 mA (20 ns); 140 mA (25 ns); 130 mA (30 ns) DESCRIPTION: Maxwell Technologies' 33LV408 high-density 4 Megabit SRAM microcircuit features a greater than 100 krad (Si) total dose tolerance, depending upon space mission. Using Maxwell's radiation-hardened RAD-PAK(R) packaging technology, the 33LV408 realizes a high density, high performance, and low power consumption. Its fully static design eliminates the need for external clocks, while the CMOS circuitry reduces power consumption and provides higher reliability. The 33LV408 is equipped with eight common input/output lines, chip select and output enable, allowing for greater system flexibility and eliminating bus contention. The 33LV408 features the same advanced 512K x 8-bit SRAM, high-speed, and low-power demand as the commercial counterpart. Maxwell Technologies' patented RAD-PAK(R) packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK(R) provides greater than 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S. 04.02.04 REV 2 All data sheets are subject to change without notice 1 (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com (c)2004 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM TABLE 1. PINOUT DESCRIPTION PIN 12-5, 27, 26, 23, 25, 4, 28, 3, 31, 2, 30, 1 29 22 24 13-15, 17-21 32 16 SYMBOL A0-A18 WE CS OE I/O 1-I/O 8 VCC VSS DESCRIPTION Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power Ground 33LV408 TABLE 2. 33LV408 ABSOLUTE MAXIMUM RATINGS Memory PARAMETER Voltage on VCC supply relative to VSS Voltage on any pin relative to VSS Power Dissipation Storage Temperature Operating Temperature SYMBOL VCC VIN, VOUT PD TS TA MIN -0.5 -0.5 --65 -55 MAX 7.0 VCC +0.5 1.0 +150 +125 UNIT V V W C C TABLE 3. DELTA LIMITS PARAMETER ICC ISB ISB1 VARIATION 10% of stated vaule in Table 6 10% of stated vaule in Table 6 10% of stated vaule in Table 6 04.02.04 REV 2 All data sheets are subject to change without notice 2 (c)2004 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM TABLE 4. 33LV408 RECOMMENDED OPERATING CONDITIONS (VCC = 3.3 + 10%, TA = -55 TO +125 C, UNLESS OTHERWISE NOTED) PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage Weight 1. VIH (max) = VCC +2.0V ac (pulse width < 10 ns) for I < 20 mA 2. VIL (min) = -2.0V ac(pulse width < 10 ns) for I < 20 mA 1 2 33LV408 SYMBOL VCC VSS VIH VIL MIN 3.0 0 2.2 -0.3 -MAX 3.6 0 VCC+0.3 0.8 1.21 12 UNIT V V V V C/W Grams Thermal Impedance JC TABLE 5. 33LV408 CAPACITANCE (f = 1.0 MHZ, VCC = 3.3 V, TA = 25 C) PARAMETER Input Capacitance1 CS1 - CS4, OE, WE I/O0-7, I/O8-15, I/O16-23, I/O24-31 Input / Output Capacitance1 1. Guaranteed by design. SYMBOL CIN TEST CONDITIONS VIN = 0 V 7 28 7 COUT VI/O = 0 V 8 pF MAX UNITS pF Memory TABLE 6. 33LV408 DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V + 10%, TA = -55 TO +125 C, UNLESS OTHERWISE SPECIFIED) PARAMETER Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Current -20 -25 -30 Standby Power Supply Current SYMBOL CONDITION ILI ILO VOL VOH ICC VIN = VSS to VCC CS=VIH or OE=VIH or WE=VIL, VOUT =VSS to VCC IOL = 8mA IOH = -4mA Min cycle, 100% Duty, CS=VIL, IOUT=0mA, VIN = VIH or VIL SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 ---1, 2, 3 -150 140 130 60 mA MIN -2 -2 -2.4 MAX 2 2 0.4 -UNIT A A V V mA ISB CS = VIH, Min Cycle 04.02.04 REV 2 All data sheets are subject to change without notice 3 (c)2004 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM TABLE 6. 33LV408 DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V + 10%, TA = -55 TO +125 C, UNLESS OTHERWISE SPECIFIED) PARAMETER Standby Power Supply Current - CMOS Input Capacitance 1 Output Capacitance 1 1. Guaranteed by design. SYMBOL CONDITION ISB1 CIN CI/O CS > VCC - 0.2V; VIN > VCC - 0.2V or VIN < 0.2V VIN = 0V, f = 1MHz, TA = 25 C VI/O = 0V SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 MIN ---- 33LV408 MAX 10 7 8 UNIT mA pF pF TABLE 7. 33LV408 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 3.3 + 10%, TA = -55 TO +125 C, UNLESS OTHERWISE NOTED) PARAMETER Input Pulse Level Output Timing Measurement Reference Level Input Rise/Fall Time Input Timing Measurement Reference Level MIN 0.0 ---TYP ----MAX 3.0 1.5 3.0 1.5 UNITS V V ns V Memory TABLE 8. 33LV408 AC CHARACTERISTICS FOR READ CYCLE (VCC = 3.3V + 10%, TA = -55 TO +125 C, UNLESS OTHERWISE SPECIFIED) PARAMETER Read Cycle Time -20 -25 -30 Address Access Time -20 -25 -30 Chip Select Access Time -20 -25 -30 Output Enable to Output Valid -20 -25 -30 Chip Enable to Output in Low-Z -20 -25 -30 SYMBOL tRC SUBGROUPS 9, 10, 11 20 25 30 tAA 9, 10, 11 ---tCO 9, 10, 11 ---tOE 9, 10, 11 ---tLZ 9, 10, 11 ---3 3 3 ------10 12 14 ns ---20 25 30 ---20 25 30 ns ------ns MIN TYP MAX UNIT ns ns 04.02.04 REV 2 All data sheets are subject to change without notice 4 (c)2004 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM TABLE 8. 33LV408 AC CHARACTERISTICS FOR READ CYCLE (VCC = 3.3V + 10%, TA = -55 TO +125 C, UNLESS OTHERWISE SPECIFIED) PARAMETER Output Enable to Output in Low-Z -20 -25 -30 Chip Deselect to Output in High-Z -20 -25 -30 Output Disable to Output in High-Z -20 -25 -30 Output Hold from Address Change -20 -25 -30 Chip Select to Power Up Time -20 -25 -30 Chip Select to Power Down Time -20 -25 -30 SYMBOL tOLZ SUBGROUPS 9, 10, 11 ---tHZ 9, 10, 11 ---tOHZ 9, 10, 11 ---tOH 9, 10, 11 3 5 6 tPU 9, 10, 11 ---tPD 9, 10, 11 ---10 15 20 ---0 0 0 ---------5 6 8 ---5 6 8 ---0 0 0 ---MIN TYP 33LV408 MAX UNIT ns ns ns ns Memory ns ns TABLE 9. 33LV408 FUNCTIONAL DESCRIPTION CS H L L L 1. X = don't care. WE X1 H H L OE X1 H L X1 MODE Not Select Output Disable Read Write I/O PIN High-Z High-Z DOUT DIN SUPPLY CURRENT ISB, ISB1 ICC ICC ICC 04.02.04 REV 2 All data sheets are subject to change without notice 5 (c)2004 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM TABLE 10. 33LV408 AC CHARACTERISTICS FOR WRITE CYCLE (VCC = 3.3V + 10%, TA = -55 TO +125 C, UNLESS OTHERWISE SPECIFIED) PARAMETER Write Cycle Time -20 -25 -30 Chip Select to End of Write -20 -25 -30 Address Setup Time -20 -25 -30 Address Valid to End of Write -20 -25 -30 Write Pulse Width (OE High) -20 -25 -30 Write Recovery Time -20 -25 -30 Write to Output in High-Z -20 -25 -30 Write Pulse Width (OE Low) -20 -25 -30 Data to Write Time Overlap -20 -25 -30 End Write to Output Low-Z -20 -25 -30 SYMBOL tWC SUBGROUPS 9, 10, 11 20 25 30 tCW 9, 10, 11 14 15 17 tAS 9, 10, 11 0 0 0 tAW 9, 10, 11 14 15 17 tWP 9, 10, 11 14 15 17 tWR 9, 10, 11 0 0 0 tWHZ 9, 10, 11 ---tWP1 9, 10, 11 ---tDW 9, 10, 11 9 10 11 tOW 9, 10, 11 ---6 7 8 ---20 25 30 5 5 6 ------------------MIN TYP 33LV408 MAX ---- UNIT ns ns ---ns ---ns ---ns ---ns ---ns ---ns ---ns ---ns ---- Memory 04.02.04 REV 2 All data sheets are subject to change without notice 6 (c)2004 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM TABLE 10. 33LV408 AC CHARACTERISTICS FOR WRITE CYCLE (VCC = 3.3V + 10%, TA = -55 TO +125 C, UNLESS OTHERWISE SPECIFIED) PARAMETER Data Hold from Write Time -20 -25 -30 SYMBOL tDH SUBGROUPS 9, 10, 11 0 0 0 ---MIN TYP 33LV408 MAX ---UNIT ns FIGURE 1: TIMING WAVEFORM OF READ CYCLE(1) Memory FIGURE 2: TIMING WAVEFORM OF READ CYCLE (2) Read Cycle Notes: 1. WE is high for read cycle. 2. All read cycle timing is referenced form the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. 5. 6. At any given temperature and voltage condition, tHZ(max) is less than tLZ(min) both for a given device and from device to device. Transition is measured + 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. Device is continuously selected with CS = VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention condition is necessary during read and write cycle. 04.02.04 REV 2 All data sheets are subject to change without notice 7 (c)2004 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM FIGURE 3: TIMING WAVEFORM OF WRITE CYCLE(1) 33LV408 Memory FIGURE 4: TIMING WAVEFORM OF WRITE CYCLE(2) 04.02.04 REV 2 All data sheets are subject to change without notice 8 (c)2004 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM FIGURE 5: TIMING WAVEFORM OF WRITE CYCLE (3) 33LV408 Memory WRITE CYCLE NOTE: 1. 2. All write cycle timing is referenced from the last valid address to the first transition address. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and WE going low: A write ends at the earliest transition among CS going high and WE going high. t is measured from beginning of write to the end of write. t is measured from the later of CS going low to end of write. t is measured from the address valid to the beginning of write. t is measured form the end of write to the address change. TWR applied in case a write ends as CS, or WR going high. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state. D is the read data of the new address. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. WP CW AS WR OUT 3. 4. 5. 6. 7. 8. 9. 10. 04.02.04 REV 2 All data sheets are subject to change without notice 9 (c)2004 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM 33LV408 Memory 32 PIN RAD-PAK(R) FLAT PACKAGE SYMBOL MIN A b c D E E1 E2 E3 e L Q S1 N 0.390 0.088 -0.122 0.015 0.008 -0.635 -0.550 -DIMENSION NOM 0.135 0.017 0.010 0.930 0.645 -0.565 0.040 0.050 BSC 0.400 0.098 0.082 32 Note: All dimensions in inches 0.410 .108 -MAX 0.155 0.019 0.012 0.940 0.655 0.690 --- 04.02.04 REV 2 All data sheets are subject to change without notice 10 (c)2004 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM Important Notice: 33LV408 These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies' products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies' liability shall be limited to replacement of defective parts. Memory 04.02.04 REV 2 All data sheets are subject to change without notice 11 (c)2004 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM Product Ordering Options Model Number 33LV408 33LV408 XX F X -XX Feature Access Time Option Details 20 = 20 ns 25 = 25 ns 30 = 30 ns Screening Flow Monolithic S = Maxwell Class S B = Maxwell Class B I = Industrial (testing @ -55C, +25C, +125C) E = Engineering (testing @ +25C) Memory Package F = Flat Pack Radiation Feature RP = RAD-PAK(R) package Base Product Nomenclature 4 Megabit CMOS SRAM 04.02.04 REV 2 All data sheets are subject to change without notice 12 (c)2004 Maxwell Technologies All rights reserved. |
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