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| CMOS Logic Hex Non-Inverting Buffers 54HC4050 Logic Diagram Memory FEATURES: * High speed CMOS logic hex non-inverting buffers * RAD-PAK(R) radiation hardened against natural space radiation * Single Event Effects: - SEL: > 120 MeV/mg/cm2 * Total dose hardness: * - > 100 Krad (Si), depending upon space mission * Package: -16 Pin RAD-PAK(R) Flat Pack * Typical propagation delay: - 6ns at VCC = 5V, CL = 15pF, TA = 25C * High-to-Low voltage level converter for up to VI = 16V * Fanout (over temperature range) -10 LSTTL loads (Standard Outputs) -15 LSTTL loads (Bus Driver Outputs) * Balanced propagation delay and transition times * Significant power reduction compared to LSTTL logic ICs * 2V to 6V operation * High noise immunity * -NIL = 30%, NIH = 30% of VCC at VCC = 5V DESCRIPTION: Maxwell Technologies' 54HC4050 high speed CMOS Logic Hex Non-Inverting Buffers features a greater than 100 krad(Si) total dose tolerance, depending upon space mission. These parts have a modified input protection structure that enables them to be used as logic level translators which will convert high-level logic to a low-level logic while operating off the lowlevel logic supply. For example, 15V input pulse levels can be down-converted to 0V to 5V logic levels. The modified input protection structure protects the input from negative electrostatic discharge. The 54HC4050 can be used as simple buffers or inverters without level translation. Maxwell Technologies' patented RAD-PAK(R) packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides greater than 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S. 1000587 12.19.01 Rev 1 All data sheets are subject to change without notice 1 (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com (c)2001 Maxwell Technologies. All rights reserved. CMOS Logic Hex Non-Inverting Buffers TABLE 1. 54HC4050 PINOUT DESCRIPTIONS PIN 1 8 13, 16 3, 5, 7, 9, 11, 14 2 4 6 10 12 15 SYMBOL VCC VSS NC A-F G=A H=B I=C J=D K=E L=F DESCRIPTION Power supply Ground Not Connected Inputs Buffered Output Buffered Output Buffered Output Buffered Output Buffered Output Buffered Output 54HC4050 Memory TABLE 2. 54HC4050 ABSOLUTE MAXIMUM RATINGS PARAMETER Storage Temperature Operating Temperature Range DC Supply Voltage DC Input Diode Current For VI < -0.5V or VI > VCC +0.5V DC Output Diode Current For VO < -0.5V or VO > VCC +0.5V DC Output Source or Sink Current per Output Pin For VO > -0.5V or VO < VCC +0.5V DC VCC or Ground Current SYMBOL TS TA VCC IIK IOK IO ICC or IGND MIN -65 -55 -0.5 -20 -20 -25 -50 MAX 150 125 7.0 +20 +20 +25 +50 UNIT C C V mA mA mA mA TABLE 3. DELTA LIMITS PARAMETER ICC VARIATION 10% of specified value in Table 5 1000587 12.19.01 Rev 1 All data sheets are subject to change without notice 2 (c)2001 Maxwell Technologies. All rights reserved. CMOS Logic Hex Non-Inverting Buffers TABLE 4. 54HC4050 RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage DC Input or output Voltage Input Rise and Fall Time 2V 4.5V 6V Temperature Range TA SYMBOL VCC VI, VO MIN 2 0 -1000 500 400 -55 125 MAX 6 VCC 54HC4050 UNIT V V ns C TABLE 5. 54HC4050 DC ELECTRICAL CHARACTERISTICS (VCC = 5V 10%, TA = -55 TO 125C, UNLESS OTHERWISE SPECIFIED) PARAMETER High Level Output Voltage CMOS Loads SYMBOL VOH TEST CONDITIONS VI = VIH or VIL, IO = -0.02mA VCC = 2V VCC = 4.5V VCC = 6V VI = VIH or VIL, IO = -4mA VCC = 4.5V VI = VIH or VIL, IO = -5.2mA VCC = 6V Low Level Output Voltage CMOS Loads VOL VI = VIH or VIL, IO = -0.02mA VCC = 2V VCC = 4.5V VCC = 6V VI = VIH or VIL, IO = 4mA VCC = 4.5V VI = VIH or VIL, IO = 5.2mA VCC = 6V High Level Input Voltage VIH VCC = 2V VCC = 4.5V VCC = 6V VCC = 2V VCC = 4.5V VCC = 6V VCC = 6V, VI = VCC or GND VCC = 6V, VI = 15V +25C -55 to 125C +25C -55 to 125C 1000587 12.19.01 Rev 1 MIN 1.9 4.4 5.9 +25C -55 to 125C +25C -55 to 125C 3.98 3.7 5.48 5.2 MAX ------- UNIT V Memory High Level Output Voltage TTL Loads V 0.1 0.1 0.1 +25C -55 to 125C +25C -55 to 125C 0.26 0.4 0.36 0.4 1.5 3.15 4.2 --------------0.5 1.35 1.8 0.1 1 0.5 5 V Low Level Output Voltage TTL Loads Low Level Input Voltage VIL V Input Leakage Current II A All data sheets are subject to change without notice 3 (c)2001 Maxwell Technologies. All rights reserved. CMOS Logic Hex Non-Inverting Buffers TABLE 5. 54HC4050 DC ELECTRICAL CHARACTERISTICS (VCC = 5V 10%, TA = -55 TO 125C, UNLESS OTHERWISE SPECIFIED) PARAMETER Quiescent Device Current SYMBOL ICC TEST CONDITIONS VI = VCC or GND, IO = 0mA VCC = 6V +25C -55 to 125C MIN --- 54HC4050 MAX 2 40 UNIT A TABLE 6. 54HC4050 AC ELECTRICAL CHARACTERISTICS (VCC = 5V 10%, TA = -55 TO 125C, UNLESS OTHERWISE SPECIFIED) PARAMETER Propogation Delay nA to nY SYMBOL tPLH, tPHL CL = 50pF VCC = 2V VCC = 4.5V VCC = 6V Transition Times (Figure 1) tTLH, tTHL CL = 50pF VCC = 2V VCC = 4.5V VCC = 6V TEST CONDITION +25C --55 to 125C +25C -55 to 125C +25C -55 to 125C +25C --55 to 125C +25C -55 to 125C +25C -55 to 125C -----75 110 15 22 13 19 -----85 130 17 26 MIN MAX UNIT ns Memory 14 22 ns TABLE 7. 54HC4050 CAPACITANCE1 PARAMETER Input Capacitance Power Dissipation Capacitance2, 3 SYMBOL CI CPD VCC = 5V TEST CONDITIONS MAX 10 35 UNIT pF pF 1. Guaranteed by design. 2. CPD is used to determine the dynamic power consumption, per gate. 3. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 1000587 12.19.01 Rev 1 All data sheets are subject to change without notice 4 (c)2001 Maxwell Technologies. All rights reserved. CMOS Logic Hex Non-Inverting Buffers 54HC4050 FIGURE 1. TRANSITION TIMES AND PROPOGATION DELAY TIMES, COMBINATION LOGIC Memory 1000587 12.19.01 Rev 1 All data sheets are subject to change without notice 5 (c)2001 Maxwell Technologies. All rights reserved. CMOS Logic Hex Non-Inverting Buffers 54HC4050 Memory 16-PIN RAD-PAK(R) FLAT PACKAGE SYMBOL MIN A b c D E E1 E2 E3 e L Q S1 N 0.325 0.020 0.005 0.115 0.015 0.004 0.407 0.275 -0.150 0.030 DIMENSION NOM 0.135 0.017 0.005 0.415 0.280 -0.156 0.062 0.050 BSC 0.335 0.033 0.024 16 0.345 0.045 0.045 MAX 0.150 0.019 0.007 0.423 0.285 0.500 0.162 -- F16-01 Note: All dimensions in inches 1000587 12.19.01 Rev 1 All data sheets are subject to change without notice 6 (c)2001 Maxwell Technologies. All rights reserved. CMOS Logic Hex Non-Inverting Buffers Important Notice: 54HC4050 These data sheets are created using the chip manufacturer's published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies' products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies' liability shall be limited to replacement of defective parts. Memory 1000587 12.19.01 Rev 1 All data sheets are subject to change without notice 7 (c)2001 Maxwell Technologies. All rights reserved. CMOS Logic Hex Non-Inverting Buffers Product Ordering Options Model Number 54HC4050 RP F X Feature 54HC4050 Option Details Screening Flow Monolithic S = Maxwell Class S B = Maxwell Class B E = Engineering (testing @ +25C) I = Industrial (testing @ -55C, +25C, +125C) Memory Package F = Flat Pack Radiation Feature RP = RAD-PAK(R) package Base Product Nomenclature CMOS Logic Hex Non-Inverting Buffers 1000587 12.19.01 Rev 1 All data sheets are subject to change without notice 8 (c)2001 Maxwell Technologies. All rights reserved. |
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