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74F620 * 74F623 Inverting Octal Bus Transceiver with 3-STATE Outputs
April 1988 Revised August 1999
74F620 * 74F623 Inverting Octal Bus Transceiver with 3-STATE Outputs
General Description
These devices are octal bus transceivers designed for asynchronous two-way data flow between the A and B busses. Both busses are capable of sinking 64 mA and have 3STATE outputs. Dual enable pins (GAB, GBA) allow data transmission from the A bus to the B bus or from the B bus to the A bus. The 74F620 is an inverting option of the 74F623.
Features
s Designed for asynchronous two-way data flow between busses s Outputs sink 64 mA s Dual enable inputs control direction of data flow s Guaranteed 4000V minimum ESD protection s 74F620 is an inverting option of the 74F623
Ordering Code:
Order Number 74F620PC 74F623SC 74F623PC Package Number N20A M20B N20A Package Description 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
FAST(R) is a registered trademark of Fairchild Semiconductor Corporation
(c) 1999 Fairchild Semiconductor Corporation
DS009577
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74F620 * 74F623
Unit Loading/Fan Out
Pin Names GBA, GAB A0-A7 B0-B7 Description Enable Inputs A Inputs or 3-STATE Outputs B Inputs or 3-STATE Outputs U.L. HIGH/LOW 1.0/1.0 3.5/1.083 150/40 3.5/1.083 150/40 Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 70 A/-0.4 mA -3 mA/64 mA 70 A/-0.4 mA -3 mA/64 mA
Functional Description
The enable inputs GAB and GBA control whether data is transmitted from the A bus to the B bus or from the B bus to the A bus. If both GBA and GAB are disabled (GBA HIGH and GAB LOW), the outputs are in the high impedance state and data is stored at the A and B busses. When GBA is active LOW, B data is sent to the A bus. When GAB is active HIGH, data from the A bus is sent to the B bus. If both enable inputs are active (GBA LOW and GAB HIGH) B data is sent to the A bus while A data is sent to the B bus.
Function Table
Enable Inputs GBA L H H L GAB L H L H 74F620 B Data to A Bus A Data to B Bus Z B Data to A Bus, A Data to B Bus
H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance
Operation 74F623 B Data to A Bus A Data to B Bus Z B Data to A Bus, A Data to B Bus
Logic Diagrams
74F620
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F623
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F620 * 74F623
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI IBVIT ICEX VID IOD IIL IIH + IOZH IIL + IOZL IOS IZZ ICCH ICCL ICCZ ICCH ICCL ICCZ Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown (I/O) Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current (74F620) Power Supply Current (74F620) Power Supply Current (74F620) Power Supply Current (74F623) Power Supply Current (74F623) Power Supply Current (74F623) -100 4.75 3.75 -0.6 70 -650 -225 500 82 82 95 65 82 85 10% VCC 10% VCC 2.0 0.55 5.0 7.0 0.5 50 Min 2.0 0.8 -1.2 Typ Max Units V V V V V A A mA A V A mA A A mA A mA mA mA mA mA mA Min Min Min Max Max Max Max 0.0 0.0 Max Max Max Max 0.0V Max Max Max Max Max Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA (Non I/O Pins) IOH = -15 mA (An, Bn) IOL = 64 mA (A n, Bn) VIN = 2.7V VIN = 7.0V (GBA, GAB) VIN = 5.5V (An, Bn) VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (Non I/O Pins) VOUT = 2.7V (An, Bn) VOUT = 0.5V (An, Bn) VOUT = 0V VOUT = 5.25V VO = HIGH, VIN = 0.2V VO = LOW VO = HIGH Z VO = HIGH VO = LOW, VIN = 0.2V VO = HIGH Z
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74F620 * 74F623
AC Electrical Characteristics
TA = +25C Symbol Parameter Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Propagation Delay A Input to B Output (74F620) Propagation Delay B Input to A Output (74F620) Propagation Delay A Input to B Output (74F623) Propagation Delay B Input to A Output (74F623) Enable Time GBA Input to A Output Disable Time GBA Input to A Output Enable Time GAB Input to B Output (74F620) Disable Time GAB Input to B Output (74F620) Enable Time GAB Input to B Output (74F623) Disable Time GAB Input to B Output (74F623) 2.5 2.0 2.5 2.0 1.5 2.0 1.5 2.0 2.0 2.5 1.5 1.0 2.0 3.0 2.5 2.0 2.0 2.5 2.0 2.0 VCC = +5.0V CL = 50 pF Typ Max 7.5 7.0 7.5 7.0 6.5 7.0 6.5 7.0 7.0 8.0 6.5 5.5 7.5 8.0 8.0 7.5 7.5 8.0 8.0 8.0 TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 2.0 2.0 2.0 2.0 1.5 2.0 1.5 2.0 2.0 2.0 1.5 1.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 Max 8.0 7.0 8.0 7.0 7.5 7.5 7.5 7.5 8.0 8.5 7.5 5.5 8.5 8.5 9.0 8.0 8.5 8.5 9.0 8.0 ns ns ns ns ns ns ns Units
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74F620 * 74F623
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B
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74F620 * 74F623 Inverting Octal Bus Transceiver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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