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| 74LCX138 LOW VOLTAGE CMOS 3 TO 8 LINE DECODER (INV.) WITH 5V TOLERANT INPUTS s s s s s s s s s s 5V TOLERANT INPUTS HIGH SPEED: tPD = 6.7ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V SOP TSSOP Table 1: Order Codes PACKAGE SOP TSSOP T&R 74LCX138MTR 74LCX138TTR DESCRIPTION The 74LCX138 is a low voltage CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for inputs. If the device is enabled, 3 binary select inputs (A, B and C) determine which one of the outputs will Figure 1: Pin Connection And IEC Logic Symbols go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go to high. Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. September 2004 Rev. 4 1/12 74LCX138 Figure 2: Input And Output Equivalent Circuit Table 2: Pin Description PIN N 1, 2, 3 4, 5 6 15, 14, 13, 12, 11, 10, 9, 7 8 16 SYMBOL A, B, C G2A, G2B G1 Y0 to Y7 GND VCC NAME AND FUNCTION Address Inputs Enable Inputs Enable Input Outputs Ground (0V) Positive Supply Voltage Table 3: Truth Table INPUTS OUTPUTS ENABLE G2B X X H L L L L L L L L G2A X H X L L L L L L L L G1 L X X H H H H H H H H C X X X L L L L H H H H SELECT B X X X L L H H L L H H A X X X L H L H L H L H Y0 H H H L H H H H H H H Y1 H H H H L H H H H H H Y2 H H H H H L H H H H H Y3 H H H H H H L H H H H Y4 H H H H H H H L H H H Y5 H H H H H H H H L H H Y6 H H H H H H H H H L H Y7 H H H H H H H H H H L X : Don't Care 2/12 74LCX138 Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays Table 4: Absolute Maximum Ratings Symbol VCC VI VO VO IIK IOK IO ICC IGND Tstg TL Supply Voltage DC Input Voltage DC Output Voltage (VCC = 0V) DC Output Voltage (High or Low State) (note 1) DC Input Diode Current DC Output Diode Current (note 2) DC Output Current DC Supply Current per Supply Pin DC Ground Current per Supply Pin Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 50 - 50 50 100 100 -65 to +150 300 Unit V V V V mA mA mA mA mA C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) IO absolute maximum rating must be observed 2) VO < GND 3/12 74LCX138 Table 5: Recommended Operating Conditions Symbol VCC VI VO VO IOH, IOL IOH, IOL Top dt/dv Supply Voltage (note 1) Input Voltage Output Voltage (VCC = 0V) Output Voltage (High or Low State) High or Low Level Output Current (VCC = 3.0 to 3.6V) High or Low Level Output Current (VCC = 2.7V) Operating Temperature Input Rise and Fall Time (note 2) Parameter Value 2.0 to 3.6 0 to 5.5 0 to 5.5 0 to VCC 24 12 -55 to 125 0 to 10 Unit V V V V mA mA C ns/V 1) Truth Table guaranteed: 1.5V to 3.6V 2) VIN from 0.8V to 2V at VCC = 3.0V Table 6: DC Specifications Test Condition Symbol Parameter VCC (V) -40 to 85 C Min. 2.0 2.7 to 3.6 0.8 2.7 to 3.6 2.7 3.0 VOL Low Level Output Voltage 2.7 to 3.6 2.7 3.0 II Ioff ICC ICC Input Leakage Current Power Off Leakage Current Quiescent Supply Current ICC incr. per Input 2.7 to 3.6 0 2.7 to 3.6 IO=-100 A IO=-12 mA IO=-18 mA IO=-24 mA IO=100 A IO=12 mA IO=16 mA IO=24 mA VI = 0 to 5.5V VI or VO = 5.5V VI = VCC or GND VCC-0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 5 10 10 10 500 VCC-0.2 2.2 2.4 2.2 0.2 0.4 0.4 0.55 5 10 10 10 500 A A A A V V 0.8 V Max. Value -55 to 125 C Min. 2.0 Max. V Unit VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage VI or VO= 3.6 to 5.5V VIH = VCC - 0.6V 2.7 to 3.6 Table 7: Dynamic Switching Characteristics Test Condition Symbol Parameter VCC (V) 3.3 CL = 50pF VIL = 0V, VIH = 3.3V Value TA = 25 C Min. Typ. 0.8 -0.8 Max. V Unit VOLP VOLV Dynamic Low Level Quiet Output (note 1) 1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state. 4/12 74LCX138 Table 8: AC Electrical Characteristics Test Condition Symbol Parameter VCC (V) 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 3.0 to 3.6 CL (pF) 50 50 50 50 RL () 500 500 500 500 ts = tr (ns) 2.5 2.5 2.5 2.5 -40 to 85 C Min. 1.5 1.5 1.5 Max. 7.9 6.7 6.4 5.8 7.4 6.5 1.0 Value -55 to 125 C Min. 1.5 1.5 1.5 Max. 7.9 6.7 6.4 5.8 7.4 6.5 1.0 ns ns ns ns Unit tPLH tPHL tPLH tPHL tPLH tPHL tOSLH tOSHL Propagation Delay Time A, B, C to Y Propagation Delay Time G1 to Y Propagation Delay Time G2 to Y Output To Output Skew Time (note1, 2) 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|) 2) Parameter guaranteed by design Table 9: Capacitive Characteristics Test Condition Symbol Parameter VCC (V) 3.3 3.3 VIN = 0 to VCC fIN = 10MHz VIN = 0 or VCC Value TA = 25 C Min. Typ. 6 42 Max. pF pF Unit CIN CPD Input Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC Figure 4: Test Circuit CL = 50pF or equivalent (includes jig and probe capacitance) RL = 500 or equivalent RT = ZOUT of pulse generator (typically 50) 5/12 74LCX138 Figure 5: Waveform - Propagation Delays For Inverting Outputs (f=1MHz; 50% duty cycle) Figure 6: Waveform - Propagation Delays For Non-inverting Outputs (f=1MHz; 50% duty cycle) 6/12 74LCX138 SO-16 MECHANICAL DATA DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.25 1.64 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.010 0.063 0.018 0.010 0016020D 7/12 74LCX138 TSSOP16 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8 0.75 0 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0079 0.201 0.260 0.176 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 8/12 74LCX138 Tape & Reel SO-16 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.45 10.3 2.1 3.9 7.9 12.8 20.2 60 22.4 6.65 10.5 2.3 4.1 8.1 0.254 0.406 0.082 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.262 0.414 0.090 0.161 0.319 MIN. TYP. MAX. 12.992 0.519 inch 9/12 74LCX138 Tape & Reel TSSOP16 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.7 5.3 1.6 3.9 7.9 12.8 20.2 60 22.4 6.9 5.5 1.8 4.1 8.1 0.264 0.209 0.063 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.272 0.217 0.071 0.161 0.319 MIN. TYP. MAX. 12.992 0.519 inch 10/12 74LCX138 Table 10: Revision History Date 15-Sep-2004 Revision 4 Description of Changes Ordering Codes Revision - pag. 1. 11/12 74LCX138 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 12/12 |
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