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A8439
Photoflash Capacitor Charger with IGBT Driver and Refresh
Features and Benefits
Power with 1 Li+ or 2 Alkaline/NiMH/NiCAD batteries Adjustable output voltage Auto-refresh >75% efficiency Eight-level, digitally-programmable current limit Charge complete indication Integrated IGBT driver with trigger No primary-side Schottky diode needed Low-profile package (0.75 mm nominal height)
Description
The A8439 is a highly integrated IC that charges photoflash capacitors for digital and film cameras. An integrated MOSFET switch drives the transformer in a flyback topology. It also features an integrated IGBT driver that facilitates the flash discharge function and saves board space. The CHARGE pin enables the A8439 and starts the charging of the output capacitor. When the designated output voltage is reached, the A8439 stops the charging until the CHARGE pin is toggled again, or when output voltage falls below 90% of the designated value. Pulling the CHARGE pin low stops the charging. The DONE pin is an open-drain indicator of when the designated output voltage is reached. The peak current limit can be adjusted to eight different levels between 270 mA and 1.4 A, by clocking the CHARGE pin. This allows the user to operate the flash even at low battery voltages. The A8439 can be used with two Alkaline/NiMH/NiCAD or one single-cell Li+ battery connected to the transformer primary. Connect the VIN pin to a 3.0 to 5.5 V supply, which can be either the system rail or the Li+ battery, if used. The A8439 is available in a very low profile (0.75 mm) 10terminal 3x3 mm MLP/TDFN package, making it ideal for space-constrained applications. It is lead (Pb) free, with 100% matte-tin leadframe plating. Applications include the following: Digital camera flash Film camera flash Cell phone flash Emergency strobe light
Package: 10 pin TDFN/MLP (suffix EJ)
Approximate Scale
Typical Applications
VBIAS 3.0 to 5.5 V Two Alkaline/NiMH/NiCAD or one Li+ battery or 1.5 to 5.5 V D1 VBATT T1 +
C1 0.1 F C2 4.7 F
VOUT
One Li+ battery VBATT or 3.0 to 5.5 V
T1
D1
VOUT R1 R2
R4
R1 R2
100 k
COUT
R4
C1 0.1 F
C2 4.7 F
COUT
100 k
VIN CHARGE
SW FB
VIN CHARGE
SW FB
R5
10 k
A8439
DONE TRIGGER IGBTDRV GND
R3
R5
C3
10 k
A8439
DONE TRIGGER IGBTDRV GND
R3
C3
R6
To IGBT Gate
10 k
R6
To IGBT Gate
10 k
Figure 1. Typical circuit with separate power supply to transformer A8439-DS, Rev. 5
Figure 2. Typical circuit with single power supply
A8439
Photoflash Capacitor Charger with IGBT Driver and Refresh
Selection Guide
10-pin TDFN/MLP *Contact Allegro for additional packing options
Part Number A8439EEJTR-T
Package
Packing*
1500 pieces/ 7-in. reel
Absolute Maximum Ratings
Characteristic SW pin IGBTDRV pin FB pin All other pins Operating Ambient Temperature Maximum Junction Temperature Storage Temperature Symbol VSW VIGBTDRV VFB VX TA TJ(max) Tstg Range E Notes Rating -0.3 to 40 -0.3 to VIN + 0.3 -0.3 to VIN -0.3 to 7 -40 to 85 150 -55 to 150 Units V V V V C C C
Package Thermal Characteristics
Characteristic Package Thermal Resistance Symbol RJA Test Conditions* 4layer PCB, based on JEDEC standard Rating Units 45 C/W
*Additional information is available on the Allegro website.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8439
Photoflash Capacitor Charger with IGBT Driver and Refresh
Functional Block Diagram
SW VIN DCM Comparator Control Logic CMP3 1.2 V
18 s
HL Triggered Timer CMP2
S SET Q R
CLR Q
Q
40 V DMOS
ILIM Comparator CHARGE ILIM Decoder Adjustable Reference Enable FB
CMP1 1.2 V DONE VIN TRIGGER
IGBTDRV
GND
Device Pin-out Diagram
Terminal List Table
Number 1,10 Name NC VIN GND CHARGE SW Function No connection Power supply input Device ground Charging enable and ISWLIM code input; set to low to power-off the A8439 Switch, internally connected to the DMOS power FET drain Open drain, when pulled low by internal MOSFET, indicates that charging target level has been reached Output voltage feedback
NC IGBTDRV VIN GND CHARGE
1 2 3 4 5
10 NC 9 8 7 6 FB DONE TRIGGER SW
2 3 4 5 6 7 8 9
IGBTDRV IGBT driver gate drive output
TRIGGER Strobe signal input DONE FB
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8439
Photoflash Capacitor Charger with IGBT Driver and Refresh
ELECTRICAL CHARACTERISTICS Typical values at TA = 25C and VIN = 3.3 V (unless otherwise noted)
Characteristics Supply Voltage* Supply Current Symbol VIN IIN ISWLIM1 ISWLIM2 ISWLIM3 ISWLIM4 ISWLIM5 ISWLIM6 ISWLIM7 ISWLIM8 RDS(On)SW ISWLKG tOFF(Max) tON(Max) ICHARGE VCHARGE(H) VCHARGE(L) tILIM1(H) tILIM(H) tILIM(L) tILIM(SU) IDONELKG VDONE(L) VFB IFB VFBR VUVLO VUVLOHYS 32 A into pin DONE VFB = 1.205 V VIN rising Charging Charging done / Refresh monitoring Shutdown (VCHARGE = 0 V, VTRIGGER = 0 V) Test Conditions Min. 3 - - - 1.2 - - - - - - - - - - - - 2 - 20 0.2 0.2 - - - 1.187 - - 2.55 - - - - 2 - - - - - Typ. - 1.5 300 0.01 1.4 1.2 1.0 0.86 0.7 0.55 0.4 0.27 0.27 - 18 18 - - - - - - 54 - - Max. Units 5.5 - 600 1 1.6 - - - - - - - - 1 - - 1 - 0.8 - - - - 1 100 V mA A A A A A A A A A A A s s A V V s s s s A mV V nA V V mV A V V ns ns ns ns
Primary Side Current Limit (ILIM clock input at CHARGE pin)
SW On Resistance SW Leakage Current* SW Maximum Off-Time SW Maximum On-Time CHARGE Input Current CHARGE Input Voltage* ILIM Clock High Time at CHARGE Pin ILIM Clock Low Time at CHARGE Pin Total ILIM Setup Time Output Leakage Current* DONE Output Low Voltage* DONE FB Voltage Threshold* FB Input Current Auto-Refresh Threshold Level UVLO Enable Threshold UVLO Hysteresis IGBT Driver IGBTDRV On Resistance to VIN IGBTDRV On Resistance to GND TRIGGER Input Current
VIN = 3.3 V, ID = 800 mA, TA = 25C VSW = 35 V
VCHARGE = VIN
Initial pulse Subsequent pulses
1.205 1.223 -120 - 1.07 - 2.65 2.75 150 - 5 6 - - - 30 30 70 70 - - 1 - 0.8 - - - -
RDS(On)I-V VIN = 3.3 V, VIGBTDRV = 1.5 V, VTRIGGER = VIN RDS(On)I-G VIN = 3.3 V, VIGBTDRV = 1.5 V, VTRIGGER = 0 V ITRIGGER VTRIGGER = VIN VTRIGGER(H) TRIGGER Input Voltage* VTRIGGER(L) Propagation Delay, Rising tDr Rgate=12 , CLOAD = 6500 pF, VIN = 3.3 V Propagation Delay, Falling tDf Rgate=12 , CLOAD = 6500 pF, VIN = 3.3 V Output Rise Time tr Rgate=12 , CLOAD = 6500 pF, VIN = 3.3 V Output Fall Time tf Rgate=12 , CLOAD = 6500 pF, VIN = 3.3 V *Guaranteed by design and characterization over operating temperature range, -40C to 85C.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8439
Photoflash Capacitor Charger with IGBT Driver and Refresh
Operation Timing Diagram
VIN CHARGE SW
VUVLO
Target VOUT
VOUT DONE TRIGGER IGBTDRV A B C D E F
Explanation of Events:
A. B. C. D. E. F. Start charging by pulling CHARGE to high, provided that VIN is above the VUVLO level. Charging stops when VOUT reaches the target voltage. goes low, to signal the DONE completion of the charging process. Start a new charging process with a low-to-high transition at the CHARGE pin. Pull CHARGE to low, to put the controller in low-power standby mode. Charging does not start, because VIN is below VUVLO level when CHARGE goes high. After VIN goes above VUVLO, another low-to-high transition at the CHARGE pin is required to start charging.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8439
Photoflash Capacitor Charger with IGBT Driver and Refresh
Tests performed using application circuit shown in figure 8 with ISWLIM set to 1.4A (Single rising edge on CHARGE pin), unless otherwise noted
Performance Characteristics
Charging Waveforms
VOUT
Symbol C1 C4 t Conditions
Parameter VOUT IBATT(Avg) time Parameter VBATT VBIAS COUT
Units/Division 50 V 200 mA 1s Value 2.5 V 3.3 V 100 F
IBATT C4
C1
t
VOUT
Symbol C1 C4 t Conditions
Parameter VOUT IBATT(Avg) time Parameter VBATT VBIAS COUT
Units/Division 50 V 200 mA 1s Value 3.6 V 3.3 V 100 F
IBATT C4
C1
t
VOUT
Symbol C1 C4 t Conditions
Parameter VOUT IBATT(Avg) time Parameter VBATT VBIAS COUT
Units/Division 50 V 200 mA 1s Value 4.2 V 3.3 V 100 F
IBATT C4
C1
t
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8439
Photoflash Capacitor Charger with IGBT Driver and Refresh
Performance Characteristics, continued
Tests performed using application circuit shown in figure 8 with ISWLIM set to 1.4A (Single rising edge on CHARGE pin), unless otherwise noted
Charge Time
VBIAS = 3.3 V, COUT = 100 F Connect VBATT to a separate power supply
88 77 90 80
Efficiency
VBATT = VBIAS , TA = 25C
Charge Time (s)
Charge Time (s)
66 55 44 33 22 2.0 2
Efficiency (%)
70 60 50 40 100
VBATT = 5.0 V VBATT = 4.2 V VBATT = 3.0 V
VV ==320 VV OUT OUT 320 VV ==300 VV OUT OUT 300
2.5 2.5
33.0 3.53.5 4 4.0 4.5 4.5 5 VBATT (V) VBATT (V)
5.0 5.5
5.5 6
6.0
150
200 VOUT (V)
250
300
350
Typical Switching Waveform
VBATT C3 VOUT
Symbol C1 C2 C3 C4 t Conditions
Parameter VOUT VSW VBATT IPrimary time Parameter VOUT VBATT
Units/Division 50 V 10 V 5V 500 mA 2 s Value 300 V VIN
C2
VSW
IPrimary
C4 C1
t
IGBT Drive Timing Definition
TRIGGER
50%
50%
t Dr
tr
90%
t Df
tf
90% 10%
IGBTDRV
10%
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8439
Photoflash Capacitor Charger with IGBT Driver and Refresh
Performance Characteristics, continued
IGBT Drive waveforms are measured with R-C load (12 , 6800 pF)
IGBT Drive Performance Rising Signal
tr VIGBTDRV
Symbol C2 C3 t Conditions
Parameter VIGBTDRV VTRIGGER time Parameter tDr tr CLOAD Rgate
Units/Division 1V 1V 50 ns Value 22.881 ns 63.125 ns 6800 pF 12
C2 VTRIGGER
C3
t
Falling Signal
tf
Symbol C2 C3 t Conditions
Parameter VIGBTDRV VTRIGGER time Parameter tDf tf CLOAD Rgate
Units/Division 1V 1V 50 ns Value 27.427 ns 65.529 ns 6800 pF 12
C2
VIGBTDRV
C3
VTRIGGER t
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8439
Photoflash Capacitor Charger with IGBT Driver and Refresh
Functional Description
Overview The A8439 is a photoflash capacitor charger control IC with adjustable input current limiting and automatic refresh. It also integrates an IGBT driver for strobe operation of the flash tube, dramatically saving board space in comparison to discrete solutions for strobe flash operation. The control logic is shown in the functional block diagram. The charging operation of the A8439 is started by a low-to-high signal on the CHARGE pin, provided that VIN is above VUVLO level. If CHARGE is already high before VIN reaches VUVLO , another low-to-high transition on the CHARGE pin is required to start the charging. The primary peak current is set by input clock signals from the CHARGE pin. When a charging cycle is initiated, the transformer primary side current, IPrimary, ramps up linearly at a rate determined by the combined effect of the battery voltage, VBATT , and the primary side inductance, LPrimary. When IPrimary reaches the current limit, ISWLIM , the internal MOSFET is turned off immediately, allowing the energy to be pushed into the photoflash capacitor, COUT, from the secondary winding. The secondary side current drops linearly as COUT charges. The recharging cycle starts again, either after the transformer flux is reset, or after a predetermined time period, tOFF(Max) (18 s), whichever occurs first. The output voltage, VOUT, is sensed by a resistor string, R1, R2 , and R3 (see application circuit diagrams), connected between the positive terminal of the output capacitor and ground. This resistor string forms a voltage divider that feeds back to the FB pin. The resistors must be sized to achieve a desired output voltage level based on a typical value of 1.205 V at the FB pin. As soon as VOUT reaches the desired value, the charging process is terminated. The A8439 automatically starts a new charging cycle when the internal voltage sensing circuit detects a 10 % drop in the output voltage. Toggling the CHARGE pin can also start a refresh operation.
Auto-Refresh The A8439 features auto-refresh when the feedback resistor network is connected at the output. Auto-refresh initiates when the output voltage drops to 90 % of the set stop voltage of the resistor network. The operation is shown in figure 3. Input Current Limiting The peak current limit can be adjusted to eight different levels, from 270 mA to 1.4 A, by clocking the CHARGE pin. An internal digital circuit decodes the input clock signals to a counter, which sets the charging time. This flexible scheme allows the user to operate the flash circuit according to different battery input voltages. The battery life can be effectively extended by setting a lower current limit at low battery voltages. Figure 4 shows the ILIM clock timing scheme protocol. The total ILIM setup time, tILIM(SU) , denotes the time needed for the
Figure 3. Auto-refresh waveform of A8439.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8439
Photoflash Capacitor Charger with IGBT Driver and Refresh
decoder circuit to receive ILIM inputs and set ISWLIM , and has a minimum duration of 54 s. Figure 5 shows the timing definition of the primary current limiting circuit. At the end of the setup period, tILIM(SU) , primary current starts to ramp up to the set ISWIM. The ISWLIM setting remains in effect as long as the CHARGE pin is high. To reset the ILIM counter, pull the CHARGE pin low before clocking in the new setting. After the first start-up or an ILIM counter reset, each new current limit can be set by sending a burst of pulses to the CHARGE pin. The first rising edge starts the ILIM counter, and up to 8 rising edges will be counted to set the ISWLIM level. The first pulse width, tILIM1(H), must be at least 20 s long. Subsequent pulses (up to 7 more) can be as short as 0.2 s. The last low-to-high edge must arrive within 54 s from the first edge. The CHARGE pin will stay high afterwards. The four panels of figure 6 show examples of the pulse streams and the resulting current levels.
t ILIM(L)
Clock input at CHARGE pin
(A) 1.4 A
(B) 1.2 A
0.2 s
t ILIM(H)
0.2 s
t ILIM1(H) = min. first pulse width t ILIM(SU) = maximum
ILIM setup time First rising edge 0 s 20 s Subsequent rising edges (0 to 7) 54 s Switching starts
(C) 1.0 A
Figure 4. ILIM Clock Timing Definition
Start ILIM counter
Reset ILIM counter
(D) 0.86 A
CHARGE
Four rising edges within tILIM(SU)
ISWLIM4 = 0.86 A
I SW
Switching starts Switching stops
0 s
20 s
54 s
Figure 5. Current Limit Programming Example (ISWLIM4 selected).
Figure 6. ILIM programming waveforms for ISWLIM = 1.4 A, 1.2 A, 1.0 A, and 0.86 A.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8439
Photoflash Capacitor Charger with IGBT Driver and Refresh
Figure 7 shows the last charging cycle, when the CHARGE pin is forced low before charging has been completed. The A8439 implements an adaptive off-time, tOFF , control. After the switch is turned off, a sensing circuit tracks the flyback
voltage at the SW node. As soon as this voltage swings below 1.2 V, the switch is turned on again for the next charging cycle. However, when the photoflash capacitor charger circuit starts up at low output voltage, a timeout may be triggered to limit the maximum switch off-time to 20 s.
Figure 7. Last charging cycle, when the CHARGE pin is forced low before charging is complete.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8439
Photoflash Capacitor Charger with IGBT Driver and Refresh
Applications Information
Transformer Design
Turns Ratio. The minimum transformer turns ratio, N,
primary inductance, LPrimary (H), use the following formula:
(Secondary:Primary) should be chosen based on the following formula:
LPrimary
300 x 10-9 x VOUT N x ISWLIM
.
(2)
VOUT + VD_Drop N 40 - VBATT
(1)
where: VOUT (V) is the required output voltage level, VD_Drop (V) is the forward voltage drop of the output diode(s), VBATT (V) is the transformer battery supply, and 40 (V) is the rated voltage for the internal MOSFET switch, representing the maximum allowable reflected voltage from the output to the SW pin. For example, if VBATT is 3.5 V and VD_Drop is 1.7 V (which could be the case when two high voltage diodes were in series), and the desired VOUT is 320 V, then the turns ratio should be at least 8.9. In a worst case, when VBATT is highest and VD_Drop and VOUT are at their maximum tolerance limit, N will be higher. Taking VBATT = 5.5 V, VD_Drop = 2 V, and VOUT = 320 V x 102 % = 326.4 V as the worst case condition, N can be determined to be 9.5. In practice, always choose a turns ratio that is higher than the calculated value to give some safety margin. In the worst case example, a minimum turns ratio of N = 10 is recommended.
Primary Inductance. As a loose guideline when choosing the
Ideally, the charging time is not affected by transformer primary inductance. In practice, however, it is recommended that a primary inductance be chosen between 10 H and 20 H. When LPrimary is lower than 10 H, the converter operates at higher frequency, which increases switching loss proportionally. This leads to lower efficiency and longer charging time. When LPrimary is greater than 20 H, the rating of the transformer must be dramatically increased to handle the required power density, and the series resistances are usually higher. A design that is optimized to achieve a small footprint solution would have an LPrimary of 12 to 14 H, with minimized leakage inductance and secondary capacitance, and minimized primary and secondary series resistance. Please refer to the table Recommended Components for more information.
Leakage Inductance and Secondary Capacitance. The trans-
former design should minimize the leakage inductance to ensure the turn-off voltage spike at the SW node does not exceed the 40 V limit. An achievable minimum leakage inductance for this application, however, is usually compromised by an increase in parasitic capacitance. Furthermore, the transformer secondary capacitance should be minimized. Any secondary capacitance is multiplied by N 2 when reflected to the primary, leading to high initial current swings when the switch turns on, and to reduced efficiency.
VBIAS 3.0 to 5.5 V
Two Alkaline/NiMH/NiCAD or one Li + VBATT 1.5 to 5.5 V T1 D1
1:10.2
Symbol
VOUT R1 R2
Rating
0.1 F, X5R or X7R, 10 V 4.7 F, X5R or X7R, 10 V 1 nF, X5R or X7R, 10 V Fairchild Semiconductor BAV23S (dual diode connected in series) Tokyo Coil Engineering T-16-024A, LPrimary = 12 H, N = 10.2 1206 resistors, 1 % 0603 resistor, 1 % Pull-up resistor Pull-down resistors
C1 C2 C3 D1 T1
+
R4
100 k
C1 0.1 F
C2 4.7 F
4.99 M
COUT
100 F 330 V
VIN CHARGE
SW FB
4.99 M
R5
10 k
A8439
DONE TRIGGER IGBTDRV GND
39 k
R3
C3 1 nF
R1, R2 R3 R4 R5, R6
R6
To IGBT Gate
10 k
Figure 8. Typical circuit for photoflash capacitor charging application.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8439
Adjusting Output Voltage
Photoflash Capacitor Charger with IGBT Driver and Refresh
The peak current of the rectifying diode, ID_Peak, is calculated as:
The A8439 senses output voltage continuously in order to provide auto-refresh function. The output voltage can be adjusted by selecting proper values of the voltage divider resistors. Use the following equation to calculate values for Rx ():
ID_ Peak = IPrimary_Peak / N .
Input Capacitor Selection
(5)
R1 + R2 VOUT = -1 . R3 VFB
(3)
R1 and R2 together need to have a breakdown voltage of at least 300 V. A typical 1206 surface mount resistor has a 150 V breakdown voltage rating. It is recommended that R1 and R2 have similar values to ensure an even voltage stress between them. Recommended values are: R1 = R2 = 4.99 M (1206) R3 = 39.4 k (0603) which together yield a stop voltage of 305 V.
Output Diode Selection
Ceramic capacitors with X5R or X7R dielectrics are recommended for the input capacitor, C2. It should be rated at least 4.7 F / 6.3 V to decouple the battery input, VBATT , at the primary of the transformer. When using a separate bias, VBIAS , for the A8439 VIN supply, connect at least a 0.1 F / 6.3 V bypass capacitor to the VIN pin. Layout Guidelines Key to a good layout for the photoflash capacitor charger circuit is to keep the parasitics minimized on the power switch loop (transformer primary side) and the rectifier loop (secondary side). Use short, thick traces for connections to the transformer primary and SW pin. Output voltage sensing circuit elements must be kept away from switching nodes such as SW pin. It is important that the DONE signal trace and other signal traces be routed away from the transformer and other switching traces, in order to minimize noise pickup. In addition, high voltage isolation rules must be followed carefully to avoid breakdown failure of the circuit board.
Choose the rectifying diode(s), D1, to have small parasitic capacitance (short reverse recovery time) while satisfying the reverse voltage and forward current requirements. The peak reverse voltage of the diode, VD_Peak , occurs when the internal MOSFET switch is closed, and the primary-side current starts to ramp-up. It can be calculated as:
. VD_ Peak = VOUT + N x V BATT
(4)
Recommended Components Table Component Rating 0.1 F, 10%, 16 V X7R ceramic C1, Input Capacitor capacitor (0603) 4.7 F, 10%, 10 V, X5R ceramic C2, Input Capacitor capacitor (0805) COUT, Photoflash Capacitor 330 V 100 F (or 19 to 180 F) D1, Output Diode R1, R2, FB Resistors R3, FB Resistor T1, Transformer 2 x 250 V, 225 mA, 5 pF 4.99 M, 1/4 W 1% (1206) 39.0 k 1/10 W 1% (0603) 1:10.2, LPrimary = 14.5 H 1:10.2, LPrimary = 12 H 1:10, LPrimary = 10.8 H
Part Number GRM188R71C104KA01D LMK212BJ475KG EPH-331ELL101B131S BAV23S 9C12063A4994FKHFT 9C06031A3902FKHFT LDT565630T-002 T-16-024A ST-532517A Murata
Source
Taiyo Yuden Chemi-Con Philips Semiconductor, Fairchild Semiconductor Yageo Yageo TDK Tokyo Coil Engineering Asatech
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A8439
Photoflash Capacitor Charger with IGBT Driver and Refresh
Package EJ, 10-Contact TDFN/MLP
3.15 .124 2.85 .112 Preliminary dimensions, for reference only (reference JEDEC MO-229 WEED) Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (reference dimensions only, terminal #1 identifier appearance at supplier discretion) C Reference pad layout (reference IPC7351 SON50P300X300X80-11WEED2M); adjust as necessary to meet application process requirements 10X 0.08 [.003] C 10X 0.30 .012 0.18 .007 0.10 [.004] M C A B 0.05 [.002] M C 0.50 .020 0.30 .012 NOM 8X 0.20 .008 MIN C 0.50 .020 NOM 1 R0.20 .008 REF 1.65 .065 NOM 3.10 .122 NOM 2 10
A B
3.15 .124 2.85 .112 A 1 2 C
SEATING PLANE 0.80 .031 0.70 .028 0.20 .008 REF 0.05 .002 0.00 .000
0.85 .033 NOM
B
1.65 .065 NOM
0.50 .020 0.30 .012
10 8X 0.20 .008 MIN 2.39 .094 NOM
2.39 .094 NOM
The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detailed specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright(c)2005, 2006 AllegroMicrosystems, Inc.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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