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| TM Table 1: CS3810 32 QAM Demodulator Interface Signal Descriptions Name RESTART I/O Input Width 1 Description Synchronous reset signal, active HIGH. The BLL restart the acquisition process after it is activated. The CLL returns to idle state after RESTART and re-starts acquisition until the BLL lock is achieved. INPUT DATA ZIFMT Input 1 Input sample format, static programming signal 0: two's complement 1: offset binary Input sample A from DAC, 2x symbol rate (74MHz), format is determined by ZIFMT Input sample B from DAC, 2x symbol rate (74MHz), format is determined by ZIFMT ZA ZB AGC SETTING AGCREF BLL SETTINGS VCORNG Input Input 10 10 Input 8 AGC threshold reference, static programming signal Input 1 VCO frequency range selection, static programming signal, specifying the corresponding Df/f0 of the VCO when the 12-bit control signal VCOV changes from the middle to the maximal or minimal value 0: 1/8192 1: 1/4092 The actual Df/f0 of the VCO may not be necessarily accurate as the specified and the BLL can still be functioning. It only affects the BLL acquisition range and speed. Costas low pass filter H(f) gain factor selection, static programming signal 0: 1/32 1: 1/16 Frequency error low pass filter gain factor selection before the BLL lock is declared, static programming signal 00: 1/2048 01: 1/1024 10: 1/512 11: 1/256 Frequency error low pass filter gain factor selection, after the BLL lock is declared, static programming signal 00: 1/16384 01: 1/8192 10: 1/4096 11: 1/2048 BLL Lock threshold selection, relative to the lock indicator value for ideal signal, static programming signal 0: 1/2 1: 3/4 BLL lock detection window size selection, in terms of number of 32-QAM symbols, static programming signal 0: 16384 1: 32768 HBWBLL Input 1 FFKBLL Input 2 LFFKBLL Input 2 LCKTHBLL Input 1 LCKWINBLL Input 1 3 CS3810 Name CLL SETTINGS INIPCLL 32 QAM Demodulator Table 1: CS3810 32 QAM Demodulator Interface Signal Descriptions I/O Width Description Input 1 CLL initial period selection, in terms of 32-QAM symbols, static programming signal, 0: 16384 1: 32768 When the BLL lock is declared, the CLL switches from idle state to initial state in which the equalizer is put into CMA mode. The CLL acquisition starts after the initial period. Use or not use AFC for frequency offset estimate, static programming signal 0: do not use AFC 1: use AFC When AFC is not in use, the CLL uses a scan counter mechanism to estimate the frequency offset. Every time when the pull-in fails the counter is increased by one to give a new frequency offset value until the lock is achieved. Number of AFC computations for averaging in AFC period 0: 16 1: 64 Simulation shows that in noisy conditions selection of 64 gives more reliable frequency offset estimate CLL pull-in (acquisition) mode bandwidth select 0: 0.0015(55KHz) 1: 0.003(110KHz) The bandwidth is approximated based on the assumption of damping factor of 0.71 CLL decision-direct (tracking) mode bandwidth select 0: 0.01(370KHz) 1: 0.02(740KHz) The bandwidth is approximated based on the assumption of damping factor of 0.71 Equalizer m select for CMA mode 00: 1/1024 01: 1/512 10: 1/256 11: 1/128 Equalizer m select for DD LMS mode 00: 1/8192 01: 1/4096 10: 1/2048 11: 1/1024 AFCCLL Input 1 NAFCCLL Input 1 PILBWCLL Input 1 DDLBWCLL Input 1 MUCMAEQ Input 2 MUDDEQ Input 2 OUTPUT DATA RXSYNC RXDATA Output Output 1 8 Output ready flag. Signals that valid output data is present at the RXDATA port Received output data port 4 TM Table 1: CS3810 32 QAM Demodulator Interface Signal Descriptions Name I/O Width Description ERROR CORRECTION STATISTICS TCMERR RSERR_U RSERR_L AGC CONTROL AGCP VCO CONTROL VCOV Output 12 VCO control voltage, 12-bit offset-binary format, normalized according to the VCO frequency range such that the maximal value corresponds to the lowest frequency and zero corresponds to the highest frequency, updated every four symbols (9.25 MHz, 8 clock cycles) VCO control voltage strobe, asserted for 4 cycles in every 8 clock cycles to indicate the update of VCOV Output 1 AGC width-modulated pulse with period of 256 symbols. The pulse width is proportional to the input signal level. Output Output Output 16 16 16 Reports the number of estimated errors in the decoded IQ datastream Reports the number of errors corrected by the Reed Solomon Decoder (upper 16 bits) Reports the number of errors corrected by the Reed Solomon Decoder (lower 16 bits) VCSTRB Output 1 ERROR CORRECTION CONTROL RSERRPRD UPTCM BYPASS LOCK STATUS AGCOK LCKBLL LCKCLL STATCLL Output Output Output Output 1 1 1 3 AGC OK indicator, asserted when the average peak sample level is within +/-15% of the ideal level BLL lock flag, asserted when lock is declared or retained, updated once every BLL lock detection window CLL lock flag, asserted when lock is declared or retained, updated for every output symbol (two clock cycles) CLL status, updated for every output symbol (two clock cycles) 000: idle (equalizer in initial mode, phase error set to 0) 001: initial (equalizer in CMA, phase error set to 0) 010: AFC (equalizer in CMA, estimate frequency offset) 011: DFS (equalizer in CMA, scan counter increases) 100: 4GC pull-in (equalizer in CMA, CLL 4GC pull-in) 110: DD pull-in (equalizer in CMA, CLL DD pull-in) 111: Lock (equalizer in DD, CLL DD tracking) When Asserted signifies the output fifo has overflowed and data has been dropped When asserted signifies the TCM decoder has achieved lock When asserted signifies that block synchronization has been achieved Input Input Input 2 8 1 Static signal-sets the duration over which RS statistics are gathered Static signal used to control operation of TCM decoder Static signal, when asserted the TCM decoder is bypassed FIFOERROR LCKTCM LCKUW Output Output Output 1 1 1 5 CS3810 Name TEST DATA BLLSTRB 32 QAM Demodulator Table 1: CS3810 32 QAM Demodulator Interface Signal Descriptions I/O Width Description Output 1 BLL output sample strobe, one cycle pulse every two clock cycles, indicating the peak or transition samples after BLL lock is achieved 1: peak sample 0: transition sample BLL output sample I, two's complement format BLL output sample Q, two's complement format TCM decoder test input TCM decoder test input Active strobe signal used to sample MAPI and MAPQ Static signal, when asserted MAPI and MAPQ are sampled otherwise the demodulated data is decoded as normal BLLIQ BLLQI MAPI MAPQ MapStrb MapTest Output Output Input Input Input Input 11 11 4 4 1 1 MICROPROCESSOR INTERFACE DATA ADDR ALE CSB WRB Tri-state Input Input Input Input 16 5 1 1 1 16-bit data bus 5-bit address bus Address latch enable Chip select, level sensitive and active LOW Write/Read control signal 0: Write 1: Read Output enable, level sensitive and active LOW. The demodulator drives the data bus only when both CSB and OEB are active OEB Input 1 6 TM DEMODULATOR OVERVIEW The input to the demodulator may be fed directly from an A/ D converter. It samples the received spectrum at double the symbol rate. REED SOLOMON DECODING Prior to RS decoding the block boundaries are recovered. The sync detection circuitry searches for a unique word similar to the scheme employed by Intelsat IESS-308. Once locked the sync detection module also repacks the TCM output stream into 8 bit Reed Solomon symbols. The delineated blocks are de-interleaved and Reed Solomon decoded. The corrected errors are reported and reflected on the RSERR_U and RSERR_L output ports during a statistics gathering period. AGC An AGC loop is implemented with an external gain control element in order to achieve the desired receiver dynamic range and maintain proper input level to the ADC. The AGC module determines the average power of the input signal and compares it to a programmed threshold. A pulse width modulated signal is output by the AGC module. The PWM stream is externally integrated and can be used as a AGC control voltage. DESCRAMBLING A self synchronizing descrambler utilizing a 220-1 pattern operates on the data stream thus de randomizing it to recover the original modulated input message. Data from the descrambler is written to a FIFO on the symbol rate clock and output on RXDATA on the rising edge of the RXUSRCLK. TIMING RECOVERY The received data stream then enters the symbol timing recovery loop, which consists of resampling circuitry and filtering, crosstalk removal, IQ imbalance adjustment and a Digital Phase Locked Loop (DPLL). A combined resampling / matched filter is used to enable transfer of the input data stream from the input data domain to the symbol rate domain. LOCK INDICATION A number of lock indicators are provided as status registers bits to enable the overall synchronisation status of the demodulator to be monitored. These are: * * * * Symbol timing recovery loop lock Carrier recovery loop lock TCM decoder synchronized Unique word sync detection lock CARRIER RECOVERY The recovered symbol rate data then enters the carrier recovery loop of the demodulator. This consists of a derotation module, removal of DC crosstalk, adjustment of any I/Q imbalance, equalization and the DPLL. As the constellation of the recovered symbol rate data can still be rotating at this stage it is necessary to de-rotate this prior to equalization. After de-rotation the symbol rate data is applied to an adaptive equaliser to remove transmission related distortions. TCM The recovered symbols are fed to the 64 state TCM decoder. The user can select the puncture rate, lock thresholds or even to bypass the TCM decoder. The TCM decoder provides BER estimates which may be read via the microprocessor interface. 7 CS3810 32 QAM Demodulator TIMING CHARACTERISTICS The programming signals are assumed to be static, i.e., they do not change during normal operation process. The microprocessor interface signals have been described in the CLK ZA ZB previous section. The timing diagrams of the other signals are provided below, with reference to the clock and output sample strobe signals. Figure 4: Input Data Timing CLK ZSTRB 512 cycles (256 symbols) AGCP AGCOK Figure 5: AGC Control Timing CLK BLLSTRB BLLIQ BLLQI Figure 6: Test Data Timing 8 TM PERFORMANCE Figure 7 demonstrates the over all error correction performance of the Concatenated correction system employed by the decoder (under AWGN conditions). BER Performance 10 1.00E+00 1.00E-01 1.00E-02 1.00E-03 Concatenated coded data Uncoded Data 10.25 10.5 10.75 11 BER 1.00E-04 1.00E-05 1.00E-06 1.00E-07 1.00E-08 Eb/No (dB) Figure 7: Error Correction Performance The demodulator. acquisition performance is presented in shown in Table 2 Table 2: Demodulator Acquisition Performance Metric Carrier acquisition range Symbol acquisition range Carrier tracking range Typical acquisition time 600KHz > 140ppm of baud rate 600KHz < 10 mS Performance 9 CS3810 32 QAM Demodulator PERFORMANCE AND DENSITY METRICS PROGRAMMABLE LOGIC CORES - DENSITY METRICS For ASIC prototyping or for projects requiring fast time-to-market of a programmable logic solution, Amphion programmable logic cores offer the silicon-aware performance tuning found in all Amphion products, combined with the rapid design times offered by today's leading programmable logic solutions. The following performance and density metrics has been obtained when the demodulator core is implemented as a stand-alone design in the device specified below. It should be noted that if the function is implemented on different FPGA devices, or combined with additional logic in larger devices, then additional constraints might need to be applied to achieve the similar metrics. Note that the metrics are provided for demodulation (Table 3) and channel decoding (Table 4) separately. Table 3: CS3810 FEC Decoder Programmable Logic Core - Altera DEVICE SILICON VENDOR AREA MEMORY REQUIREMENT 34 ESBs CRITICAL PATH (TXUSRXLK) 56.82 MHz (17.6 ns) CRITICAL PATH (CLK74M) 75.76 MHz (13.2 ns) APEX20KC-7 Altera 10044 LEs Table 4: CS3810 Symbol & Timing Recovery Programmable Logic Core - Altera DEVICE SILICON VENDOR AREA MEMORY REQUIREMENT 24 ESBs CRITICAL PATH (CLK74M) 74.63 MHz (13.4 ns) APEX20KC-7 Altera 11276 LEs 10 TM Typical ASIC or FPGA Design Flow (Conceptual) Data Formats Supplied by AMPHION System-Level "C" Code simulation Bit Accurate C Model Hardware RTL Development RTL Simulation RTL Simulation Models Logic Synthesis Testbench (VHDL & Verilog) Gate-level analysis (timing & functional) Netlists (Verilog, VHDL, EDIF, .bd) Physical Design FPGA Programming Files Figure 8: Design Data Formats Supplied by Amphion 11 CS3810 ABOUT AMPHION 32 QAM Demodulator CORPORATE HEADQUARTERS Amphion Semiconductor Ltd 50 Malone Road Belfast BT9 5BS Northern Ireland, UK Tel: Fax: +44 28 9050 4000 +44 28 9050 4001 TM Virtual Components for the Converging World WORLDWIDE SALES & MARKETING Amphion Semiconductor, Inc 2001 Gateway Place, Suite 130W San Jose, CA 95110 Tel: Fax: (408) 441 1248 (408) 441 1239 Amphion (formerly Integrated Silicon Systems) is the leading supplier of speech coding, video/ image processing and channel coding application specific silicon cores for system-on-a-chip (SoC) solutions in the broadband, wireless, and mulitmedia markets EUROPEAN SALES Amphion Semiconductor Ltd CBXII, West Wing 382-390 Midsummer Boulevard Central Milton Keynes MK9 2RG England, UK Tel: Fax: +44 1908 847109 +44 1908 847580 CANADA & EAST COAST US SALES Amphion Semiconductor, Inc Montreal Quebec Canada Tel: Fax: (450) 455 5544 (450) 455 5543 Web: www.amphion.com Email: info@amphion.com SALES AGENTS Voyageur Technical Sales Inc 1 Rue Holiday Tour Est, Suite 501 Point Claire, Quebec Canada H9R 5N3 Tel: Fax: (905) 672 0361 (905) 677 4986 Phoenix T echnologies Ltd 3 Gavish Street Kfar-Saba, 44424 Israel SPINNAKER SYSTEMS INC Hatchobori SF Bldg. 5F 3-12-8 Hatchobori, Chuo-ku Tokyo 104-0033 Japan T el: Fax: +972 9 7644 800 +972 9 7644 801 Tel: Fax: +81 3 3551 2275 +81 3 3351 2614 JASONTECH, INC Hansang Building, Suite 300 Bangyidong 181-3, Songpaku Seoul Korea 138-050 SPS-DA PTE LTD 21 Science Park Rd #03-19 The Aquarius Singapore Science P ark II Singapore 117628 T el: Fax: +65 774 9070 +65 774 9071 Tel: Fax: +82 2 420 6700 +82 2 420 8600 (c) 2002 Amphion Semiconductor Ltd. All rights reserved. Amphion, the Amphion logo,"Virtual Components for the Converging World", are trademarks of Amphion Semiconductor Ltd. All others are the property of their respective owners. 12 03/02 Publication #: DS3810 v1.0 |
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