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| Design Idea DI-53 DPA-SwitchTM 50 W DC-DC Dual Output Converter Application Telecom Device DPA425R Power Output 50 W Input Voltage 36-75 VDC Output Voltage 5 V & 3.3 V Topology Forward Sync. Rect. (R) Design Highlights * High efficiency: 90% at 36 VDC using synchronous rectification * Dual output with tight cross-regulation 4% from zero to full load on both outputs * Output overload, open loop and thermal protection * 300 kHz switching frequency to allow sufficient transformer reset time with sync rectification * 3.85 x 2.25 x 0.6 inch (~9.62 W/in3) recirculate the transformer leakage energy during normal operation, with Zener VR1 providing absolute clamping for transient conditions. Capacitor C21 charges the gate of Q2, the forward synchronous rectifier MOSFET of the 5 V output. Resistor R21 limits gate oscillation and R22 provides gate pull-down. Zener diode VR20 limits the Q2 gate voltage during conduction and also reverse charges C21 during the Q2 off time. The same drive technique is used for the forward synchronous rectifier MOSFET (Q4) of the 3.3 V output (with C22, R24, R25, and VR21). MOSFETs Q1 and Q3 are driven via resistors R23 and R26 from the transformer (T1) reset voltage and operate only when Q2 and Q4 are off. Diodes D20 and D21 provide a conduction path for the output inductor (L4) current when the transformer reset is complete. A winding on the coupled inductor L4, along with diode D4 and capacitor C9, provide the DPA-Switch bias voltage. L4 3.5 H 9,10 7,8 5 V, 6 A (8 A pk) 3.3 V, 6 A (8 A pk) Operation DPA-Switch greatly simplifies the design compared to a discrete implementation. This design uses a coupled output inductor and synchronous rectification to achieve excellent cross-regulation and high efficiency. Resistor R1 programs the under/over voltages and linearly reduces the maximum duty cycle with input voltage to prevent core saturation during load transients. Components D1, D2, C9 and L2 implement a resonant clamp circuit to catch and T1 8,9 R23 10 Q1 D20 + VIN 36-75 VDC L1 1 H 2.5 A 1 R26 10 Q3 1,2 3,4 4,5 D1 ES1D C9 150 pF 200 V R1 619 k 1% 10 6,7 R20 3.3 2,3 C21-C22 4700 pF R21 10 R24 10 Q4 R25 10 k VR21 15 V D21 C23-C26 100 F 10 V 5 6 C27 1 F C28 1 F RTN C20 Q2 R22 VR20 3.3 nF 10 k 15 V C7 1 nF 1.5 kV D4 L2 220 H C1-C3 1 F 100 V R7 10 k U2 R10 8.66 k 1% R12 15.9 k 1% DPA-Switch U1 DPA425R D L CONTROL C9 4.7 F 16 V U2 PC267 N1T D3 BAV19WS R6 150 C16 100 nF R12 5.1 R9 220 C14 1 F U3 LM431 AIM3X R11 10.0 k 1% PI-3561-072203 C D2 ES1D S X F VR1 SMBJ 150 A -VIN R3 15 k 1% C5 0.22 F R4 1.0 C6 68 F 10 V C15 10 F 10 V Figure 1. DPA425R - 50 W, 5 V, 6 A and 3.3 V, 6 A DC-DC Converter. . DI-53 www.powerint.com July 2003 DI-53 Key Design Points * Capacitors C20, CQ1gs and CQ3gs will all load transformer reset. Choose values to ensure sufficient reset at low line and safe maximum drain voltage at high line. Also use 300 kHz operation for longest reset time. * Capacitors C21 and C22 will capacitively drive MOSFET gate capacitances CQ2gs and CQ4gs (respectively). C21 and C22 should be chosen to ensure that gate drive voltage attains turn-on threshold of MOSFET (VgTH), at worst case conditions (low line for forward MOSFET). * Reduce transformer leakage inductance by filling each winding layer across the entire width of the bobbin. * Higher efficiency (+1%) can be acheived by using a DPA426R and increasing R3 to reduce the internal current limit. PI-3562-061603 TRANSFORMER PARAMETERS Core Material Bobbin Winding Details Winding Order and Pin Numbers Primary Inductance Primary Resonant Frequency Leakage Inductance Ferroxcube P/N: EFD25-3F3, ungapped 10-pin EFD25 surface mount bobbin Primary 11T, 4 x 28 AWG 3.3 V 2T, 2 x 4 x 26 AWG 5 V 3T, 2 x 4 x 26 AWG 5 V (6, 7-8, 9), Primary (1-10), 3.3 V (4.5-2.3) 250 H 25% at 300 kHz 3.8 MHz (minimum) 0.8 H (maximum) 95 90 Table 1. Transformer Design Parameters. Efficiency (%) 85 80 75 70 65 60 2 4 6 8 10 12 INDUCTOR PARAMETERS Core Material Bobbin Winding Details Winding Order and Pin Numbers Ferroxcube P/N: EFD25-3F3 ungapped 10-pin EFD20 surface mount bobbin 5 V 6T, 2 x 4 x 26 AWG 3.3 V 4T, 2 x 4 x 26 AWG Bias 12T, 1 x 30 TIW 5 V (9, 10-7, 8), 3.3 V (1, 2-3, 4), Bias (FL1-FL2) Pin (1, 2-3, 4): 3.5 H 10% at 300 kHz 36 VDC 54 VDC 72 VDC IOUT1 + IOUT2 (A) Inductance Figure 2. Efficiency vs. Output Power. Table 1. Inductor Design Parameters. A 7/03 www.powerint.com |
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