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EL5027
Data Sheet June 24, 2004 FN7426.0
Dual 2.5MHz Rail-to-Rail Input-Output Buffer
The EL5027 is a dual, low power, high voltage rail-to-rail input-output buffer. Operating on supplies ranging from 5V to 15V, while consuming only 110A per channel, the EL5027 has a bandwidth of 2.5MHz -(-3dB). The EL5027 also provides rail-to-rail input and output ability, giving the maximum dynamic range at any supply voltage. The EL5027 also features fast slewing and settling times, as well as a high output drive capability of 30mA (sink and source). These features make the EL5027 ideal for use as voltage reference buffers in Thin Film Transistor Liquid Crystal Displays (TFT-LCD). Other applications include battery power, portable devices, and anywhere low power consumption is important. The EL5027 is available in space-saving 6-pin TSOT package and operates over a temperature range of -40C to +85C.
Features
* 2.5MHz -3dB bandwidth * Unity gain buffer * Supply voltage = 4.5V to 16.5V * Low supply current (per buffer) = 110A * High slew rate = 1.2V/s * Rail-to-rail operation * Pb-free available (RoHS compliant)
Applications
* TFT-LCD drive circuits * Electronics notebooks * Electronics games * Personal communication devices * Personal Digital Assistants (PDA) * Portable instrumentation
Ordering Information
PART NUMBER (See Note) EL5027IWTZ-T7 EL5027IWTZ-T7A PACKAGE (Pb-Free) 6-Pin TSOT 6-Pin TSOT TAPE & REEL 7" (3K pcs) 7" (250 pcs) PKG. DWG. # MDP0049 MDP0049
* Wireless LANs * Office automation * Active filters * ADC/DAC buffer
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
Pinout
EL5027 (6-PIN TSOT) TOP VIEW
VINA 1 VS- 2 VINB 3 6 VOUTA 5 VS+ 4 VOUTB
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002-2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners.
EL5027
Absolute Maximum Ratings (TA = 25C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS+ +0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN AV
VS+ = +5V, VS- = -5V, RL = 10k and CL = 10pF to 0V, TA = 25C unless otherwise specified. CONDITION MIN TYP MAX UNIT
DESCRIPTION
Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain
VCM = 0V (Note 1) VCM = 0V
1 5 2 1 1.35
15
mV V/C
50
nA G pF
-4.5V VOUT 4.5V
0.995
1.005
V/V
OUTPUT CHARACTERISTICS VOL VOH ISC Output Swing Low Output Swing High Short-circuit Current IL = -5mA IL = 5mA Short to GND 4.85 -4.92 4.92 120 -4.85 V V mA
POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current (Per Buffer) VS is moved from 2.25V to 7.75V No load 55 80 110 160 dB A
DYNAMIC PERFORMANCE SR tS BW CS NOTES: 1. Measured over the operating temperature range 2. Slew rate is measured on rising and falling edges Slew Rate (Note 2) Settling to +0.1% -3dB Bandwidth Channel Separation -4.0V VOUT 4.0V, 20% to 80% VO = 2V step RL = 10k, CL = 10pF f = 5MHz 0.7 1.2 900 2.5 75 V/s ns MHz dB
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FN7426.0 June 24, 2004
EL5027
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN AV Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain 0.5 VOUT 4.5V 0.995 VCM = 2.5V (Note 1) VCM = 2.5V 1 5 2 1 1.35 1.005 50 15 mV V/C nA G pF V/V VS+ = +5V, VS- = 0V, RL = 10k and CL = 10pF to 2.5V, TA = 25C unless otherwise specified. CONDITION MIN TYP MAX UNIT
DESCRIPTION
OUTPUT CHARACTERISTICS VOL VOH ISC Output Swing Low Output Swing High Short-circuit Current IL = -5mA IL = 5mA Short to GND 4.85 80 4.92 120 150 mV V mA
POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current (Per Buffer) VS is moved from 4.5V to 15.5V No load 55 80 110 160 dB A
DYNAMIC PERFORMANCE SR tS BW CS NOTES: 1. Measured over the operating temperature range 2. Slew rate is measured on rising and falling edges Slew Rate (Note 2) Settling to +0.1% -3dB Bandwidth Channel Separation 1V VOUT 4V, 20% to 80% VO = 2V Step RL = 10k, CL = 10pF f = 5MHz 0.7 1.2 900 2.5 75 V/s ns MHz dB
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FN7426.0 June 24, 2004
EL5027
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN AV Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain 0.5 VOUT 14.5V 0.995 VCM = 7.5V (Note 1) VCM = 7.5V 1 5 2 1 1.35 1.005 50 15 mV V/C nA G pF V/V VS+ = +15V, VS- = 0V, RL = 10k and CL = 10pF to 7.5V, TA = 25C unless otherwise specified. CONDITION MIN TYP MAX UNIT
DESCRIPTION
OUTPUT CHARACTERISTICS VOL VOH ISC Output Swing Low Output Swing High Short-circuit Current IL = -5mA IL = 5mA Short to GND 14.85 80 14.92 120 150 mV V mA
POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current (Per Buffer) VS is moved from 4.5V to 15.5V No load 55 80 110 160 dB A
DYNAMIC PERFORMANCE SR tS BW CS NOTES: 1. Measured over the operating temperature range 2. Slew rate is measured on rising and falling edges Slew Rate (Note 2) Settling to +0.1% -3dB Bandwidth Channel Separation 1V VOUT 14V, 20% to 80% VO = 2V Step RL = 10k, CL = 10pF f = 5MHz 0.7 1.2 900 2.5 75 V/s ns MHz dB
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FN7426.0 June 24, 2004
EL5027 Typical Performance Curves
20 NORMALIZED MAGNITUDE (dB) 10 0 -10 -20 -30 1K 562 150 20 NORMALIZED MAGNITUDE (dB) 10 0 -10 -20 -30 1K 1nF 100pF
CL = 10pF VS = 5V 10k 1k
RL = 10k VS = 5V 47pF 12pF
10K
100K
1M
10M
10K
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS RL
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS CL
MAXIMUM OUTPUT SWING (VP-P)
2000 OUTPUT IMPEDANCE () 1600 1200 800 400 0 1K
TA = 25C VS = 5V
12 10 8 6 4 2 0 10K
VS = 5V RL = 10k CL = 12pF TA = 25C
10K
100K
1M
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 4. MAXIMUM OUTPUT SWING vs FREQUENCY
300 VOLTAGE NOISE (nV/Hz)
0.12 0.1 THD + NOISE (%)
100
0.08 0.06 0.04 0.02 0 1K
10
1K
10K
100K
1M
10M
100M
10K FREQUENCY (Hz)
100K
FREQUENCY (Hz)
FIGURE 5. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY
FIGURE 6. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
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FN7426.0 June 24, 2004
EL5027 Typical Performance Curves
100 90 80 OVERSHOOT (%) 70 60 50 40 30 20 0 10 100 CAPACITANCE (pF) 1K
(Continued)
% OF BUFFERS
VS = 5V RL = 10k VIN = 50mV TA = 25C
18 16 14 12 10 8 6 4 2 0 -8 -6 -4 -2 0 2 4 6 -10 8 65 65 INPUT OFFSET VOLTAGE (mV) 10 85 85
FN7426.0 June 24, 2004
FIGURE 7. SMALL SIGNAL OVERSHOOT vs LOAD CAPACITANCE
FIGURE 8. INPUT OFFSET VOLTAGE DISTRIBUTION
3.5 INPUT BIAS CURRENT (nA) 3 2.5 2 1.5 1
OUTPUT HIGH VOLTAGE (V)
VS = 5V
4.955 4.95 4.945 4.94 4.935 4.93 4.925
VS = 5V IOUT = 5mA
-35
-15
5
25
45
65
85
-35
-15
5
25
45
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 9. INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 10. OUTPUT HIGH VOLTAGE vs TEMPERATURE
-4.938 OUTPUT LOW VOLTAGE (V) -4.942 -4.946 -4.95 -4.954 -4.958
VS = 5V IOUT = -5mA VOLTAGE GAIN (V/V)
1.0045 1.004 1.0035 1.003 1.0025 1.002 1.0015
VS = 5V
-35
-15
5
25
45
65
85
1.001
-35
-15
5
25
45
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 11. OUTPUT LOW VOLTAGE vs TEMPERATURE
FIGURE 12. VOLTAGE GAIN vs TEMPERATURE
6
EL5027 Typical Performance Curves
2.255
(Continued)
VS=5V SUPPLY CURRENT (mA)
0.185 0.18 0.175 0.17 0.165 0.16
VS = 5V
SLEW RATE (V/s)
2.245
2.235
2.225
2.215 -40
-20
0
20
40
60
80
-35
-15
5
25
45
65
85
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 13. SLEW RATE vs TEMPERATURE
FIGURE 14. SUPPLY CURRENT PER CHANNEL vs TEMPERATURE
0.195 SUPPLY CURRENT (mA) 0.19 0.185 0.18 0.175 0.17 0.165
TA = 25C
1V/DIV
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (V)
4s/DIV
FIGURE 15. SUPPLY CURRENT PER CHANNEL vs SUPPY VOLTAGE
FIGURE 16. LARGE SIGNAL TRANSIENT RESPONSE
20mV/DIV
1s/DIV
FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE
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FN7426.0 June 24, 2004
EL5027 Pin Descriptions
6-Pin tsot 1 Pin Name VINA Buffer A Input Function Equivalent Circuit
VS+
VSCIRCUIT 1
2 3 4
VSVINB VOUTB
Negative Supply Voltage Buffer B Input Buffer B Output (Reference Circuit 1)
VS+
GND CIRCUIT 2
VS-
5 6
VS+ VOUTA
Positive Supply Voltage Buffer A Output (Reference Circuit 2)
Applications Information
Product Description
The EL5027 unity gain buffer is fabricated using a high voltage CMOS process. It exhibits rail-to-rail input and output capability and has low power consumption (500A per buffer). These features make the EL5027 ideal for a wide range of general-purpose applications. When driving a load of 10k and 12pF, the EL5027 has a -3dB bandwidth of 2.5MHz and exhibits 2.2V/s slew rate.
5V 10s
VS=5V TA=25C VIN=10VP-P
Operating Voltage, Input, and Output
The EL5027 is specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most EL5027 specifications are stable over both the full supply range and operating temperatures of -40C to +85C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The output swings of the EL5027 typically extend to within 80mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 1 shows the input and output waveforms for the device. Operation is from 5V supply with a 10k load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.985VP-P.
5V
FIGURE 18. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT
Short-Circuit Current Limit
The EL5027 will limit the short-circuit current to 120mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds 30mA. This limit is set by the design of the internal metal interconnects.
Output Phase Reversal
The EL5027 is immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 2 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's
8
OUTPUT
FN7426.0 June 24, 2004
INPUT
EL5027
output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur.
1V 10s
where: i = 1 to 2 for dual buffer VS = Total supply voltage ISMAX = Maximum supply current per channel VOUTi = Maximum output voltage of the application ILOADi = Load current If we set the two PDMAX equations equal to each other, we can solve for RLOADi to avoid device overheat. Figure 20 and Figure 21 provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves.
VS=2.5V TA=25C VIN=6VP-P 1V
FIGURE 19. OPERATION WITH BEYOND-THE-RAILS INPUT
Power Dissipation
With the high-output drive capability of the EL5027 buffer, it is possible to exceed the 125C 'absolute-maximum junction temperature' under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the buffer to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA
Unused Buffers
It is recommended that any unused buffer have the input tied to the ground plane.
Driving Capacitive Loads
The EL5027 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking increase. The buffers drive 10pF loads in parallel with 10k with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5 and 50) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a "snubber" circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150 and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain.
where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature JA = Thermal resistance of the package PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or:
P DMAX = i [ V S x I SMAX + ( V S + - V OUT i ) x I LOAD i ]
Power Supply Bypassing and Printed Circuit Board Layout
The EL5027 can provide gain at high frequency. As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a 0.1F ceramic capacitor should be placed from VS+ to pin to VS- pin. A 4.7F tantalum capacitor should then be connected in parallel, placed in the region of the buffer. One 4.7F capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used.
when sourcing, and:
P DMAX = i [ V S x I SMAX + ( V OUT i - V S - ) x I LOAD i ]
when sinking.
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FN7426.0 June 24, 2004
EL5027
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN7426.0 June 24, 2004

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