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PRO-LINX TM GS7000
Serial Digital Video Transceiver
PRELIMINARY DATA SHEET FEATURES * fully integrated 270Mb/s SDI receiver or transmitter * fully compliant with SMPTE 259M-C * lock and carrier detect output indication * performance from 0 - 85C RECEIVER FUNCTION * accepts SMPTE 259M-C 270Mb/s serial digital video and outputs SMPTE 125M compliant 27Mb/s parallel digital video and clock * integrated cable equalization (beyond 100m Belden 8281) * ease of design use and adjustment free operation * H timing signal output TRANSMITTER FUNCTION * accepts SMPTE 125M (27Mb/s) parallel video data and clock, outputs SMPTE 259M-C 270Mb/s serial digital video * integrated cable driver provides one differential output (or two single-ended outputs) APPLICATIONS Space limited, low power 270Mb/s serial to parallel or parallel to serial interfaces; Alternate, broadcast quality uncompressed video interface for industrial and professional video equipment using the IEEE P1394 interface. ORDERING INFORMATION
PART NUMBER GS7000-CQT GS7000-CTT PACKAGE 52 pin MQFP 52 pin MQFP Tape TEMPERATURE 0C to 85C 0C to 85C
DESCRIPTION The GS7000 is a dual function IC capable of operating as either a 270Mb/s Serial Digital Video receiver or a 270Mb/s Serial Digital Video transmitter. The GS7000 is designed so that it can be programmed to operate in either receive or transmit mode via a mode select pin. When operating as a receiver, the serial data input accepts SMPTE 259M-C compliant signals. Line terminations are on the device. An on-chip by-passable fixed gain equalizer provides cable equalization beyond 100m of high quality co-axial cable. The clock recovery is performed on chip with minimal external components. Incoming Serial Digital Video data is decoded using a NRZI decoder and SMPTE descrambler to provide clocked SMPTE 125M compliant parallel output. The SMPTE descrambler and NRZI decoding functions can be disabled. When operating as a transmitter, the GS7000 accepts parallel SMPTE 125M compliant ten bit video. An on-chip scrambler and NRZI encoder converts the parallel data into a bit serial SMPTE 259M-C compliant NRZI output signal suitable for driving co-axial cable. Through the SMPTE select pin, the SMPTE scrambler and NRZI coding functions can be disabled.
GS7000
SMPTE
C1 C2
DIN (0,9) 10
SCRAMBLER P to S
NRZI ENCODER
SDO SDO SIGNAL LOCK DETECT
f/10 PCLKOUT H
PLL
LOCK CD PCLKIN
MUX
DOUT(0,9) 10
S to P
TRS DETECTOR DESCRAMBLER NRZI DECODER SLICER EQUALIZER SDI SDI
SMPTE
Rx/Tx
EQ
BLOCK DIAGRAM
Revision Date: August 1999 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com Document No. 522 - 06 - 02
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Range (any input) DC Input Current (any one input) VALUE 5.5V VEE < VIN < VCC 10mA 830mW 125C 0C TA 85C -65C TS 150C 260C
GS7000
Power Dissipation (VCC = 5.25 V) Maximum Die Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (soldering 10s)
AC ELECTRICAL CHARACTERISTICS (Receiver Mode)
VCC = 5V, VEE = 0V, TA = 0C to 85C, unless otherwise specified. Serial Data Rate = 270Mb/s, Parallel Data Rate = 27Mb/s, fPCLK = 27MHz
PARAMETER Parallel Data Output - Rise/Fall Time PCLK rising edge to DOUT(n) center PCLK rise/fall time Input Return Loss
CONDITIONS CL = 20pF
SYMBOL tR/F_PDO tD
MIN 1.0 0.5 -
TYP 17
MAX 6.0 5 3.0 -
UNITS ns ns ns dB
NOTES 1 2, 3 1
TEST LEVEL 1 1 1 6
CL = 20pF 75 match 5MHz -> 270MHz
tR/F_PCLKo LOSSIN
Asynchronous Lock Time Synchronous Lock Time Input Jitter Tolerance Output PCLK Jitter Max Error Free Cable Length NOTES pathological Input pathological Input pathological Input
tLOCK_ASYNC tLOCK_SYNC tJ_SI tJ_PCLKo
75
0.4 1000 100
250 10 -
ms s U.I. ps p-p m
4 5 6 6 6, 7
1 1 4 1 1, 4
TEST LEVELS 1. 100% tested at 25 C 2. Guaranteed by design 3. Inferred or correlated value 4. Evaluated using test setup Figure 1a. 5. Evaluated using test setup Figure 1b. 6. Evaluated using test setup Figure 1c.
1. Rise/Fall time is defined as the time for the signal to rise from 20% to 80% of the specified p-p value, or to fall from 80% to 20% of the specified value. 2. Refer also to Figure 21. 3. This is the time difference between the rising edge of PCLKOUT and the center of the bit period. 4. This is the time delay between a valid serial TRS signal on the input, to the moment valid data appears on the parallel outputs. 5. This is the time for the PLL to re-lock when video streams are switched during the vertical blanking interval in accordance with SMPTE RP168-1993. The two streams may be 180 out of phase with respect to one another, but pixel aligned. 6. This pathological pattern is defined in SMPTE RP178-1996, paragraphs 4.1 and 4.3. 7. "Error free" is defined as no single bit errors over a period of 10 minutes, using Belden 8281 Cable and 75 connections. The MIN value is fully tested and the TYP value is based on using the EB7000 Evaluation Board.
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AC ELECTRICAL CHARACTERISTICS (Transmitter Mode)
VCC = 5V, VEE = 0V, TA = 0C to 85C, unless otherwise specified in `conditions' Serial Data Rate = 270Mb/s, Parallel Data Rate = 27Mb/s, fPCLK = 27MHz
PARAMETER Parallel Data Inputs - rise/fall time Parallel Data Inputs - setup Parallel Data Inputs - hold Parallel Data Inputs - high Parallel Data Inputs - low Parallel Clock Input - rise/fall time Serial Data Output - signal swing Serial Data Output - high Serial Data Output - low Serial Data Output - rise/fall time Serial Data Output - jitter Lock Time Output Return Loss NOTES 8. Refer to Figure 26.
CONDITIONS
SYMBOL tR/F_DPI tSETUP tHOLD
MIN 0.5 4 4 2.0 VEE 0.5 720 400 15
TYP
MAX
10
UNITS ns ns ns V V ns mV p-p V V ps ps p-p ms dB
NOTES 1 8 8
TEST LEVEL 2 1 1 1 1 2
800 VCC - 0.8 VCC - 1.6 600 -
VCC 0.8 4 880 1500 675 250 -
GS7000
VCC = 5.25V VCC = 4.75V
VDPI VDPI tR/F_PCLK
VCC = 4.75 - 5.25V
VDSO VOH VOL tR/F
9, 10 11 11 1 12 13
1 2 2 1 1 1 6
VCC = 4.75V
tJ_DSO tLOCK
270MHz
TEST LEVELS 1. 100% tested at 25C 2. Guaranteed by design 3. Inferred or correlated value 4. Evaluated using test setup Figure 1a. 5. Evaluated using test setup Figure 1b. 6. Evaluated using test setup Figure 1c.
9. The outputs are capable of driving a 75 single-ended load, terminated to ground. 10.This value is measured after the resistor network at the SDI outputs shown in Figure 2. 11.Typical PECL values 12.6 additive intrinsic jitter contribution based on pathological input signal 13.This is the lapsed time between valid parallel TRS input to valid serial output
DC ELECTRICAL CHARACTERISTICS
VCC = 5V, VEE = 0V, TA = 0C to 85C, unless otherwise specified. Serial Data Rate = 270Mb/s, Parallel Data Rate = 27Mb/s, fPCLK = 27MHz
PARAMETER Positive Supply Voltage Supply Current - Receive Mode Supply Current - Transmit Mode Power Consumption - Receive Mode Power Consumption - Transmit Mode Logic Inputs - Low Logic Inputs - High Logic Outputs - Low Logic Outputs - High
CONDITIONS
SYMBOL VCC
MIN + 4.75 VEE 2.0 VEE 2.4
TYP + 5.00 150 130 750 650 -
MAX + 5.25 0.8 VCC 0.5 VCC
UNITS V mA mA mW mW V V V V
TEST LEVEL
VCC = 5.25V VCC = 5.25V VCC = 5.25V VCC = 5.25V VCC = 5.25V VCC = 4.75V VCC = 5.25V VCC = 4.75V
ICC ICC PD PD VIL VIH VOL VOH
1 1 3 3 2 2 2 2
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DATA TEKTRONIX GigaBERT 1400 TRANSMITTER DATA GS9028 CABLE DRIVER
BELDEN 8281 CABLE
EB7000 BOARD
TEKTRONIX TDS 820 SCOPE
CLOCK
TRIGGER
GS7000
Fig. 1a Test Setup for Jitter Measurements
TEKTRONIX VIDEO SlGNAL GENERATOR
VIDEO STREAM WITH EDH
BELDEN 8281 CABLE
EB7000 BOARD
EB9021 EDH ERROR COUNTER
Fig. 1b Test Setup for Error-Free Cable Length
HP 4195A NETWORK ANALYSER
BELDEN 8281 CABLE
BELDEN 8281 CABLE EB7000 BOARD
HP 4195A NETWORK ANALYSER
Fig. 1c Test Setup for Return Loss Measurements
VCC 7.5 10u 10u SERIAL DIGITAL OUT 825 52 51 50 49 48 47 46 45 44 43 42 41 40 NC CD SMPTE NC SDO SDO NC VCC3 VEE3 VDD PCLKOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 NC NC 39 DOUT0 38 DOUT1 37 DOUT2 36 DOUT3 35 34 DOUT4 33 DOUT5 32 DOUT6 31 DOUT7 30 DOUT8 29 DOUT9 28 LOCK 27 NC 825 7.5 VCC 100n
220
CD 10k VCC MODE VCC 100n 33 PARALLEL CLOCK OUT 10p 100n 10u VCC
SERIAL DIGITAL OUT
NC DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 H
All resistors in ohms, all capacitors in farads, unless otherwise shown.
PARALLEL DATA INPUTS
GS7000
PARALLEL DATA OUTPUTS VCC 220
10k
LOCK
PCLKIN
VEE1
SDI
SDI
EQ
NC
14 15 16 17 18 19 20 21 22 23 24 25 26 100n 100n 100n
NC
C1
C2
NC
Rx/Tx
VCC1
VCC2
VEE2
VCC Rx/Tx
PARALLEL CLOCK IN SERIAL DIGITAL IN
33 10p 10u 10u VCC
VCC EQ
Fig. 2 Test Circuit (Half Duplex Operation)
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PIN CONNECTIONS
NC VEE3 SDO SDO VCC3 CD SMPTE NC NC PCLKOUT VDD VSS NC 52 51 50 49 48 47 46 45 44 43 42 41 40 1 2 3 4 5 GS7000 6 TOP VIEW 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 NC VEE1 C1 C2 VCC1 SDI SDI VCC2 PCLKIN VEE2 EQ Rx/Tx NC
NC DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 H NC
39 38 37 36 35 34 33 32 31 30 29 28 27
NC DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 DOUT8 DOUT9 LOCK NC
GS7000
PIN DESCRIPTIONS
NUMBER 1, 13, 14, 26, 27, 39, 40, 44, 45, 52 2-11 12 SYMBOL NC TYPE MODE DESCRIPTION No Connect - Connected to Ground.
DIN(0,9) H
I O
Tx Rx
27Mb/s Parallel Data Input Indicates the presence of active video. Low after SAV ID and high after EAV ID Most negative supply for analog circuits External 100nF Loop Filter Capacitor Connection Most positive supply for analog circuits Differential Serial Data Input Most positive supply for PECL circuits 27MHz External Clock Input Most negative supply for PECL circuits Equalizer control. LOW = EQ on, HIGH = EQ bypassed. Receiver/Transmitter Mode Control Input Signal Lock Indication Output. Goes HIGH approximately 38 s after valid parallel data occurs. 27Mb/s Parallel Data Output
15 16, 17 18 19, 20 21 22 23 24 25 28
VEE1 C1, C2 VCC1 SDI, SDI VCC2 PCLKIN VEE2 EQ Rx/Tx LOCK
I I I I O
Rx Tx Rx Rx/Tx
29 - 38
DOUT(9,0)
O
Rx
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PIN DESCRIPTIONS
NUMBER 41 42 43 SYMBOL VSS VDD PCLKOUT SMPTE TYPE O I MODE Rx Rx/Tx DESCRIPTION Most negative supply for CMOS circuits Most positive supply for CMOS circuits 27MHz Clock Output NRZI de/encoding and SMPTE de/scrambling control. LOW = NRZI and SMPTE mode on, HIGH = NRZI and SMPTE mode disabled. Indicates loss of carrier. Low when carrier is present and high when carrier is lost. Most positive supply for Analog and PECL Circuits Differential Serial Data Output Most negative supply for Analog and PECL Circuits
GS7000
46
47
CD
O
Rx/Tx
48 49, 50 51
VCC3 SDO, SDO VEE3
O -
Tx -
INPUT / OUTPUT CIRCUITS
VDD VDD TO INTERNAL STRUCTURES
ESD
ESD
IN
TO INTERNAL STRUCTURES
OUT
VEE VEE
Fig. 3 SDI, SDI
Fig. 4 SDO, SDO
VDD
VDD
ESD
ESD
TTL-IN
TO INTERNAL STRUCTURES
TO INTERNAL STRUCTURES
OUT
VSS
VEE
Fig. 5 DIN(0,9), PCLKIN, EQ, Rx/Tx, SMPTE
Fig. 6 DOUT(0,9), H, LOCK, CD
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VDD
ESD
TO INTERNAL STRUCTURES
OUT
GS7000
VEE
Fig. 7 PCLKOUT
TYPICAL PERFORMANCE CURVES
(VCC = 5 V, TA = 25 C unless otherwise shown)
DATA TO FOLLOW
DATA TO FOLLOW
Fig. 8 Output PCLK Jitter vs. Cable Length
Fig. 9
815
0
SERIAL DATA OUTPUT LEVEL (mV)
810
-10
RETURN LOSS (dB)
270MHz -20
805
800
-30
135MHz
795
-40
790 0 10 20 30 40 50 60 70 80 90
-50 0.05 GHz 1 GHz
TEMPERATURE (C)
FREQUENCY (GHz)
Fig. 10 Serial Data Output Level vs. Temperature
Fig. 11 Input Return Loss
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0
-10
0
270MHz
RETURN LOSS (dB)
-20
AMPLITUDE (dB)
600kHz -3
GS7000
-30
135MHz
-40
-6
-50 0.05 1
1k
10k
100k
1M
10M
FREQUENCY (GHz)
FREQUENCY (Hz)
Fig. 12 Output Return Loss
Fig. 13 Loop Bandwidth
J1 J2 J0.5
54MHz 1.97GHz 270MHz 540MHz
Impedances normalized to 50 9 -J0.5
-J2 -J1
Fig. 14 Serial Data Output
J1 J2 J0.5
800
Fig. 15 Input Impedance
Rx 700 600
POWER (mW)
500 400 300 200 100
Tx
1.97GHz
54MHz
270MHz 540MHz
Impedances normalized to 50 9 -J0.5
0 0 10 20 30 40 50 60 70 80 90
-J2 -J1
TEMPERATURE (C)
Fig. 16 Output Impedance
Fig. 17 Power vs. Temperature
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RECEIVER OPERATION
EQ 0 1 0 1 Rx/Tx 1 1 1 1 SMPTE 0 0 1 1 GS7000 OPERATING MODE SMPTE 259M Receiver (Equalizer on, SMPTE / NRZI on) SMPTE 259M Receiver with equalizer bypassed Receiver function with NRZI and SMPTE Descrambler disabled, equalizer enabled.
GS7000
Receiver function with NRZI and SMPTE Descrambler disabled, equalizer bypassed.
The diagram below depicts the active portions of the chip when operating in Receiver mode (Rx/Tx set to logic high level) with the equalizer, descrambling and NRZI functions all active. In this mode of operation the output of the LOCK pin is logic high whenever the receiver has successfully locked to the input serial bit stream. The output H is set low after the SAV ID and is set high after the EAV ID when these sequences are identified in the incoming bit stream. Note the function available called "Equalizer Control" (EQ). Setting EQ to a logic HIGH level shuts off the equalization function of the device for implementations where the length of cable to be equalized is very short (less than 10 m). It is possible to turn off the NRZI and SMPTE Descrambler function by setting SMPTE HIGH. When operating in this mode, the output of H, will be either "1" or "0" (indeterminate).
SMPTE C1 C2
SCRAMBLER DIN (0,9) 10 P to S
NRZI ENCODER
SDO SDO
f/10 PCLKOUT H
PLL
SIGNAL LOCK DETECT
LOCK CD PCLKIN
MUX
DOUT(0,9) 10
S to P
TRS DETECTOR DESCRAMBLER NRZI DECODER SLICER EQUALIZER SDI SDI
SMPTE
Rx/Tx
EQ
Fig. 18 Functional Block Diagram (Receiver Mode)
TRANSMITTER OPERATION
EQ X X Rx/Tx 0 0 SMPTE 0 1 SMPTE 259M Transmitter Transmitter function with NRZI and SMPTE Scrambler disabled GS7000 OPERATING MODE
The diagram below depicts the active portions of the chip when operating in Transmitter mode (Rx/Tx set to logic low level), with the NRZI and scrambling functions active. Note that similar to receive mode above, it is possible to turn off the NRZI and SMPTE Scrambler by setting SMPTE high.
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SMPTE
C1 C2
SCRAMBLER DIN (0,9) 10 P to S
NRZI ENCODER
SDO SDO
GS7000
f/10 PCLKOUT H
PLL
SIGNAL LOCK DETECT
LOCK CD PCLKIN
MUX
DOUT(0,9) 10
S to P
TRS DETECTOR DESCRAMBLER NRZI DECODER SLICER EQUALIZER SDI SDI
SMPTE
Rx/Tx
EQ
Fig. 19 Functional Block Diagram (Transmitter Mode)
DIAGRAMS The figure below describes the timing relationship between the outputs of the GS7000 when operating in receiver mode.
...
XXX XXX 3FF 000 000 XXX SAV ID XXX XXX XXX XXX ... XXX XXX 3FF 000 000 XXX EAV ID XXX XXX PCLKOUT DOUT(n)
...
Fig. 20 Timing Diagram For Parallel Outputs, PCLKOUT and H
H
The figure below describes the relationship between the output parallel clock and the output parallel data. The output parallel clock rising edge is centered on the output data within 5 ns.
WORD CENTER 5 ns 5 ns
DOUT(n)
PCLKOUT
Fig. 21 Receiver Parallel Clock Alignment
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The figure below describes the relationship between the input parallel clock and the input parallel data. The input parallel data must be stable for 4ns prior to the rising edge of the PCLKIN (setup time), and for 4 ns following the rising edge of the PCLKIN (hold time).
tSETUP = 4ns
tHOLD = 4ns
GS7000
DIN(n)
PCLKIN
Fig. 22 Transmitter Setup and Hold Time
TYPICAL APPLICATION CIRCUITS
VCC1 GND 100n 10u 10n 14 15 VCC 100n 16 17 100n 18 75 75 19 20 VCC 21 VCC 22 100n 23 475 24 VCC 25 26 2k VCC 475 1u 10n 220 LOCK NC VEE1 C1 C2 VCC1 SDI SDI VCC2 PCLKIN VEE2 EQ Rx/Tx DOUT9 DOUT8 DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 LOCK NC NC GS7000 VCC SSI-CD VCC 13 12 11 10 NC H DIN9 100p 987 DIN7 DIN6 6 DIN5 5432 DIN4 DIN3 DIN2 DIN1 1 DIN0 NC VCC 220 100n CD DIN8
VCC 10n 10n 75 10n 37.5 75 75 VCC 10n
AGC VCC DIN DIN GND VCC
AGC CD DOUT DOUT CD-ADJ OEM
GND TRISTATE
GS9024 VCC
All resistors in ohms, all capacitors in farads, unless otherwise shown.
DOUT0
NC 52 VEE3 51 50 SDO 49 SDO 48 VCC3 47 CD 46 SMPTE 45 NC 44 NC 43 PCLKOUT 42 VDD 41 VSS 40 NC NC
10k VCC MODE
33
PCLK OUT 10p
75
10n
VCC
27 28 29 30 31 32 33 34 35 36 37 38 39 10k
100n
PARALLEL DATA OUTPUTS
Typical Receiver Application Circuit with External Equalizer
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PARALLEL DATA IN 13 12 11 10 9 8 NC H DIN9 DIN8 DIN7 76 DIN6 DIN5 543 DIN4 DIN3 DIN2 21 DIN1 DIN0 NC 100n NC VEE3 SDO SDO VCC3 CD GS7000 SMPTE NC NC PCLKOUT VDD VSS DOUT9 DOUT8 DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 LOCK DOUT0 NC NC 52 51 50 10u 49 10u 48 VCC 47 100n 46 45 44 43 42 41 40 V VCC 10u VCC IN 75 75 VEE
100n
VCC
OUT
75
75
75 8.2n 1u
14 15 100n 16 VCC 17 18 VCC 100n 10k 19 10k 20 VCC 100n 21 22 23 10p 24 PARALLEL CLOCK IN 25 26 33 VCC
NC VEE1 C1 C2 VCC1 SDI SDI VCC2 PCLKIN VEE2 EQ Rx/Tx NC NC
OUT OUT 8.2n 75 59 OUT VCC 220 CD 1u RSET
GS7000
IN NC/GND
GS9028 VCC 10k MODE
CC
100n
27 28 29 30 31 32 33 34 35 36 37 38 39 VCC 10k 220 VCC VCC LOCK 100n 10u
All resistors in ohms, all capacitors in farads, unless otherwise shown.
Typical Transmitter Application Circuit with Cable Driver
SDO
7.5 825
10
GS7000 7.5 SDO 825 75 10
All resistors in ohms, all capacitors in farads, unless otherwise shown.
Typical Transmitter Application Circuit - Single Ended Output Operation (as above with changes shown)
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VCC 220 10k CD VCC
All resistors in ohms, all capacitors in farads, unless otherwise shown.
VCC VCC 100n 10p 10u
33 MODE VCC 100n 52 51 50 49 48 47 46 45 44 43 42 41 40 SMPTE NC CD NC NC SDO SDO VCC3 VDD VEE3 PCLKOUT VSS NC VCC 100n
GS7000
VCC1
VCC2
SDI
SDI
EQ
NC
14 15 16 17 18 19 20 21 22 23 24 25 26 100n 100n 100n VCC VCC SERIAL DIGITAL INPUT 10u 10u VCC 10k
NC
C1
C2
NC
Rx/Tx
VEE1
H
PCLKIN VEE2
1 2 3 4 5 6 7 8 9 10 11 12 13
NC DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9
GS7000
NC 39 DOUT0 38 DOUT1 37 DOUT2 36 DOUT3 35 DOUT4 34 DOUT5 32 33 D 31 30 DOUT8 29 DOUT9 28 LOCK 27 NC DOUT7
OUT6
PARALLEL CLOCK OUT
PARALLEL DATA OUT
VCC 220
LOCK
EQ
Typical Receiver Application Circuit - Unbalanced Input Operation
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PACKAGE DIMENSIONS
17.20 BSC 14.00 BSC
14 2
0.40 MIN 0 MIN 0.13 MIN RADIUS 7 MAX 0 MIN
GS7000
17.20 BSC 14.00 BSC
14 2 0.13 MIN. RADIUS 1.60 REF 0.88 0.15
52 pin MQFP
1.00 BSC 0.50 MAX 0.35 MIN
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
PRELIMINARY DATA SHEET The product is in a preproduction phase and specifications are subject to change without notice.
REVISION NOTES:
Removed figure 8.
GENNUM CORPORATION
MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM UK LIMITED Centaur House, Ancells Bus. Park, Ancells Rd, Fleet, Hants, England GU13 8UJ Tel. +44 (0)1252 761 039 Fax +44 (0)1252 761 114
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright April 1999 Gennum Corporation. All rights reserved. Printed in Canada.
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