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| HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DESCRIPTION The 6N137, HCPL-2601/2611 single-channel and HCPL-2630/2631 dual-channel optocouplers consist of a 850 nm AlGaAS LED, optically coupled to a very high speed integrated photodetector logic gate with a strobable output. This output features an open collector, thereby permitting wired OR outputs. The coupled parameters are guaranteed over the temperature range of -40C to +85C. A maximum input signal of 5 mA will provide a minimum output sink current of 13 mA (fan out of 8). An internal noise shield provides superior common mode rejection of typically 10 kV/s. The HCPL- 2601 and HCPL- 2631 has a minimum CMR of 5 kV/s. The HCPL-2611 has a minimum CMR of 10 kV/s. 8 8 1 DUAL-CHANNEL HCPL-2630 HCPL-2631 8 1 1 FEATURES * * * * * * * * Very high speed-10 MBit/s Superior CMR-10 kV/s Double working voltage-480V Fan-out of 8 over -40C to +85C Logic gate output Strobable output Wired OR-open collector U.L. recognized (File # E90700) N/C 1 8 VCC +1 VF1 8 VCC +2 VF _ 3 7 VE _2 7 V01 6 VO _ V 3 6 V02 F2 N/C 4 5 GND +4 5 GND APPLICATIONS * * * * * * * Ground loop elimination LSTTL to TTL, LSTTL or 5-volt CMOS Line receiver, data transmission Data multiplexing Switching power supplies Pulse transformer replacement Computer-peripheral interface 6N137 HCPL-2601 HCPL-2611 HCPL-2630 HCPL-2631 TRUTH TABLE (Positive Logic) Input H L H L H L Enable H H L L NC NC A 0.1 F bypass capacitor must be connected between pins 8 and 5. (See note 1) Output L H H H L H 2001 Fairchild Semiconductor Corporation DS300202 7/9/01 1 OF 11 www.fairchildsemi.com HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Operating Temperature Lead Solder Temperature EMITTER DC/Average Forward Input Current Enable Input Voltage Not to exceed VCC by more than 500 mV Reverse Input Voltage Power Dissipation DETECTOR Supply Voltage Output Current Output Voltage Collector Output Power Dissipation Single channel Dual channel (Each channel) Each channel Single channel Dual channel (Each channel) Each channel Single channel Dual channel (Each channel) Single channel Dual channel (Each channel) Single channel VE VR PI VCC (1 minute max) IO VO PO IF (No derating required up to 85C) Symbol TSTG TOPR TSOL Value -55 to +125 -40 to +85 260 for 10 sec 50 30 5.5 5.0 100 45 7.0 50 50 7.0 85 60 V V mW Units C C C mA DUAL-CHANNEL HCPL-2630 HCPL-2631 V mA V mW RECOMMENDED OPERATING CONDITIONS Parameter Input Current, Low Level Input Current, High Level Supply Voltage, Output Enable Voltage, Low Level Enable Voltage, High Level Low Level Supply Current Fan Out (TTL load) Symbol IFL IFH VCC VEL VEH TA N Min 0 *6.3 4.5 0 2.0 -40 Max 250 15 5.5 0.8 VCC +85 8 Units A mA V V V C * 6.3 mA is a guard banded value which allows for at least 20 % CTR degradation. Initial input current threshold value is 5.0 mA or less www.fairchildsemi.com 2 OF 11 7/9/01 DS300202 HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 ELECTRICAL CHARACTERISTICS (TA = -40C to +85C Unless otherwise specified.) DUAL-CHANNEL HCPL-2630 HCPL-2631 INDIVIDUAL COMPONENT CHARACTERISTICS Parameter Test Conditions EMITTER (IF = 10 mA) Input Forward Voltage TA =25C Input Reverse Breakdown Voltage (IR = 10 A) Input Capacitance (VF = 0, f = 1 MHz) Input Diode Temperature Coefficient (IF = 10 mA) DETECTOR High Level Supply Current Single Channel (VCC = 5.5 V, IF = 0 mA) Dual Channel (VE = 0.5 V) Low Level Supply Current Single Channel (VCC = 5.5 V, IF = 10 mA) Dual Channel (VE = 0.5 V) Low Level Enable Current (VCC = 5.5 V, VE = 0.5 V) High Level Enable Current (VCC = 5.5 V, VE = 2.0 V) High Level Enable Voltage (VCC = 5.5 V, IF = 10 mA) Low Level Enable Voltage (VCC = 5.5 V, IF = 10 mA) (Note 3) Symbol VF BVR CIN VF/ TA ICCH ICCL IEL IEH VEH VEL 5.0 60 -1.4 7 10 9 14 -0.8 -0.6 2.0 0.8 10 15 13 21 -1.6 -1.6 Min Typ** 1.4 Max 1.8 1.75 Unit V V pF mV/C mA mA mA mA V V SWITCHING CHARACTERISTICS AC Characteristics Propagation Delay Time to Output High Level Propagation Delay Time to Output Low Level Pulse Width Distortion (TA = -40C to +85C, VCC = 5 V, IF = 7.5 mA Unless otherwise specified.) Symbol TPLH TPHL TPHL-TPLH tr tf tELH tEHL Min 20 25 Typ** 45 45 3 50 12 20 20 Max 75 100 75 100 35 Unit ns ns ns ns ns ns ns Test Conditions (Note 4) (TA =25C) (RL = 350 , CL = 15 pF) (Fig. 12) (Note 5) (TA =25C) (RL = 350 , CL = 15 pF) (Fig. 12) (RL = 350 , CL = 15 pF) (Fig. 12) (RL = 350 , CL = 15 pF) Output Rise Time (10-90%) (Note 6) (Fig. 12) (RL = 350 , CL = 15 pF) Output Fall Time (90-10%) (Note 7) (Fig. 12) Enable Propagation Delay Time (IF = 7.5 mA, VEH = 3.5 V) to Output High Level (RL = 350 , CL = 15 pF) (Note 8) (Fig. 13) Enable Propagation Delay Time (IF = 7.5 mA, VEH = 3.5 V) to Output Low Level (RL = 350 , CL = 15 pF) (Note 9) (Fig. 13) Common Mode Transient Immunity (TA =25C) VCM = 50 V, (Peak) (at Output High Level) (IF = 0 mA, VOH (Min.) = 2.0 V) 6N137, HCPL-2630 (RL = 350 ) (Note 10) HCPL-2601, HCPL-2631 (Fig. 14) HCPL-2611 VCM = 400 V (RL = 350 ) (IF = 7.5 mA, VOL (Max.) = 0.8 V) Common Mode 6N137, HCPL-2630 VCM = 50 V (Peak) Transient Immunity HCPL-2601, HCPL-2631 (TA =25C) (at Output Low Level) (Note 11) (Fig. 14) HCPL-2611 (TA =25C) VCM = 400 V CMH 5000 10,000 10,000 10,000 15,000 10,000 V/s CML 5000 10,000 10,000 15,000 V/s DS300202 7/9/01 3 OF 11 www.fairchildsemi.com HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 TRANSFER CHARACTERISTICS DC Characteristics High Level Output Current Low Level Output Current (TA = -40C to +85C Unless otherwise specified.) Test Conditions (VCC = 5.5 V, VO = 5.5 V) (IF = 250 A, VE = 2.0 V) (Note 2) (VCC = 5.5 V, IF = 5 mA) (VE = 2.0 V, ICL = 13 mA) (Note 2) Input Threshold Current (VCC = 5.5 V, VO = 0.6 V, VE = 2.0 V, IOL = 13 mA) Symbol IOH VOL IFT .35 3 Min Typ** Max 100 0.6 5 Unit A V mA DUAL-CHANNEL HCPL-2630 HCPL-2631 ISOLATION CHARACTERISTICS Characteristics Input-Output Insulation Leakage Current (TA = -40C to +85C Unless otherwise specified.) Test Conditions Symbol Min Typ** Max Unit (Relative humidity = 45%) (TA = 25C, t = 5 s) (VI-O = 3000 VDC) (Note 12) II-O 1.0* A Withstand Insulation Test Voltage Resistance (Input to Output) Capacitance (Input to Output) (RH < 50%, TA = 25C) (Note 12) ( t = 1 min.) (VI-O = 500 V) (Note 12) (f = 1 MHz) (Note 12) VISO RI-O CI-O 2500 1012 0.6 VRMS pF ** All typical values are at VCC = 5 V, TA = 25C NOTES The VCC supply to each optoisolator must be bypassed by a 0.1F capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC and GND pins of each device. 2. Each channel. 3. Enable Input - No pull up resistor required as the device has an internal pull up resistor. 4. tPLH - Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse. 5. tPHL - Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse. 6. tr - Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse. 7. tf - Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse. 8. tELH - Enable input propagation delay is measured from the 1.5 V level on the HIGH to LOW transition of the input voltage pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse. 9. tEHL - Enable input propagation delay is measured from the 1.5 V level on the LOW to HIGH transition of the input voltage pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse. 10. CMH - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e., VOUT > 2.0 V). Measured in volts per microsecond (V/s). 11. CML - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low output state (i.e., VOUT < 0.8 V). Measured in volts per microsecond (V/s). 12. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together. 1. www.fairchildsemi.com 4 OF 11 7/9/01 DS300202 HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 TYPICAL PERFORMANCE CURVES Fig.1 Low Level Output Voltage vs. Ambient Temperature 0.8 0.7 Conditions: IF = 5 mA VE = 2 V VCC = 5.5V IOL = 12.8 mA 0.5 0.4 0.3 0.2 IOL = 9.6 mA 0.1 IOL = 6.4 mA 0.0 -40 -20 0 20 40 60 80 0.001 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 30 16 10 DUAL-CHANNEL HCPL-2630 HCPL-2631 Fig. 2 Input Diode Forward Voltage vs. Forward Current IOL = 16 mA VOL-Low Level Output Voltage (V) 0.6 IF = Forward Current (mA) 1 0.1 0.01 TA - Ambient Temperature (C) VF - Forward Voltage (V) Fig.3 Switching Time vs. Forward Current 120 50 Fig. 4 Low Level Output Current vs. Ambient Temperature IF = 15 mA VCC = 5 V 100 IOL - Low Level Output Current (mA) 45 IF = 10 mA 40 IF = 5 mA 35 TP - Propagation Delay (ns) 80 RL = 4 k 60 (TPLH) 40 30 20 RL = 350 0 5 7 9 (TPLH) RL = 1 k RL = 4 k (TPHL) RL = 350 k 11 RL = 1 k (TPLH) 25 Conditions: VCC = 5 V VE = 2 V VOL = 0.6 V 13 15 20 -40 -20 0 20 40 60 80 IF - Forward Current (mA) TA - Ambient Temperature (C) Fig. 5 Input Threshold Current vs. Ambient Temperature 4 Conditions: VCC = 5.0 V VO = 0.6 V Fig. 6 Output Voltage vs. Input Forward Current 6 RL = 350 5 RL = 350 IFT - Input Threshold Current (mA) VO - Output Voltage (V) 3 4 RL =4k 3 RL = 1k 2 2 1 RL = 1k RL = 4k 1 -40 -20 0 20 40 60 80 0 0 1 2 3 4 5 6 TA - Ambient Temperature (C) IF - Forward Current (mA) DS300202 7/9/01 5 OF 11 www.fairchildsemi.com HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DUAL-CHANNEL HCPL-2630 HCPL-2631 Fig. 7 Pulse Width Distortion vs. Temperature 80 600 Fig. 8 Rise and Fall Time vs. Temperature 500 PWD - Pulse Width Distortion (ns) Conditions: IF = 7.5 mA VCC = 5 V Tr/Tf - Rise and Fall Time (ns) 60 RL = 4 k 400 Conditions: IF = 7.5 mA VCC = 5 V RL = 4 k RL = 1 k (tr) RL = 350 (tr) 40 RL = 1 k RL = 350 20 300 200 (tr) 100 0 0 RL = 1 k RL = 4 k RL = 350 -40 -20 0 20 40 ] (tf) 60 80 100 -60 -40 -20 0 20 40 60 80 100 -60 TA - Temperature (C) TA - Temperature (C) Fig. 9 Enable Propagation Delay vs. Temperature 120 RL = 4 k 100 (TELH) 120 Fig. 10 Switching Time vs. Temperature 100 TE-Enable Propagation Delay (ns) 80 TP-Propagation Delay (ns) 80 RL = 4 k RL = 1 k 60 TPLH RL = 350 TPLH TPLH 60 RL = 1 k (TELH) RL = 350 (TELH) 40 20 RL = 350 RL = 1 k RL = 4 k -40 -20 0 20 40 60 40 0 -60 ] (TEHL) 80 100 20 -60 -40 -20 0 20 40 RL = 1 k RL = 4 k RL = 350 60 ] TPHL 80 100 TA-Temperature (C) TA-Temperature (C) Fig. 11 High Level Output Current vs. Temperature 20 Conditions: VCC = 5.5 V VO = 5.5 V VE = 2.0 V IF = 250 A IOH-High Level Output Current (A) 15 10 5 0 -60 -40 -20 0 20 40 60 80 100 TA-Temperature (C) www.fairchildsemi.com 6 OF 11 7/9/01 DS300202 HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DUAL-CHANNEL HCPL-2630 HCPL-2631 Pulse Generator tr = 5ns Z O = 50 +5V I F = 7.5 mA 1 2 Input Monitor (I F) 47 VCC 8 7 6 CL .1 f bypass RL Output (VO ) Input (I F) t PHL Output (VO ) tPLH I F = 3.75 mA 1.5 V 90% 10% tf tr 3 4 GND Output (VO ) 5 Fig. 12 Test Circuit and Waveforms for tPLH, tPHL, tr and tf. Pulse Generator tr = 5ns Z O = 50 Input Monitor (V E) +5V 3.0 V VCC 1 7.5 mA 8 7 6 CL RL Output (VO ) Input (VE ) t EHL tELH 1.5 V 2 3 4 .1 f bypass Output (VO ) 1.5 V GND 5 Fig. 13 Test Circuit tEHL and tELH. DS300202 7/9/01 7 OF 11 www.fairchildsemi.com HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DUAL-CHANNEL HCPL-2630 HCPL-2631 VCC 1 IF A B VFF 8 7 6 5 .1 f bypass 350 +5V 2 3 4 Output (VO) GND VCM Pulse Gen Peak VCM 0V 5V Switching Pos. (A), I F= 0 VO VO (Min) CM H VO (Max) Switching Pos. (B), I F 7.5 mA = CM L VO 0.5 V Fig. 14 Test Circuit Common Mode Transient Immunity www.fairchildsemi.com 8 OF 11 7/9/01 DS300202 HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 Package Dimensions (Through Hole) PIN 1 ID. 4 3 2 1 DUAL-CHANNEL HCPL-2630 HCPL-2631 Package Dimensions (Surface Mount) 0.390 (9.91) 0.370 (9.40) 4 3 2 1 PIN 1 ID. 0.270 (6.86) 0.250 (6.35) 5 6 7 8 0.270 (6.86) 0.250 (6.35) 0.390 (9.91) 0.370 (9.40) 5 6 7 8 SEATING PLANE 0.070 (1.78) 0.045 (1.14) 0.200 (5.08) 0.140 (3.55) 0.020 (0.51) MIN 0.070 (1.78) 0.045 (1.14) 0.020 (0.51) MIN 0.300 (7.62) TYP 0.016 (0.41) 0.008 (0.20) 0.154 (3.90) 0.120 (3.05) 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) TYP 0.016 (0.40) 0.008 (0.20) 15 MAX 0.300 (7.62) TYP 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) TYP Lead Coplanarity : 0.004 (0.10) MAX 0.045 [1.14] 0.315 (8.00) MIN 0.405 (10.30) MIN Package Dimensions (0.4"Lead Spacing) Recommended Pad Layout for Surface Mount Leadform 4 3 2 1 PIN 1 ID. 0.070 (1.78) 0.270 (6.86) 0.250 (6.35) 0.060 (1.52) 5 6 7 8 0.390 (9.91) 0.370 (9.40) 0.100 (2.54) 0.295 (7.49) 0.070 (1.78) 0.045 (1.14) SEATING PLANE 0.415 (10.54) 0.030 (0.76) 0.200 (5.08) 0.140 (3.55) 0.004 (0.10) MIN 0.154 (3.90) 0.120 (3.05) 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) TYP 0.016 (0.40) 0.008 (0.20) 0 to 15 0.400 (10.16) TYP NOTE All dimensions are in inches (millimeters) DS300202 7/9/01 9 OF 11 www.fairchildsemi.com HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DUAL-CHANNEL HCPL-2630 HCPL-2631 ORDERING INFORMATION Order Entry Identifier .S .SD .W Option S SD W Description Surface Mount Lead Bend Surface Mount; Tape and reel 0.4" Lead Spacing QT Carrier Tape Specifications ("D" Taping Orientation) 12.0 0.1 4.90 0.20 4.0 0.1 0.30 0.05 4.0 0.1 O1.55 0.05 1.75 0.10 7.5 0.1 13.2 0.2 16.0 0.3 10.30 0.20 0.1 MAX 10.30 0.20 O1.6 0.1 User Direction of Feed www.fairchildsemi.com 10 OF 11 7/9/01 DS300202 MARKING INFORMATION 1 2601 V 3 4 2 6 XX YY T1 5 Definitions 1 2 3 4 5 6 Fairchild logo Device number VDE mark (Note: Only appears on parts ordered with VDE option - See order entry table) Two digit year code, e.g., `03' Two digit work week ranging from `01' to `53' Assembly package code Reflow Profile 300 Temperature (C) 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3 225 C peak 215 C, 10-30 s Time above 183C, 60-150 sec Ramp up = 3C/sec 3.5 4 4.5 Time (Minute) * Peak reflow temperature: 225C (package surface temperature) * Time of temperature higher than 183C for 60-150 seconds * One time soldering reflow is recommended TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM FAST ActiveArrayTM FASTrTM BottomlessTM FPSTM CoolFETTM FRFETTM CROSSVOLTTM GlobalOptoisolatorTM DOMETM GTOTM EcoSPARKTM HiSeCTM E2CMOSTM I2CTM EnSignaTM i-LoTM FACTTM ImpliedDisconnectTM FACT Quiet SeriesTM ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC Across the board. Around the world.TM OPTOPLANARTM PACMANTM The Power Franchise POPTM Programmable Active DroopTM Power247TM PowerEdgeTM PowerSaverTM PowerTrench QFET QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SerDesTM SILENT SWITCHER SMART STARTTM SPMTM StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic TINYOPTOTM TruTranslationTM UHCTM UltraFET VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I13 |
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