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Semiconductor
NOT
October 1998
N FOR DED 3086 N MME ee HI S ECO R
E
ES WD
IGN
S
HI1866
6-Bit, 140 MSPS, Flash A/D Converter
Description
HI1866 is a 6-bit, high-speed, flash A/D converter capable of digitizing analog signals at the maximum rate of 140 MSPS. The digital input level is compatible with the ECL 100K/10KH/10K.
Features
* Ultra-High Speed Operation with Maximum Conversion Rate. . . . . . . . . . . . . . . . . . . . . . . 140 MSPS
[ /Title (HI1866) * Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . 7pF /Subject (6-Bit, 140 MSPS, Flash A/D Converter) * Wide Analog Input Bandwidth . . . . . . . . . . . . . 210MHz /Author () * Low Power Consumption . . . . . . . . . . . . . . . . . .325mW Ordering Information /Keywords (Harris Semiconductor, RGB, Video, Flat * Low Error Rate Panel, LCD) PART TEMP. NUMBER RANGE (oC) PACKAGE * Excellent Temperature Characteristics /Creator () * 1:2 Demultiplexed Output (TTL Level) /DOCINFO pdfmark HI1866JCQ -20 to 75 48 Ld MQFP
* Direct Replacement for Sony CXA1866
PKG. NO. Q48.12x12-S
[ /PageMode /UseOutlines Applications /DOCVIEW pdfmark
* LCD Panels * Magnetic Recording (PRML) * Communications (QPSK, QAM)
Pinout
HI1866 (MQFP) TOP VIEW
DGND1 DGND3 DVEE DGND2 DGND2 DVEE DVCC2 DVCC1 DVCC2 DGND1 DVCC1 DVCC2
DGND3 P2D0 (LSB) P2D1 P2D2 P2D3 P2D4 P2D5 (MSB) DGND3 DVCC2 NC DCLK NDCLK
1 2 3 4 5 6 7 8 9 10
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
DGND3 P1D5 (MSB) P1D4 P1D3 P1D2 P1D1 P1D0 (LSB) DGND3 DVCC2 INV CCLK NCCLK
26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24
VIN AGND
VRBS VRB
AGND
AVEE
VRT VRTS
NC
AVEE
NC
NC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1997
File Number
4108.2
4-1
HI1866 Functional Block Diagram
VRBS 15 VIN 19 VRTS 22
VRTS 16
REFERENCE RESISTANCE CHAIN
21 VRT
COMPARATOR
6-BIT LATCH 41 DVEE INV 27 CCLK 26 CD NCCLK 25 CLATCH A 20 AGND 46 DGND1 45 DGND2 42 DGND3 CLATCH B 6 DCLK 11 CD NDCLK 12 TTLOUT 6 47 DVCC1 48 DVCC2 6 23 AVEE
7 P2D5 (MSB)
6 P2D4
5 P2D3
4 P2D2
3 P2D1
2 P2D0 (LSB)
35 34 33 32 31 30 PD15 MSB) P1D4 P1D3 P1D2 P1D1 P1D0 (LSB)
CD: CLOCK DRIVER
4-2
HI1866 Pin Descriptions
PIN NO. 21 SYMBOL VRT I/O I TYPICAL VOLTAGE LEVEL 0V
VRT VRTS COMPARATOR 1
EQUIVALENT CIRCUIT
DESCRIPTION Top reference voltage input (= 0). This is the top reference voltage supplied to the internal resistance chain. The external input can be set in accordance with the peak value on the plus side of the input analog signal amplitude. VRT sense output. This is the voltage sense pin for VRT . Bottom reference voltage input (= -2V). This is the bottom reference voltage supplied to the internal resistance chain. The external input can be set in accordance with the peak value on the minus side of the input analog signal amplitude. VRB sense output. This is the voltage sense pin for VRB .
AGND
22 16
VRTS VRB
O I
0V -2V
COMPARATOR 2 COMPARATOR 31
COMPARATOR 32
15
VRBS
O
-2V
VRBS VRB
COMPARATOR 63
19
VIN
I
VRTS to VRBS
VIN
Analog input. The input range is 2VP-P .
AVEE
26 25
CCLK NCCLK
I I
ECL ECL
DGND1 R R 500 R R
CCLK clock input. This is the conversion clock, and is an ECL level input. CCLK inversion clock input. This is an ECL level input. When left open, this input goes to the ECL threshold potential (-1.3V). Only CCLK input can be used for operation with the NCCLK input left open, but complementary input is recommended to attain fast and stable operation. DCLK clock input. This is the 1:2 DMPX latch clock; input a clock of 1/2 frequency of CCLK. Data is output from DMPX port 1 and port 2 synchronously with the rising edge of this signal. This is an ECL level input. DCLK inversion clock input. This is an ECL level input. When left open, this input goes to the ECL threshold potential (-1.3V). Only DCLK input can be used for operation with the NDCLK input left open, but complementary input is recommended to attain fast and stable operation.
11
DCLK
I
ECL
CCLK (DCLK) NCCLK (NDCLK) 500
12
NDCLK
I
ECL
R DVEE R 1.3V
4-3
HI1866 Pin Descriptions
PIN NO. 27 SYMBOL INV (Continued) TYPICAL VOLTAGE LEVEL ECL
DGND1
I/O I
EQUIVALENT CIRCUIT
DESCRIPTION Digital output polarity inversion input. This is an ECL level input. This input inverts the polarity of the digital outputs P1D0 to P1D5, and P2D0 to P2D5. (Refer to the Output Code Table.) When left open, this signal is maintained at the low level.
R R 500 INV R
1.3V
R DVEE
1.3V
30 31 32 33 34 35 2 3 4 5 6 7 38, 47 9, 28, 37, 43, 48 39, 46 40, 45 1, 8, 29, 36, 42 17, 20
P1D0 P1D1 P1D2 P1D3 P1D4 P1D5 P2D0 P2D1 P2D2 P2D3 P2D4 P2D5 DVCC1 DVCC2
O
TTL
DVCC1 DVCC2
These pins are for the 6 bits of digital output data for DMPX port 1. P2D5 is the MSB, and P2D0 is the LSB. These are TTL levels outputs.
P1D0 TO D5 P2D0 TO D5 100K
These pins are for the 6 bits of digital output data for DMPX port 2. P2D5 is the MSB, and P2D0 is the LSB. These are TTL level outputs.
DGND2
DGND3
-
+5.0V +5.0V
+5V power supply for TTL level internal circuit. +5V power supply for TTL level output buffers (P1D0 to P2D5). Ground for DVEE digital circuit. Ground for DVCC1 digital circuit. Ground for DVCC2 digital circuit. Ground for AVEE analog circuit. Used as the ground for the comparator input buffers, latches, etc. Separated from DGND. -5.2V power supply for digital circuit. Connected internally with AVEE . (Resistance is 4 to 6.) -5.2V power supply for analog circuit. Connected internally with DVEE . (Resistance is 4 to 6.)
DGND1 DGND2 DGND3 AGND
-
0V 0V 0V 0V
41, 44
DVEE
-
-5.2V
14, 23
AVEE
-
-5.2V
4-4
HI1866
Absolute Maximum Ratings
Supply Voltage (AVEE , DVEE) . . . . . . . . . . . . . . . . . . . . -7V to 0.5V (DVCC) (Note 2). . . . . . . . . . . . . . . . . . . .0.5V to 7.0V Reference Voltage (VRT , VRB) . . . . . . . . . . . . . . . . . . . -2.7V to 0.5V (VRT - VRB). . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . -2.7V to 0.5V Digital Input Voltage (DIN) (Note 3) . . . . . . . . . . . . . . . -4.0V to 0.5V ( CCLK-NCCLK , DCLK-NDCLK ) . . . . 2.5V Digital Output Current (ID0 to ID6) . . . . . . . . . . . . . -30mA to +30mA Storage Temperature (TSTG) . . . . . . . . . . . . . . . . . . -65oC to 150oC Ambient Operating Temperature (TA) . . . . . . . . . . . . . -20oC to 75oC Allowable Power Dissipation (PD). . . . . . . . . . . . . . . . . . . . . 750mW
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range (TSTG) . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only)
Recommended Operating Conditions
Supply Voltage MIN TYP AVEE, DVEE . . . . . . . . . . . . . . . . . . . . . . . -5.5V -5.2V AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . .-0.05V 0V AGND - DGND (Note 4) . . . . . . . . . . . . . - 0.05V 0V DVCC (Note 5). . . . . . . . . . . . . . . . . . . . . . 4.75V 5.0V Temperature Range (TA) . . . . . . . . . . . . . . . -20oC MAX -4.75V 0.05V 0.05V 5.25V 75oC Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Input Voltage (VIN) . . . . . . . . . . . . . Digital Input Voltage, DIN (H) . . . . . . . . . . . DIN (L) CCLK, NCCLK Frequency (fCCLK)(MHz) . . DCLK, NDCLK Frequency (fDCLK)(MHz) . . CCLK, NCCLK Duty (DCCLK)(%) . . . . . . . . DCLK, NDCLK Duty (DDCLK)(%) . . . . . . . . CCLK-DCLK Time Difference (tDCD)(ns). . . . MIN TYP MAX -0.1V 0V 0.1V -2.2V -2.0V -0.8V VRB To VRT -1.1V -1.5V 140 70 40 50 60 40 50 60 -tPWL + 2 0 tPWH + 1
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. DVCC = DVCC1 , DVCC2 . 3. DIN = CCLK, NCCLK, DCLK, NDCLK, INV. 4. DGND = DGND1, DGND2, DGND3. 5. Refer to Timing Chart 1 for tPWL , tPWH .
Electrical Specifications
PARAMETER Resolution, n DC CHARACTERISTICS Integral Linearity Error Differential Linearity Error No Missing Code ANALOG INPUT Analog Input Capacitance Analog Input Resistance Input Bias Current REFERENCE INPUT Reference Resistance Reference Resistance Current Offset Voltage VRT VRB DIGITAL INPUT Logic High Level
TA = 25oC, AVEE = DVEE = -5.2V, DVCC = 5V, VRT = 0V, VRB = -2V SYMBOL n TEST CONDITIONS MIN TYP 6 MAX UNITS bits
EIL EDL
fC = 140MHz fC = 140MHz
-
Guaranteed
0.2 0.2 -
LSB LSB -
CIN RIN IIN
VIN = -1V_0.7VRMS , DC -2V VIN 0V -2V VIN 0V
200 -
7 -
110
pF K
RREF IREF EOT EOB
0 -
225 9 -
25 25
mA mV mV
VIH
-1.13
-
-
V
4-5
HI1866
Electrical Specifications
PARAMETER Logic Low Level Logic High Current Logic Low Current Input Capacitance SWITCHING CHARACTERISTICS Maximum Conversion Frequency Aperture Jitter Sampling Delay DIGITAL OUTPUT Logic High Level Logic Low Level Output Delay Output Rising Time Output Falling Time DYNAMIC CHARACTERISTICS Analog Amplitude Input Bandwidth FINB VIN = 2VP-P, Peak-to-Peak Value = 3dB Down Input Frequency fC = 140MHz, fIN = 1MHz fC = 140MHz, fIN = 35MHz fC = 140MHz, fIN = 70MHz fC = 140MHz, Error > 4 LSB 210 MHz VOH VOL tDO tr tf IOUT = -2mA IOUT = 1mA ZL = 25pF ZL = 25pF, 0.5V to 2.4V ZL = 25pF, 0.5V to 2.4V 2.7 2.0 1.2 1.2 0.5 8.0 V V ns ns ns fC tAJ tDS Error Rate 1E-9 TPS (Note 1) 140 5.0 1.0 MSPS ps ns TA = 25oC, AVEE = DVEE = -5.2V, DVCC = 5V, VRT = 0V, VRB = -2V (Continued) SYMBOL VIL IIH IIL VIH = -0.8V VIL = -1.6V TEST CONDITIONS MIN 0 -50 TYP 3.5 MAX -1.50 50 50 UNITS V A A pF
S/N Ratio
SNR1 SNR2 SNR3
-
36 34 32 -10-9
-
dB dB dB TPS (Note 1)
Error Rate POWER SUPPLY Supply Current Power Consumption NOTE: 1. TPS: Times Per Sample ICC IEE PD
-
-
DVCC = +5V AVEE = DVEE = -5.2V
-60 -
20 -40 325
32 -
mA mA mW
Output Code Table
DINV: 1 VIN 0V STEP 0 1 D5 D0 000000 000001 * * * -1V 31 32 011111 100000 * * * 62 -2V 63 NOTE: VRT = 0V, VRB = -2V. 111110 111111 INV:0 D5 D0 111111 111110 * * * 100000 011111 * * * 000001 000000
4-6
HI1866 Timing Diagrams
tDS VIN N-1 N N+1 N+2 N+3 N+4 tr tf -1.1V CCLK -1.5V -1.3V DCCLK
tPWH
tPWL
NCCLK tDCD tf tr -1.1V -1.5V DDCLK
-1.3V
DCLK
-1.3V
NDCLK tDO tDO P1D0-5 2.0V 1.0V N-4 N-2 N
-1.3V
P2D0-5
2.0V 1.0V N-3 N-1 N+1
FIGURE 1. TIMING CHART 1
4-7
HI1866 Timing Diagrams
(Continued)
6 VIN COMPARATOR 6-BIT LATCH CLATCHA
6 CLATCHB
6
6 CCLK TTLOUT P1D0 TO D5
DCLK 6 TTLOUT 6 P2D0 TO D5
N-1 VIN
N
N+1
N+2
N+3
N+4
N+5
CCLK
COMPARATOR (MASTER)
N - 1q
N
N+1
N+2
N+3
N+4
N+5
COMPARATOR (SLAVE)
N-1
q
N
N+1
N+2
N+3
N+4
N+5
6-BIT LATCH
N-2
N-1
q
N
N+1
N+2
N+3
N+4
CLATCHA
N-3
N-2
N-1
q
N
N+1
N+2
N+3
CLATCHB
N-4
N-3
N-2
N-1
N
N+1
N+2
DCLK
TTLOUT (P2D0 TO D5)
N-3
N-1
N+1
TTLOUT (P1D0 TO D5)
N-4
N-2
N
FIGURE 2. TIMING CHART 2
4-8
HI1866 Test Circuits
VIN 6 6 A LATCH B
SIGNAL SOURCE fCLK 4 -1kHz
DUT HI1866 CCLK
COMPARATOR A>B
PULSE COUNTER
DCLK
+
LATCH
2VP-P SIN WAVE DATA 4 SIGNAL SOURCE fCLK AMP
1/ 2
FIGURE 3. MAXIMUM CONVERSION RATE TEST CIRCUIT
+V
S1 +
-
S1: NON WHEN A< B S2: ON WHEN A > B
S2
-V
(P1D0 TO D5) 6 VIN DUT HI1866 AB 6 SW COMPARATOR B6 A6 6 TO TO (P2D0 TO D5) B1 A1 B0 A0 "0" "1" BUFFER
CCLK DCLK 6 DVM CONTROLLER
000000 TO 111110
FIGURE 4. INTEGRAL/DIFFERENTIAL LINEARITY ERROR TEST CIRCUIT
4-9
HI1866 Test Circuits
(Continued)
36 35 34 33 32 31 30 29 28 27 26 25 DGND3 DGND3 NCCLK DVCC2 CCLK P1D5 P1D4 P1D3 P1D2 P1D1 P1D0 INV
24
37 DVCC2 38 DVCC1 39 DGND1 40 DGND2 41 DVEE 42 DGND3 HI1866 43 DVCC2 44 DVEE 45 DGND2 46 DGND1 47 DVCC1 48 DVCC2 DGND3 DGND3 NDCLK DVCC2 DCLK P2D0 P2D1 P2D2 P2D3 P2D4 P2D5
AVEE 23 VRTS 22 VRT 21 AGND 20 VIN 19 18 AGND 17 VRB 16 VRBS 15 AVEE 14 13 -2.0V IIN A -1.0V
1
2
3
4
5
6
7
8
9 10 11 12
ICC A +5.0V
IEE A -5.2V
FIGURE 5. CURRENT CONSUMPTION/ANALOG INPUT BIAS TEST CIRCUIT
6 SIGNAL SOURCE 1 : VARIABLE VIN HI1866 6 CCLK FREQUENCY LOCK DCLK SW 1024 SAMPLES LOGIC ANALYZER
SIGNAL SOURCE 2 ECL BUFFER
FIGURE 6. SAMPLING DELAY/APERTURE JITTER TEST CIRCUIT
4-10
HI1866 Typical Performance Curves
-30 CURRENT CONSUMPTION (mA) VEE = -5.2V, VCC = +5V -35 22.5 25.0 CURRENT CONSUMPTION (mA) 3.6 VEE = -5.2, VCC = 5V, IOUT = -2mA DIGITAL OUTPUT LEVEL (V) 3.5
ICC
3.4
-40 IEE -45
20.0
3.3
17.5
3.2
-50 -25
0
25
50
15.0 75
AMBIENT TEMPERATURE (oC)
3.1 -25
0
25
50
75
AMBIENT TEMPERATURE (oC)
FIGURE 7. CURRENT CONSUMPTION vs AMBIENT TEMPERATURE
FIGURE 8. VOH vs AMBIENT TEMPERATURE
0.40 VEE = -5.2V, VCC = 5V, IOUT = 1mA
38 36
DIGITAL OUTPUT LEVEL (V)
0.38 34 SNR (dB) 0.36 32 30 28 26 0.32 24 CCLK = 140MHz, DCLK = 70MHz 0.30 -25 22 0 25 50 75 AMBIENT TEMPERATURE (oC) 1 10 INPUT FREQUENCY (MHz) 100
0.34
FIGURE 9. VOL vs AMBIENT TEMPERATURE
FIGURE 10. SNR vs INPUT FREQUENCY
6.5 2ND, 3RD HARMONIC DISTORTION (dB) CCLK = 140MHz, DCLK = 70MHz EFFECTIVE BIT NUMBER (BITS) 6.0 5.5 5.0 4.5 4.0
-20 CCLK = 140MHz, DCLK = 70MHz -30
-40 3ND HARMONIC DISTORTION (dB) -50
-60 2ND HARMONIC DISTORTION (dB) -70 1 10 INPUT FREQUENCY (MHz) 100
3.5
1
10 INPUT FREQUENCY (MHz)
100
FIGURE 11. EFFECTIVE BIT NUMBER vs INPUT FREQUENCY
FIGURE 12. 2ND, 3RD HARMONIC DISTORTION vs INPUT FREQUENCY
4-11
HI1866 Notes on Operation
The HI1186 is a high speed A/D converter with ECL level logic input and demultiplexed TT level output. Take notice of the following to ensure optimum performance from this IC. Power Supply and Grounding Grounding has a profound influence on converter performance. The higher the frequency is, the more important the way of grounding becomes. The ground pattern should be as large as possible. It is recommended to make the power supply and ground patterns wider at an inner layer using the multi-layer board. To prevent interference between the AGND and DGND patterns and between the AVEE and DVEE lines, make sure the respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVEE and DVEE lines at one point each via a ferrite-bead filter. Shorting analog and digital ground patterns in one place immediately under the A/D converter improves A/D converter performance. Ground the power supply pins (AVEE , DVEE , DVCC) as close to each pin as possible with a 0.1F or larger ceramic chip capacitor. (Connect the AVEE pin to the AGND pattern, DVEE to DGND, and DVCC to DGND.) Analog Input Make the connection between the VIN pin and the analog input source as short as possible. There is a slight offset voltage at reference voltage pins VRT and VRB . If it presents no problem in the application, the voltage can be applied directly. However, if the reference voltage is to be set precisely, apply it via a feedback circuit created, using the VRTS and VRBS pins. Make adequate bypass for high frequency noise at VRT and VRB . The VRT pin is normally connected to AGND on the board. Bypass the VRB pin to the AGND pattern with a 0.1F or larger ceramic chip capacitor as short as possible. The 10F tantalum capacitor connected to VRB in the Application Circuit is to stop oscillation in the reference voltage generation circuit. Digital Input Noise at the INV pin may cause misoperation of which the cause is extremely hard to identify. If it is okay for the set voltage level to be low only, leave the pin open. If a high level voltage has to be input, bypass the INV pin to DGND with an about 0.1F ceramic chip capacitor as short as possible. It is recommended that high level input voltage is about -0.5V to 1.0V, and low level input voltage is about -1.6V to -2.5V. When inputting a high level voltage, avoid connecting directly to DGND. The HI1186 has input pins for two clocks: CCLK and DCLK. For CCLK, which is used for the internal comparator, input an ECL level clock with up to the maximum conversion frequency. For DCLK, which is used for the multiplex output, input an ECL level clock with a rate half that of CCLK. Take notice of the timing between CCLK and DCLK. It is recommended that differential signals be input to the clock input pins CCLK, NCCLK, DCLK and NDCLK. The A/D converter can be driven only by the clock input pins CCLK and DCLK, but there is a risk of unstable characteristics at maximum speeds. If the NCCLK and NDCLK pins are not used, bypass these pins to DGND with an about 0.1F capacitor. In this time, about -1.3V voltage is generated at the NCCLK and NDCLK pins. However, this is too weak to be used as threshold voltage VBB ; it can not directly drive even one ECL input load. The clock duty cycle is designed for use at 50%. Any diversion from this percentage will have a slight effect on the maximum performance of the A/D converter, but there is no great need for adjustment. Digital Output P1D0 (LSB) to P1D5 (MSB), and P2D0 (LSB) to P2D5 (MSB) are demultiplex digital outputs (2 systems), and are output using the DCLK timing. The polarity of the output data can be inverted using the INV signal.
4-12
HI1866 Typical Application Circuit
DGND 48 47 46 45 44 43 42 41 40 39 38 37 DGND1 DGND2 DGND3 DGND2 DGND1 DVCC2 DVCC1 DVCC2 DVCC1 DVCC2 DVEE DVEE
DGND3 36 1 DGND3 (TTL) P2D0 (TTL) P2D1 (TTL) P2D2 (TTL) P2D3 (TTL) P2D4 (TTL) P2D5 2 P2D0 3 P2D1 4 P2D2 5 P2D3 6 P2D4 HI1866 7 P2D5 8 DGND3 9 DVCC2 10 11 DCLK 12 NCLK NCCLK 25 AGND AVEE AGND VRBS AVEE VRTS VRB VRT VIN P1D0 30 DGND3 29 DVCC2 28 INV 27 CCLK 26 INV (ECL LEVEL) P1D5 35 P1D4 34 P1D3 33 P1D2 32 P1D1 31 P1D5 (TTL) P1D4 (TTL) P1D3 (TTL) P1D2 (TTL) P1D1 (TTL) P1D0 (TTL)
13 14 15 16 17 18 19 20 21 22 23 24
ONE POINT SHORTING
-5.2V
+5.0V
10F TANTALUM CAPACITOR
AGND
-
+
VRTS
VRB
-5.2V
1/ CLK 2
CAPACITORS, IF NOT SPECIFIED, ARE 0.1F CERAMIC CHIP CAPACITORS.
ANALOG INPUT
ECL BUFFER CLK (ECL LEVEL)
4-13

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