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| HV739 High Speed 100V 3.0A Ultrasound Pulser Features HVCMOS technology for high performance High density integration ultrasound transmitter Bipolar 100V or unipolar 0 to 200V output voltage 3A source and sink peak current Up to 10MHz operation frequency Matched delay times 1.8V to 5.0V CMOS logic interface Over temperature sensing Under voltage protections General Description The Supertex HV739 is a single channel monolithic 200V 3.0A high-speed pulser. It is designed for NDT and medical ultrasound applications. This high voltage and high-current integrated circuit can also be used for other piezoelectric, capacitive or MEMS sensor in ultrasonic transducer and sonar ranger applications. HV739 consists of controller logic interface circuit, voltage level translators, MOSFET gate drives and high current power P-channel and N-channel power MOSFETs as the output stage. The output stage of HV739 is designed to provide output peak currents over 3.3A with up to 200V swing. The P- and Nchannel power FETs gate drivers are supplied by two floating 10 to 12VDC power supplies referenced to VPP and VNN. This direct coupling topology of the gate drivers not only saves two high voltage capacitors per channel, but also makes the PCB layout easier. Applications NDT ultrasound equipment Piezoelectric transducer drivers Sonar, ranger and flow metering Typical Application Circuit +1.8~5V C1 VLL VDD +12V C2 C3 VSUB +100V +88V C4 VPF VPP +100V C5 HV739 EN PIN EN_PWR SUB VPP +1.8 to 5.0V Logic Input Level Translator P-Driver TXP D1 HVOUT1 NIN OTP Level Translator N-Driver VNN TXN D2 X1 R1 Over Temp. GREF VSS VNF C7 -88V VNN C6 -100V HV739 Ordering Information Package Options Device 32-Lead QFN 5x5mm body, 1.0mm height (max), 0.5mm pitch HV739K6-G HV739 -G indicates package is RoHS compliant (`Green') Absolute Maximum Ratings Parameter VSS, Power supply reference VLL, Positive logic supply VDD, Positive logic and level translator supply (VPP -VPF) Positive floating gate drive supply (VNF- VNN) Negative gate floating drive supply (VPP-VNN) Differential high voltage supply VPP, High voltage positive supply VNN, High voltage negative supply All logic input PIN, NIN and EN pin voltages Open drain output OPT pin voltage (VSUB - VPP) Substrate to VPP voltage difference (VPP -TXPX) VPP to TXPX voltage difference (VSUB- TXPX) Substrate to TXPX voltage difference (TXNX-VNN ) TXNX to VNN voltage difference Storage temperature Thermal resistance, JA (4-layer,1oz, 4x3in. 9-via PCB) Value 0V -0.5V to +7V Pin Configuration VSUB VSUB VPP VPP VPP VPF NC NC 1 VDD TXP TXP TXP NC NC TXN TXN TXN VLL GREF EN -0.5V to +14V -0.5V to +14V -0.5V to +14V -0.5V to +220V -0.5V to +220V -220V to +0.5V PIN NIN OTP VSS VNF NC VSUB VNN VNN VNN NC -0.5V to +14V +220V +220V +220V +220V -65C to 150C 25C/W 32-Lead QFN (top view) Package Marking HV739 LLLLLL YYWW AAACCC L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = "Green" Packaging Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. 32-Lead QFN Power-Up Sequence 1 2 3 4 5 6 VSUB VLL with logic signal low VDD VPF and VNF VPP and VNN Logic control signals Power-Down Sequence 1 2 3 4 5 6 All logic signals go to low VPP and VNN VPF and VNF VDD VLL VSUB 2 VSUB -0.5V to +7V HV739 Operating Supply Voltages and Current (4 Channel Active) (Operating conditions, unless otherwise specified, VSS = 0V,VLL = +3.3V, VDD = +12V, VPP-VPF = +12V, VNN-VNF = -12V, VPP = +100V, VNN = -100V, TA = 25C) Sym VLL VDD VPF VNF VSUB VPP VNN ILL IDDQ IDDEN IPPQ IPPEN INNQ INNEN IPFQ IPFEN INFQ INFEN Parameter Logic voltage reference Internal voltage supply Positive gate driver supply Negative gate drive supply IC substrate voltage Positive HV supply Negative HV supply VLL Current EN = Low VDD Current EN = Low VDD Current EN = High VDD Current at 5.0MHz VPP Current EN = Low VPP Current at 5.0MHz VNN Current EN = Low VNN Current at 5.0MHz VPF Current EN = Low VPF Current at 5.0MHz VNF Current EN = Low VNF Current at 5.0MHz Min 1.8 10 (VPP-12) (VNN+10) VDD 0 -220 0.1 - Typ 3.3 12 VPP 100 0.3 0.5 1.0 5.6 1.0 5.6 10 12.2 10 6.4 Max 5.0 12.5 (VPP-10) (VNN+12) +220 +220 0 250 0.7 5.0 5.0 20 20 - Units Conditions V V V V V V V A A mA mA A mA A mA A mA A mA ----Floating driver voltage supplies. Must connect to the most positive potential of the IC. --------f = 0MHz f = 5.0MHz, no loads --f = 5.0MHz, no loads --f = 5.0MHz, no loads --f = 5.0MHz, no loads --f = 5.0MHz, no loads DC Electrical Characteristics (Operating conditions, unless otherwise specified, VSS= 0V,VLL= +3.3V, VDD= +12V, VPP-VPF = +12V, VNN-VNF= -12V, VPP = +100V, VNN = -100V,TA= 25C) Output P-Channel MOSFET, TXP Sym IOUT RON COSS Parameter Output saturation current Channel resistance Output capacitance Min 3.0 Typ 3.3 6.9 87 Max Units Conditions A pF 1.0 load to ground, VDS= 12V ISD = 500mA VDS = 25V, f = 1.0MHz Output N-Channel MOSFET, TXN Sym IOUT RON COSS Parameter Output saturation current Channel resistance Output capacitance Min 3.0 Typ 3.3 7.0 87 Max Units Conditions A pF 1.0 load to ground, VDS= 12V ISD = 500mA VDS = 25V, f = 1.0MHz Logic Inputs Sym VIH VIL IIH IIL CIN Parameter Input logic high voltage Input logic low voltage Input logic high current Input logic low current Input logic capacitance Min 0.8VLL 0 -10 Typ 3 Max VLL 0.2VLL 10 5.0 Units Conditions V V A A pF ----------- HV739 AC Electrical Characteristics (Operating conditions, unless otherwise specified, VSS= 0V, VLL= +3.3V, VDD= +12V, VPP-VPF = +12V, VNN-VNF= -12V, VPP = +100V, VNN =-100V,TA= 25C) Sym fOUT HD2 tEN tDIS tdrp tdfp tdrn tdfn tr tf Parameter Output frequency range Second harmonic distortion Power enable time Power disable time Delay time on rise time P-ch Delay time on fall time P-ch Delay time on rise time N-ch Delay time on fall time N-ch Output rise time Output fall time Min - Typ -35 70 1.0 15 15 18 18 50 50 Max 35 250 10 35 35 35 35 65 65 Units Conditions MHz dB s s ns ns ns ns ns ns 220pF//1.0k load 100 resistor load Switching Time Diagram NINx 50% PINx tdr 90% 50% tdf VPP Output 10% tr tf 0 10% VNN 90% Truth Table Logic Inputs EN 1 1 1 1 0 PIN 0 1 0 1 X NIN 0 0 1 1 X TXP OFF ON OFF ON* OFF Output TXN OFF OFF ON ON* OFF *Note: Not allowed, may damage IC 4 HV739 +200V Unipolar Pulser +1.8~5V C1 VLL VDD +12V C2 C3 VSUB +200V +188V C4 VPF VPP +200V C5 HV739 SUB EN PIN EN_PWR VPP +1.8 to 5.0V Logic Input Level Translator P-Driver TXP HVOUT1 NIN OTP Level Translator N-Driver VNN TXN X1 Over Temp. GREF VSS VNF C7 +12V VNN -200V Unipolar Pulser +1.8~5.0V +12V C1 VLL VDD C2 C3 VSUB +12V -12V C4 VPF VPP HV739 EN PIN EN_PWR SUB VPP +1.8 to 5.0V Logic Input Level Translator P-Driver TXP HVOUT1 NIN OTP Level Translator N-Driver VNN TXN X1 Over Temp. GREF VSS VNF C7 -188V VNN C6 -200V 5 HV739 Pin Description Name VSS VDD VLL GREF VPP VNN VPF VNF TXP TXN PIN NIN EN OTP NC VSUB (Pad) Function Power supply return (0V) Positive internal voltage supply (+12V). Logic voltage high reference input (+3.3V). Logic voltage low reference. Logic ground (0V). Positive high voltage power supply (+100V). Negative high voltage power supply (-100V). P-FET gate driver floating power supply, (VPP- VPF) = +12V. N-FET gate driver floating power supply, (VNF- VNN) = +12V. Output P-FET drain (open drain output). Output N-FET drain (open drain output). Input logic control of high voltage output P-FET, Hi = on, Low = off. Input logic control of high voltage output N-FET, Hi = on, Low = off. Chip power enable Hi = on, Low=off. Open drain output for over temperature protection, Low = over temp. No connection Substrate is internally connected to the central thermal pad on the bottom of package. It must be connected to the most positive potential of the IC externally. 6 HV739 32-Lead QFN Package Outline (K6) 5x5mm body, 1.0mm height (max), 0.50mm pitch 32 D D2 32 Note 1 (Index Area D/2 x E/2) 1 Note 1 (Index Area D/2 x E/2) E b e 1 E2 View B Top View Bottom View Note 3 A A1 A3 Seating Plane L1 Note 2 L Side View View B Notes: 1. Details of Pin 1 identifier are optional, but must be located within the indicated area. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol MIN Dimension (mm) NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 A3 0.20 REF b 0.18 0.25 0.30 D 4.85 5.00 5.15 D2 3.20 3.70 E 4.85 5.00 5.15 E2 3.20 3.70 e 0.50 BSC L 0.30 0.40 0.50 L1 0.00 0.15 0O 14O JEDEC Registration MO-220, Variation VHHD-5, Issue K, June 2006. Drawings not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV748 NR081007 7 |
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