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HY51V(S)17403HG/HGL
4M x 4Bit EDO DRAM
PRELIMINARY
DESCRIPTION
The HY51V(S)17403HG/HGL is the new generation dynamic RAM organized 4,194,304 words x 4bit. HY51V(S)17403HG/HGL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The HY51V(S)17403HG/HGL offers Extended Data Out PageMode as a high speed access mode. Multiplexed address inputs permit the HY51V(S)17403HG/HGL to be packaged in standard 300mil 24(26)pin SOJ and 24(26) pin TSOP-II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. System oriented features include single power supply 3.3V +/- 0.3V tolerance, direct interfacing capability with high performance logic families such as Schottky TTL.
FEATURES
* * * * * Extended Data Out Mode capability Read-modify-write capability Multi-bit parallel test capability TTL(3.3V) compatible inputs and outputs /RAS only, CAS-before-/RAS, Hidden and self refresh(L-version) capability Fast access time and cycle time
Part No HY51V(S)17403HG/HGL-5 HY51V(S)17403HG/HGL-6 HY51V(S)17403HG/HGL-7 tRAC 50ns 60ns 70ns
* * * *
JEDEC standard pinout 24(26)pin plastic SOJ / 24(26)pin TSOP-II Single power supply of 3.3V +/- 0.3V Battery back up operation(L-version)
*
tCAC 13ns 15ns 18ns
tRC 84ns 104ns 124ns
tHPC 20ns 25ns 30ns
*
Power dissipation
50ns Active Standby 432mW 60ns 369mW 70ns 360mW
*
Refresh cycle
Part No HY51V17403HG HY51V17403HGL Ref 2K 2K Normal 32ms 128ms L-part
7.2mW(CMOS level Max) 0.36mW (L-version : Max)
ORDERING INFORMATION
Part Number HY51V(S)17403HGJ/HG(L)J-5 HY51V(S)17403HGJ/HG(L)J-6 HY51V(S)17403HGJ/HG(L)J-7 HY51V(S)17403HGT/HG(L)T-5 HY51V(S)17403HGT/HG(L)T-6 HY51V(S)17403HGT/HG(L)T-7
(S) : Self refresh, (L) : Low power
Access Time 50ns 60ns 70ns 50ns 60ns 70ns
Package
300mil 24(26)pin SOJ
300mil 24(26)pin TSOP-II
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.0.1/Apr.01
HY51V(S)17403HG/HGL
PIN CONFIGURATION
VCC I/O1 I/O2 WE RAS A11 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6
26 25 24 23 22 21
VSS I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 VSS
VCC I/O1 I/O2 WE RAS A11 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6
26 25 24 23 22 21
VSS I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 VSS
8 9 10 11 12 13
19 18 17 16 15 14
8 9 10 11 12 13
19 18 17 16 15 14
24(26) Pin Plastic SOJ
24(26) Pin Plastic TSOP-II
PIN DESCRIPTION
Pin /RAS /CAS /WE /OE A0-A11 A0-A11 I/O 1- I/O 4 Vcc Vss NC Function Row Address Strobe Column Address Strobe Write Enable Output Enable Address Inputs Refresh Address Inputs Data Input / Output Power (3.3V) Ground No connection
Rev.0.1/Apr.01
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HY51V(S)17403HG/HGL
ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to Vss Voltage on Vcc relative to Vss Short Circuit Output Current Power Dissipation Symbol TA TSTG VT Vcc IOUT PT Rating 0 ~ 70 -55 ~ 125 -0.5 ~ Vcc + 0.5 (Max 4.6V) -0.5 ~ 4.6 50 1 Unit
o o
C C
V V mA W
Recommended DC OPERATING CONDITIONS (TA=0 to 70 oC)
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol Vcc VIH VIL Min 3.0 2.0 -0.3 Typ. 3.3 Max 3.6 Vcc + 0.3 0.8 Unit V V V Note
Note : All voltages are referenced to Vss
Rev.0.1/Apr.01
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HY51V(S)17403HG/HGL
DC CHARACTERISTICS (Vcc = 3.3V +/- 10%, TA=0 to 70C)
Symbol VOH Output Level Output Level voltage(Iout= -2mA) Output Level Output Level voltage(Iout=2mA)
50ns ICC1
Parameter
Min
2.4
Max
Vcc
Unit
V
Note
VOL
0 -
0.4 100 90 80
V
Operating current Average power supply operating current ( /RAS, /CAS Cycling : tRC = tRC min) Standby current (TTL interface) Power supply standby current (/RAS, /CAS=VIH, Dout = High-Z) /RAS only refresh current Average power supply current /RAS only refresh mode (tRC= tRC min)
60ns 70ns
mA
1, 2
ICC2
-
2
mA
50ns 60ns 70ns 50ns
-
100 90 80 90 80 75 1 100 100 90 80 300 uA 4 mA mA uA 4 mA 1, 3 mA 2
ICC3
ICC4
Fast page mode current Average power supply current Fast page mode (tPC=tPC min) CMOS interface ( /RAS, /CAS >= Vcc-0.2V, Dout = High-Z)
60ns 70ns
ICC5 Standby current ( L-version)
50ns ICC6
-
/CAS-before-/RAS refresh current (tRC=tRC min)
60ns 70ns
ICC7
Battery back up operating current (standby with CBR refresh) (tRC=31.3us, tRAS<=0.3us, Dout=High-Z) Standby current ( /RAS = VIH, /CAS = VIL, Dout=Enable) Self refresh current (/RAS, /CAS <=0.2V, Dout=High-Z, CMOS interface) Input leakage current, Any input (0V<= Vin<=4.6V) Output leakage current, (Dout is disabled, 0V<= Vout<=4.6V)
ICC8
-
5
uA
1
ICC9 II(L) IO(L)
-10 -10
200 10 10
uA uA uA
4
Note : 1. Icc depends on output load condition when the device is selected, Icc(max) is specified at the output open condition 2. Address can be changed once or less while /RAS=VIL 3. Address can be changed once or less while /CAS=VIH 4. /CAS = L (<=0.2) while /RAS=L (<=0.2) 5. L-Version
Rev.0.1/Apr.01
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HY51V(S)17403HG/HGL
CAPACITANCE (Vcc=3.3V +/-10%, TA=25C)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Min. Max 5 7 7 Unit pF pF pF Note 1 1 1, 2
Note : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. /CAS = VIH to disable Dout
AC CHARACTERISTICS
Test Condition * *
(Vcc=3.3V +/-10%, TA=0~70C, Note 1, 2, 18)
*
Input rise and fall times = 2ns Input levels : VIL=0V, VIH=3V Input timing reference level : VIL/VIH = 0.8/2.0V
* *
Output timing reference level : VOL/VOH=0.8/0.2V Output load : 1 TTL gate + CL (100pF) ( including scope and jig )
Read, Write, Read-modify-Write and Refresh Cycle
-50 Parameter Random read or write cycle time /RAS precharge time /CAS precharge time /RAS pulse width /CAS pulse width Row address set-up time Row address hold time Column address set-up time Column address hold time /RAS to /CAS delay time /RAS to Column address delay time /RAS hold time /CAS hold time /CAS to /RAS precharge time Symbol Min tRC tRP tCP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP 84 30 8 50 8 0 8 0 8 12 10 10 35 5 Max 10,000 10,000 37 25 Min 104 40 10 60 10 0 10 0 10 14 12 13 40 5 Max 10,000 10,000 45 30 Min 124 50 13 70 13 0 10 0 13 14 12 13 45 5 Max 10,000 10,000 52 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3 4
-60
-70
Unit Note
Rev.0.1/Apr.01
5
HY51V(S)17403HG/HGL
- continued -50 Parameter /OE to Din delay time /OE delay time from Din /CAS delay time from Din Transition time ( Rise and Fall) Refresh period tREF Refresh period (L-version) 128 128 128 ms 2K Ref. Symbol Min tODD tDZO tDZC tT 13 0 0 2 Max 50 32 Min 15 0 0 2 Max 50 32 Min 18 0 0 2 Max 50 32 ns ns ns ns ms 5 6 6 7 2K Ref. -60 -70
Unit Note
Read Cycle
-50 Parameter Access time from /RAS Access time from /CAS Symbol Min tRAC tCAC Max 50 13 Min Max 60 15 Min Max 70 18 ns ns 8,9,19 9,10, 17,19 9,11, 17,19 9 -60 -70
Unit Note
Access time from column address Access time from /OE Read command set-up time Read command hold time to /CAS Read command hold time from /RAS Read command hold time to /RAS Column address to /RAS lead time Column address to /CAS lead time /CAS to output in low-Z Output data hold time Output data hold time from /OE Output buffer turn off time to /OE Output buffer turn off time /CAS to Din delay time Output data hold time from /RAS Output buffer turn-off time to /RAS Output buffer turn off time to /WE /WE to DIN delay time /RAS to DIN delay time Rev.0.1/Apr.01
tAA tOAC tRCS
tRCH
0 0 50 5 25 15 0 3 3 13 3 13 13
25 13 13 13 13 13 -
0 0 60 5 30 18 0 3 3 15 3 15 15
30 15 15 15 15 15 -
0 0 70 5 35 23 0 3 3 18 3 18 18
35 18 15 15 15 15 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
12
tRCHR tRRH tRAL tCAL
tCLZ
12
tOH
tOHO
tOEZ tOFF
tCDD
13 13 5
tOHR
tOFR
tWEZ tWDD
tRDD
6
HY51V(S)17403HG/HGL
Write Cycle
-50 Parameter Write command set-up time Write command hold time Write command pulse width Write command to /RAS lead time Write command to /CAS lead time Data-in set-up time Data-in hold time Symbol Min tWCS tWCH tWP tRWL tCWL
tDS tDH
-60 Max Min 0 10 10 10 10 0 10 Max Min 0 13 10 13 13 0 13
-70
Unit Note
Max ns ns ns ns ns ns ns 15 15 14
0 8 8 8 8 0 8
Read-Modify-Write Cycle
-50 Parameter Read-modify-write cycle time /RAS to /WE delay time /CAS to /WE delay time Column address to /WE delay time /OE hold time from /WE Symbol Min tRWC tRWD tCWD tAWD tOEH 111 67 30 42 13 Max Min 136 79 34 49 15 Max Min 161 92 40 57 18 Max ns ns ns ns ns 14 14 14 -60 -70
Unit Note
Refresh cycle
-50 Parameter /CAS set-up time ( /CAS-before-/RAS Refresh Cycle) /CAS hold time ( /CAS-before-/RAS Refresh Cycle) /WE setup time ( /CAS-before-/RAS Refresh Cycle) /WE hold time ( /CAS-before-/RAS Refresh Cycle) /RAS precharge to /CAS hold time ( /CAS-before-/RAS Refresh Cycle) Symbol Min tCSR 5 Max Min 5 Max Min 5 Max ns -60 -70
Unit Note
tCHR
8
-
10
-
10
-
ns
tWRP
0
-
0
-
0
-
ns
tWRH
10
-
10
-
10
-
ns
tRPC
5
-
5
-
5
-
ns
Rev.0.1/Apr.01
7
HY51V(S)17403HG/HGL
EDO Page Mode Cycle
-50 Parameter EDO mode cyle time EDO mode /RAS pulse width Access time from /CAS precharge /RAS hold time from /CAS precharge Output data hold time from /CAS low /CAS hold time referred /OE /CAS to /OE setup time Read command hold time from /CAS precharge Symbol Min tHPC tRASP
tACP tRHCP
-60 Max 100K 30 Min 25 35 3 10 5 35 Max 100K 35 Min 30 40 3 13 5 40
-70
Unit Note
Max 100K 40 ns ns ns ns ns ns ns ns 9 20 16 9,17,19
20 30 3 8 5 30
tDOH tCOL
tCOP tRHCP
EDO Page Mode Read-Modify-Write Cycle
-50 Parameter EDO Page read-modify-write cycle time EDO mode read-modify-write cycle /CAS precharge to /WE delay time Symbol Min tHPRWC
tCPW
-60 Max Min 68 54 Max Min 79 62
-70
Unit Note
Max ns ns 14
57 45
TEST Mode cycle
-50 Parameter Test mode /WE setup time Test mode /WE hold time Symbol Min tWTS
tWTH
-60 Max Min 0 10 Max Min 0 10
-70
Unit Note
Max ns ns
0 10
Self Refresh Mode(L-version)
-50 Parameter /RAS pulse width (self refresh) /RAS precharge time(self refresh) /CAS hold time(self refresh) Symbol Min tRASS
tRPS tCHS
-60 Max Min 100 110 -50 Max Min 100 130 -50
-70
Unit Note
Max us ns ns
100 90 -50
Rev.0.1/Apr.01
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HY51V(S)17403HG/HGL
Notes :
1. AC measurements assume tT = 2ns 2. AC initial pause of 200us is required after power up followed by a minimum of eight initialization cycles ( any combination of cycles containing /RAS-only refresh or /CAS-before-/RAS refresh) If the internal refresh counter is used, a minimum of eight /CAS-before-/RAS refresh cycle are required. 3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only : if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a reference point only : if tRAD is greater than the specified tRAD(max) limit, then access time is controlled exclusively by tAA. 5. Either tODD or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals, also transition times are measured between VIH(min) and VIL(max) 8. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown 9. Measured with a load circuit equivalent to 1 TTL loads and 100pF.( VOH=2.0V, VOL=0.8V) 10. Assumes that tRCD>=tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max) 11. Assumes that tRAD>=tRAD(max) and tRCD + tCAC(max) <= tRAD + tAA(max) 12. Either tRCH of tRRH must be satified for a read cycles 13. tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels 14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only : If tWCS >=tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit(high impedance) throughout the entire cycle : If tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min), the cycle is a read-modify-write and the data output will contain data read from the selected cell : if neither of the above sets of conditions is satified, the condition of the data out (at access time) is indeterminate. 15. These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in delayed write or read-modify-write cycles 16. tRASP defines /RAS pulse width in EDO page mode cycles
Rev.0.1/Apr.01
9
HY51V(S)17403HG/HGL
17. Access time is determined by the longest among tAA or tCAC or tACP 18. The 16M DRAM offers 16 bit time saving parallel test mode. Address CA0 and CA1 for the 4Mx4 are don' care during test mode. Test mode is set by performing a /WE-and-/CAS-before-/RAS(WCBR) t cycle. In 16bit parallel test mode, data is written into 4 bits in parallel at each I/O(I/O 1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, Data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test mode and enter a normal operation mode, perform either a regular /CAS-before-/RAS refresh cycle or /RAS-only refresh cycle. 19. In a test mode read cycle, the value of tRAC, tAA, tCAC and tACP is delayed by 2ns to 5ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet 20. tHPC(min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode /RAS cycle(EDO page mode mix cycle (1)(2)), minimum value of /CAS cycle(tCAS+tCP+2tT) becomes greater than the specified tHPC(min) value. The value of /CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2)
Rev.0.1/Apr.01
10
HY51V(S)17403HG/HGL
PACKAGE INFORMATION
24(26)pin SOJ
Unit: Inches (mm)
0.025(0.64) MIN 0.260(6.60) MIN
0 ~ 5 Deg
0.305(7.75) MAX
0.340(8.64) MAX
0.329(8.38) MIN
0.661(16.80) MIN 0.669(17.00) MAX
0.085(2.16) MIN
0.128(3.25) MIN 0.147(3.75) MAX 0.050(1.27) TYP 0.015(0.38) MIN 0.020(0.50) MAX 0.026(0.66) MIN 0.032(0.81) MAX
24(26)pin TSOP-II
0.016(0.40) MIN 0.024(0.60) MAX
0.303(7.72) MAX
0.670(17.04) MIN 0.678(17.24) MAX 0.037(0.95) MIN 0.041(1.05) MAX 0.047(1.20) MAX 0.012(0.30) MIN 0.020(0.50) MAX 0.050(1.27) TYP 0.003(0.08) MIN 0.007(0.18) MAX
0.371(9.42) MAX
0.296(7.52) MIN
0.355(9.02) MIN
0.004(0.12) MIN 0.008(0.21) MAX
Rev.0.1/Apr.01
0.275(6.99) MAX
0.295(7.49) MIN
11

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