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144 pin SO-DIMM SDRAM Modules
HYS64V16200GDL HYS64V32220GDL
128MB & 256 MB PC100 / PC133
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144 Pin Eight Byte Small Outline Dual-In-Line Synchronous DRAM Modules for PC100 and PC133 notebook applications One bank 16M x 64 (128MByte) and two banks 32M x 64 (256 MByte) non-parity module organisation Performance:
-7 PC133 2-2-2 fCK tAC Clock frequency (max.) Clock access time 133 5.4 -7.5 PC133 3-3-3 133 5.4 -8 PC100 2-2-2 100 6 Units MHz ns
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Single +3.3V( 0.3V ) power supply Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh Decoupling capacitors mounted on substrate All inputs, outputs are LVTTL compatible Serial Presence Detect with E2PROM 256Mbit SDRAM low power components in TSOP54 packages with 16M x 16 organisation 8192 refresh cycles every 64 ms Gold contact pad, JEDEC MO-190 outline dimensions This module family is fully compliant with the latest INTEL SO-DIMM layout and electrical specifications All PC133 modules are fully backward compatible to PC100-222 operation Importante Notice: These SO-DIMM modules are based on 256Mbit SDRAM technology and can be used in applications only, where 256Mbit addressing is supported.
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INFINEON Technologies
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HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules
This INFINEON modules are industry standard 144 pin 8-byte Synchronous DRAM (SDRAM) Small Outline Dual In-line Memory Modules (SO-DIMM) which are organised as x64 high speed memory arrays designed for use in non-parity applications. These SO-DIMMs use 256Mbit SDRAMs in TSOPII packages. Decoupling capacitors are mounted on the board. The DIMMs use serial presence detects implemented via a serial E2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All INFINEON 144-pin SO-DIMMs provide a high performance, flexible 8-byte interface in a 67,6 mm long footprint.
Product Spectrum:
Speed HYS64V16200GDL-7 HYS64V16200GDL-7.5 HYS64V16200GDL-8 HYS64V32220GDL-7 HYS64V32220GDL-7.5 32M x 64 HYS64V32220GDL-8 16M x 64 SDRAMs used RowAddr. Bank Select Column Refresh Addr. Period
PC133-222 PC133-333 4 16Mx16 PC100-222 PC133-222 PC133-333 8 16Mx16 PC100-222
8k 13 BA0, BA1 9 7,8 s
Note: All partnumbers end with a place code, designating the die revision. Example: HYS64V32220GDL-8-C2,
indicating Rev.C2 dies are used for SDRAM components.
Card Dimensions:
Organisation 16M x 64 32M x 64 PCB-Board INTEL Rev. 1.0/1.2 L x H x T [mm] 67.60 x 25.40 x 3.80 67.60 x 31.75 x 3.80
Pin Names
A0-A12 BA0,BA1 DQ0 - DQ63 RAS CAS WE CKE0, CKE1 CLK0, CLK1 *) Address Inputs Bank Selects Data Input/Output Row Address Strobe Column Address Strobe Read / Write Input Clock Enable Clock Input DQMB0 -DQMB7 CS0, CS1 *) Vcc Vss SCL SDA N.C. Data Mask Chip Select Power (+3.3 Volt) Ground Clock for Presence Detect Serial Data Out for Presence Detect No Connection
*) CS1 and CKE1 on two bank modules only
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Pin Configuration
PIN # Front Side PIN # Back Side PIN # Front Side PIN # Back Side
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 Vss DQMB0 DQMB1 Vcc A0 A1 A2 Vss DQ8 DQ9 DQ10 DQ11 Vcc DQ12 DQ13 DQ14 DQ15 Vss NC NC CLK0 Vcc RAS WE CS0 CS1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
VSS DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 Vss DQMB4 DQMB5 Vcc A3 A4 A5 Vss DQ40 DQ41 DQ42 DQ43 Vcc DQ44 DQ45 DQ46 DQ47 Vss NC NC CKE0 Vcc CAS CKE1 A12 N.C
73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
NC Vss NC NC Vcc DQ16 DQ17 DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 Vcc A6 A8 Vss A9 A10 Vcc DQMB2 DQMB3 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss SDA Vcc
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
CLK1 Vss NC NC Vcc DQ48 DQ49 DQ50 DQ51 Vss DQ52 DQ53 DQ54 DQ55 Vcc A7 BA0 Vss BA1 A11 Vcc DQMB6 DQMB7 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss SCL Vcc
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HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules
WE CS0 DQMB0 DQ0-DQ7 DQMB1 DQ8-DQ15 WE CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 D0 DQMB4 DQ32-DQ39 DQMB5 DQ40-DQ47 WE CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 D2
DQMB2 DQ16-DQ23 DQMB3 DQ24-DQ31
WE CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 D1
DQMB6 DQ48-DQ55 DQMB7 DQ56-DQ63
WE CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 D3
A0-A12, BA0, BA1 VC C C 1 -C 4 VSS RAS CAS CKE0 CLK0 CLK1
D0-D3 D0-D3 D0-D3 D0-D3 D0-D3 D0-D3 4 SDRAM Note: All resistors are 10 10 pF
SPB04133_256Mb
E 2 PROM (256 word x 8 Bit) SA0 SA1 SA2 SCL SDA
Block Diagram for one bank 16M x 64 (128MByte) SDRAM SO- DIMM - Module
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HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules
WE CS0 CS1 DQMB0 DQ0-DQ7 DQMB1 DQ8-DQ15 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D0 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D4 DQMB4 DQ32-DQ39 DQMB5 DQ40-DQ47 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D2 CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D6
DQMB2 DQ16-DQ23 DQMB3 DQ24-DQ31
CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D1
CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D5
DQMB6 DQ48-DQ55 DQMB7 DQ56-DQ63
CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D3
CS WE LDQM DQ0-DQ7 UDQM DQ8-DQ15 D7
A0-A12, BA0, BA1 VC C C VS S RAS CAS CKE0 CKE1 CLK0 CLK1
D0-D7 D0-D7 D0-D7 D0-D7 D0-D7 D0-D3 D4-D7 D0-D3 D4-D7 Note: All resistors are 10
SPB04134_256M
E 2 PROM (256 word x 8 Bit) SA0 SA1 SA2 SCL SDA
Block Diagram for two bank 32M x 64 (256MByte) SDRAM SO- DIMM - Module
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Absolute Maximum Ratings
Parameter Symbol min. Input / Output voltage relative to VSS Power supply voltage on VDD Storage temperature range Power dissipation (per SDRAM component) Data out current (short circuit) VIN, VOUT VDD T STG PD IOS - 1.0 - 1.0 -55 - - Limit Values max. 4.6 4.6 +150 1 50 V V
oC
Unit
W mA
Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability
DC Characteristics
TA = 0 to 70 oC; VSS = 0 V; VDD = 3.3 V 0.3 V Parameter
Symbol Limit Values min. Input high voltage Input low voltage Output high voltage (I OUT = - 4.0 mA) Output low voltage (IOUT = 4.0 mA) Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) Output leakage current (DQ is disabled, 0 V < VOUT < VDD) VIH VIL VOH VOL I I(L) I O(L) 2.0 - 0.5 2.4 - - 20 - 20 max. Vcc+0.3 0.8 - 0.4 20 20 V V V V mA mA Unit
Capacitance
TA = 0 to 70 oC; VDD = 3.3 V 0.3 V, f = 1 MHz Parameter
Symbol Limit Values 16M x 64 max. Input capacitance (A0 to A11, BA0, BA1) Input capacitance (RAS, CAS, WE, CKE0) Input Capacitance (CLK0, CLK1) Input capacitance (CS0) Input capacitance (DQMB0-DQMB7) Input / Output capacitance (DQ0-DQ63) Input Capacitance (SCL,SA0-2) Input/Output Capacitance CI1 CI2 CI3 CI4 CI5 CIO Csc Csd 28 25 35 25 10 12 8 10 32M x 64 max. 52 46 35 30 15 18 8 10 pF pF pF pF pF pF pF pF Unit
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HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules
Operating Currents per memory bank
(TA = 0 to 70 oC; VSS = 0 V; VDD = 3.3 V 0.3 V) (Recommended Operating Conditions unless otherwise noted)
Parameter & Test Condition
OPERATING CURRENT trc=trcmin., All banks operated in random access, all banks operated in ping-pong manner PRECHARGE STANDBY CURRENT in Power Down Mode CS =VIH (min.), CKE<=Vil(max) PRECHARGE STANDBY CURRENT in Non-Power Down Mode CS = VIH (min.), CKE>=Vih(min) NO OPERATING CURRENT tck = min., CS = VIH(min), active state ( max. 4 banks) BURST OPERATING CURRENT tck = min., Read command cycling AUTO REFRESH CURRENT tck = min., Auto Refresh command cycling SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V, tck = infinity. tck = min.
Symb.
-7/-7.5
-8
Note
ICC1
ICC2P
920 8
680
mA 1, 2 mA 1
tck = min.
ICC2N
160
120
mA
1
CKE>=VIH(min.) CKE<=VIL(max.)
ICC3N ICC3P
200 40 600
180
mA mA
1 1
ICC4
400 mA 1,2
1
ICC5
960
880
mA
ICC6
7.2
mA
1
Notes: 1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7 & -7.5 and at 100 MHz for -8 modules. Input signals are changed once during tck. 2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the data-out current is excluded.
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HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules
AC Characteristics 1)2)
(TA = 0 to 70 oC; VSS = 0 V; VDD = 3.3 V 0.3 V, tT = 1 ns)
Parameter
Symbol
Limit Values -7 PC133-222
min. max.
Unit
-7.5 PC133-333
min. max.
-8 PC100-222
min. max.
Clock and Access Time Clock Cycle Time CAS Latency = 3 tCK CAS Latency = 2 Clock Frequency CAS Latency = 3 tCK CAS Latency = 2 Access Time from Clock CAS Latency = 3 tAC CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Transition time Setup and Hold Paramters Input Setup Time Input Hold Time Power Down Mode Entry time Mode Register Set-up time Common Parameters Row to Column Delay Time Row Precharge Time Row Active Time Row Cycle Time - - - - 2.5 2.5 0.3 133 133 5.4 5.4 - - 1.2 - - - - 2.5 2.5 0.3 133 100 5.4 6 - - 1.2 - - - - 3 3 0.5 100 100 6 6 - - 2 MHz MHz ns ns ns ns ns
2, 3
7.5 7.5
- -
7.5 10
- -
10 10
- -
ns ns
tCH tCL tT
tIS tIH tSB tRSC
1.5 0.8 - 1 2
- - 1 - -
1.5 0.8 - 1 2
- - 1 - -
2 1 - 1 2
- - 1 - -
ns ns
4 4
CLK 4 CLK 4 CLK
Power Down Mode Exit Setup Time tPDE
tRCD tRP tRAS tRC
15 15 42 60 14 1
- -
100k
20 20 45 67 15 1
- -
100k
20 20 50 70 16 1
- -
100k
ns ns ns ns ns CLK
5 5 5 5 5
- - -
- - -
- - -
Activate(a) to Activate(b) Command tRRD period CAS(a) to CAS(b) Command period tCCD
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HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules
Parameter
Symbol
Limit Values -7 PC133-222
min. max.
Unit
-7.5 PC133-333
min. max.
-8 PC100-222
min. max.
Refresh Cycle Refresh Period (4096 cycles) Self Refresh Exit Time Read Cycle Data Out Hold Time
Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency
tREF tSREX
- 1
64 -
- 1
64 -
- 1
64 -
ms CLK 6
tOH tLZ tHZ tDQZ
3 0 3 -
- - 7 2
3 0 3 -
- - 7 2
3 0 3 -
- - 8 2
ns ns ns CLK
7
Write Cycle Data Input to Precharge (write recovery) DQM Write Mask Latency
tWR tDQW
2 0
- -
2 0
- -
2 0
- -
CLK CLK
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HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules
Notes: 1. All AC characteristics shown are for SDRAM components. An initial pause of 100 s is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 2. AC timing tests have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between Vih and V il. All AC measurements assume tT =1ns with the AC output load circuit shownSpecified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V. .
t CH CLOCK 1.4 V t CL t IH tT 2.4 V 0.4 V
t IS
INPUT tAC t LZ OUTPUT
1.4 V tAC t OH
I/O
1.4 V t HZ
IO.vsd
50 pF
Measurement conditions for tac and toh
3. If clock rising time is longer than 1ns, a time (tT -0.5) ns has to be added to this parameter. 4. If tT is longer than 1ns, a time (tT -1) ns has to be added to this parameter. 5. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh commands must be given to "wake-up" the device. 6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 7. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
Serial Presence Detects:
A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E 2PROM device during module production using a serial presence detect protocol ( I2C synchronous 2-wire bus)
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SPD-Table HYS64V16200GDL:
Byte# Description SPD Entry Value Hex 16Mx64 16Mx64 16Mx64 -7 -7.5 -8
80 08 04 0D 09 01 40 00 01 75 54 75 54 00 82 10 00 01 0F 04 06 01 01 00 0E 75 54 00 00 0F 0E 0F 2A 15 08 15 08 00 Revision 1.2 F4 12 39 64 87 FF 9C 0F 14 2D 20 15 08 15 08 FF 32 20 10 20 10 A0 60 FF FF 14 10
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 62
Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General SDRAM Cycle Time at CL = 2 SDRAM Access Time from Clock at CL=2 SDRAM Cycle Time at CL = 1 SDRAM Access Time from Clock at CL=1 Minimum Row Precharge Time Minimum Row Active to Row Active delay Minimum RAS to CAS delay Minimum Ras pulse width Module Bank Density (per bank) SDRAM input setup time SDRAM input hold time SDRAM data input setup time SDRAM data input hold time Superset information SPD Revision
128 256 SDRAM 13 9 1 64 0 LVTTL 7.5 / 10.0 ns 5.4 / 6.0 ns none Self-Refresh, 7.8 s x16 n/a tccd = 1 CLK 1, 2, 4 & 8 2 2, & 3 CS latency = 0 Write latency = 0 unbuffered Vcc tol +/- 10% 7.5 / 10 ns 5.4 / 6.0 ns not supported not supported 20 ns 15 / 16 ns 20 ns 42 / 45 / 60 ns 128MB 1.5 / 2 ns 0.8 / 1 ns 1.5 / 2 ns 0.8 / 1 ns
A0 60
63 Checksum for bytes 0 - 62 64-125 Manufactures's information 126 127 128+ Frequency Specification Details Unused storage locations
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SPD-Table HYS64V32220GDL:
Byte# Description SPD Entry Value Hex 32Mx64 32Mx64 32Mx64 -7 -7.5 -8
80 08 04 0D 09 02 40 00 01 75 54 75 54 00 82 10 00 01 0F 04 06 01 01 00 0E 75 54 00 00 0F 0E 0F 2A 15 08 15 08 00 Revision 1.2 F5 12 1E 64 C7 FF 81 0F 14 2D 20 15 08 15 08 FF 32 20 10 20 10 A0 60 FF FF 14 10
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 62
Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General SDRAM Cycle Time at CL = 2 SDRAM Access Time from Clock at CL=2 SDRAM Cycle Time at CL = 1 SDRAM Access Time from Clock at CL=1 Minimum Row Precharge Time Minimum Row Active to Row Active delay Minimum RAS to CAS delay Minimum Ras pulse width Module Bank Density (per bank) SDRAM input setup time SDRAM input hold time SDRAM data input setup time SDRAM data input hold time Superset information SPD Revision
128 256 SDRAM 13 9 2 64 0 LVTTL 7.5 / 10.0 ns 5.4 / 6.0 ns none Self-Refresh, 7.8 s x16 n/a tccd = 1 CLK 1, 2, 4 & 8 2 2, & 3 CS latency = 0 Write latency = 0 unbuffered Vcc tol +/- 10% 7.5 / 10 ns 5.4 / 6.0 ns not supported not supported 20 ns 15 / 16 ns 20 ns 42 / 45 / 60 ns 128MB 1.5 / 2 ns 0.8 / 1 ns 1.5 / 2 ns 0.8 / 1 ns
A0 60
63 Checksum for bytes 0 - 62 64-125 Manufactures's information 126 127 128+ Frequency Specification Details Unused storage locations
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Package Outlines 128 MByte SO-DIMM Module package (JEDEC MO-190) (144 pin, dual read-out, single in-line memory module)
67,6 63,6
0.13
0.15
3.8 max.
25.4 3.3 1
23.2
59 2.6 4.6
61
32.8
143
1 0.1
3.7 2 6 4
1.5 60 62 144
1.8
20
4
Detail of Contacts
Detail of Chamfer
0.6 0.8
0.2 -0.15
0.25
2.55
0.2 -0.15
L-DIM-144-10
note: all tolerances are in accordance with the JEDEC standard
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HYS64V16200GDL/HYS64V32220GDL 144 pin SO-DIMM SDRAM Modules
256 MByte SO-DIMM Module package (JEDEC MO-190) (144 pin, dual read-out, single in-line memory module)
67.6 63.6
0.13
0.15
3.8 max.
31.75 3.3 1
23.2 24.5
59
61 2.5
32.8
143
1 0.1
4.6 3.7 2 4 1.5 60 62 144 1.8
20
6 4 Detail of Contacts
Detail of Chamfer
0.25
0.6 0.8
L-DIM-144-9
0.2 -0.15
2.55
0.2 -0.15
note: all tolerances are in accordance with the JEDEC standard
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Change List
6.99 19.1.2000 19.7.2000 24.7.2000 25.7.2000 5.9.2000 First and preliminary version, -8A only -7.5 and -8 speed sorts added CKE1 added to the block diagram GDL versions added for 256Mbit S17-C2 with 1.5mA ICC6 per component -8A speed sort removed backward compatibility for "C2" base modules clarifed ICC6 changed from 6mA to 6.8 mA per memory bank after the component datasheet for 256M S17 changed from 1.5 to 1.7 mA ICC2PS changed from 16 to 8 mA ICC6 changed from 6.8 to 7.2 mA (Request from Axel Hahn and Uwe Fritsch) Component datasheet unchanged at ICC6=1.7mA Preliminary Capacitance Values added All reference to older versions based on 256M S20 removed ICC currents, where wrong and have been corrected according to the latest 256M S17 datasheet HYS64V16200GL-7/-7.5 and -8 added HYS64V1632220GDL-7 added SCR : Absolute Maximum Ratings Table added
24.11.2000
15.12.2000 5.3.2001 9.07.2001 6.09.2001
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