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Integrated Circuit Systems, Inc.
ICS8431I-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
* Fully integrated PLL * Differential 3.3V LVPECL output * Crystal oscillator interface * Output frequency range: 62.5MHz to 350MHz * Crystal input frequency range: 14MHz to 25MHz * VCO range: 250MHz to 700MHz * Programmable PLL loop divider for generating a variety of output frequencies * Spread Spectrum Clocking (SSC) fixed at 1/2% modulation for environments requiring ultra low EMI * PLL bypass modes supporting in-circuit testing and on-chip functional block characterization * Cycle-to-cycle jitter: 30ps (maximum) * 3.3V supply voltage * -40C to 85C ambient operating temperature * Replaces ICS8431I-01 * Available in both, Standard and RoHS/Lead-Free compliant packages
GENERAL DESCRIPTION
The ICS8431I-21 is a general purpose clock frequency synthesizer for IA64/32 application and a HiPerClockSTM member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The VCO operates at a frequency range of 250MHz to 700MHz providing an output frequency range of 62.5MHz to 350MHz. The output frequency can be programmed using the parallel interface, M0 through M8 to the configuration logic, and the output divider control pin, DIV_SEL. Spread spectrum clocking is programmed via the control inputs SSC_CTL0 and SSC_CTL1.
IC S
Programmable features of the ICS8431I-21 support four operational modes. The four modes are spread spectrum clocking (SSC), non-spread spectrum clock and two test modes which are controlled by the SSC_CTL[1:0] pins. Unlike other synthesizers, the ICS8431I-21 can immediately change spread-spectrum operation without having to reset the device. In SSC mode, the output clock is modulated in order to achieve a reduction in EMI. In one of the PLL bypass test modes, the PLL is disconnected as the source to the differential output allowing an external source to be connected to the TEST_I/O pin. This is useful for in-circuit testing and allows the differential output to be driven at a lower frequency throughout the system clock tree. In the other PLL bypass mode, the oscillator divider is used as the source to both the M and the Fout divide by 2. This is useful for characterizing the oscillator and internal dividers.
BLOCK DIAGRAM
XTAL_IN OSC XTAL_OUT / 16
PIN ASSIGNMENT
M0 M1 M2 M3 M4 M5 M6 M7 M8 SSC_CTL0 SSC_CTL1 VEE TEST_I/O VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nP_LOAD VCC XTAL_IN XTAL_OUT nc nc VCCA VEE MR DIV_SEL VCCO FOUT nFOUT VEE
PLL
PHASE DETECTOR /2 VCO /M /4 FOUT nFOUT
ICS8431I-21
TEST_I/O Configuration Logic SSC Control Logic
M0:M8
28-Lead SOIC 7.5mm x 18.05mm x 2.25mm package body M Package Top View
nP_LOAD
SSC_CTL0
SSC_CTL1
DIV_SEL
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Integrated Circuit Systems, Inc.
ICS8431I-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
The PLL loop divider or M divider is programmed by using inputs M0 through M8. While the nP_LOAD input is held LOW, the data present at M0:M8 is transparent to the M divider. On the LOW-to-HIGH transition of nP_LOAD, the M0:M8 data is latched into the M divider and any further changes at the M0:M8 inputs will not be seen by the M divider until the next LOW transition on nP_LOAD. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fxtal x fVCO = M 16 The M value and the required values of M0:M8 for programming the VCO are shown in Table 3B, Programmable VCO Frequency Function Table. The frequency out is defined as follows: FOUT = fVCO = fxtal x M N 16 x N For the ICS8431I-21, the output divider may be set to either /2 or /4 by the DIV_SEL pin. For an input of 16 MHz, valid M values for which the PLL will achieve lock are defined as: 250 M 511.
FUNCTIONAL DESCRIPTION
The ICS8431I-21 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. The output of the oscillator is divided by 16 prior to the phase detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to the LVPECL output buffer. The divider provides a 50% output duty cycle. The programmable features of the ICS8431I-21 support four output operational modes and a programmable M divider and output divider. The four output operational modes are spread spectrum clocking (SSC), non-spread spectrum clock and two test modes and are controlled by the SSC_CTL[1:0] pins.
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ICS8431I-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Power Input / Output Power Output Power Input Description
TABLE 1. PIN DESCRIPTIONS
Number 1, 2, 3, 4, 5, 6, 7 8, 9 10, 11 12, 15, 21 13 14, 27 16, 17 18 19 Name M0-M6 M7-M8 SSC CTL0, SSC CTL1 VEE TEST I/O VCC nFOUT, FOUT VCCO DIV_SEL
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS / LVTTL pins interface levels. Pullup Pullup SCC control pins. LVTTL / LVCMOS interface levels. Negative supply pins. Connect all VEE pins to board ground. Programmed as defined in Table 3A Function Table. Core supply pin. Differential outputs for the synthesizer. 3.3V LVPECL interface levels. Output supply pin. Determines the output divide value for FOUT. Pulldown LVCMOS / LVTTL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true output FOUT to go low and the inver ted output Pulldown nFOUT to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not effect loaded M and T values. LVCMOS / LVTTL interface levels. Analog supply pin.
20
MR
Input
22 23, 24
VCCA nc XTAL_OUT, XTAL_IN
Power Unused
No connect. Crystal oscillator interface. XTAL_IN is the input. 25, 26 Input XTAL_OUT is the output. Parallel load input. Determines when data present at M8:M0 28 nP_LOAD Input Pulldown is loaded into M divider. LVTTL / LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Pin Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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ICS8431I-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
Outputs SSC FOUT, nFOUT DIV_SEL0 DIV_SEL1 fXTAL / 32 fXTAL x M 32 Test Clk fXTAL / 64 fXTAL x M 64 Test Clk fXTAL x M 64 TEST_I/O Operational Modes
TABLE 3A. SSC CONTROL INPUT FUNCTION TABLE
Inputs SSC_CTL1 SSC_CTL0 0 0 1 1 0 1 0 1 TEST_I/O Source Internal PLL External PLL
Disabled Enabled Disabled Disabled
fXTAL / 16 PLL bypass; oscillator, M and N /M dividers test mode. NOTE 1 Default SSC; Hi-Z Modulation Factor = 1/2 Percent PLL Bypass Mode, NOTE 1; Input (1MHz Test Clk 200MHz) Hi-Z No SSC Modulation
fXTAL x M 32 NOTE 1: Used for in house debug and characterization.
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
VCO Frequency (MHz) 250 251 252 253 * * 508 509 510 511 M Count 250 251 25 2 253 * * 508 509 510 511 256 M8 0 0 0 0 * * 1 1 1 1 128 M7 1 1 1 1 * * 1 1 1 1 64 M6 1 1 1 1 * * 1 1 1 1 32 M5 1 1 1 1 * * 1 1 1 1 16 M4 1 1 1 1 * * 1 1 1 1 8 M3 1 1 1 1 * * 1 1 1 1 4 M2 0 0 1 1 * * 1 1 1 1 2 M1 1 1 0 0 * * 0 0 1 1 1 M0 0 1 0 1 * * 0 1 0 1
NOTE 1: Assumes a 16MHz crystal.
TABLE 3C. FUNCTION TABLE
Inputs DIV_SEL 0 1 N Divider Value 2 4 Output Frequency (MHz) Minimum 125 62.5 Maximum 350 17 5
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ICS8431I-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 46.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol VCC VCCO VCCA IEE ICCA Parameter Core Supply Voltage Output Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3. 3 3.3 3.3 Maximum 3.465 3.465 3.465 155 16 Units V V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol VIH Input Parameter M0:M8, SSC_CTL0, SSC_CTL1, MR, High Voltage DIV_SEL, TEST_I/O, nP_LOAD M0:M8, SSC_CTL0, SSC_CTL1, MR, Low Voltage DIV_SEL, TEST_I/O, nP_LOAD M7, M8, SSC_CTL0, SSC_CTL1, TEST_IO High Current M0:M6, DIV_SEL nP_LOAD, MR M7, M8, SSC_CTL0, SSC_CTL1, TEST_IO Low Current M0:M6, DIV_SEL nP_LOAD, MR Test Conditions Minimum 2 Typical Maximum VCC + 0.3 Units V
VIL
Input
-0.3
0.8
V
VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -150 -5
5 150
A A A A
IIH
Input
IIL
Input
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
NOTE 1: Output terminated with 50 to VCCO - 2V. See Parameter Measurement Section, 3.3V Output Load Test Circuit.
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ICS8431I-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum 14 3 Typical 16 Maximum 25 40 7 Units MHz pF
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Fundamental
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol FOUT Parameter Output Frequency Cycle-to-Cycle Jitter ; NOTE 1, 5 Output Duty Cycle Output Rise/Fall Time Cr ystal Input Range; NOTE 2, 3 SSC Modulation Frequency; NOTE 4 SSC Modulation Factor ; NOTE 4 Spectral Reduction; NOTE 4 FOUT = 200MHz FOUT = 200MHz FOUT = 200MHz 7 20% to 80% FOUT 100MHz 48 20 0 14 29 0.4 10 10 16 Test Conditions Minimum 62.5 19 50 Typical Maximum 350 30 52 700 25 33.33 0. 6 Units MHz ps % ps MHz KH z % dB ms
tj it(cc)
odc tR / tF Fxtal FM FMF SSCred
Power-up to Stable Clock Output tSTABLE See Figures in the Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Only valid within the VCO operating range. NOTE 3: For XTAL input, refer to Application Note. NOTE 4: Spread Spectrum clocking enabled. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8431I-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
V CC , VCCA, VCCO
Qx
SCOPE
nFOUT FOUT
LVPECL
VEE
nQx
tcycle
n
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
CYCLE-TO-CYCLE JITTER
nFOUT 80% Clock Outputs 80% VSW I N G 20% tR tF
odc = t PW t PERIOD x 100%
FOUT
t PW
t
PERIOD
20%
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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tcycle n+1
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ICS8431I-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8431I-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, better power supply isolation is required. Figure 3 illustrates how a 10 along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F VCCA .01F 10F 10
FIGURE 3. POWER SUPPLY FILTERING
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is typical for IA64/32 platforms. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
125
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
RTT =
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
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The ICS8431I-21 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 3 below were determined using a 25MHz, 18pF parallel resonant crystal and
ICS8431I-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p
Figure 3. CRYSTAL INPUT INTERFACE
SPREAD SPECTRUM
Spread-spectrum clocking is a frequency modulation technique for EMI reduction. When spread-spectrum is enabled, a 30kHz triangle waveform is used with 0.5% down-spread (+0.0% / -0.5%) from the nominal 200MHz clock frequency. An example of a triangle frequency modulation profile is shown in Figure 4A below. The ramp profile can be expressed as: * Fnom = Nominal Clock Frequency in Spread OFF mode (200MHz with 16MHz IN) * Fm = Nominal Modulation Frequency (30kHz) * = Modulation Factor (0.5% down spread) (1 - ) fnom + 2 fm x x fnom x t when 0 < t < 1 , 2 fm (1 - ) fnom - 2 fm x x fnom x t when 1 < t < 1 2 fm fm The ICS8431I-21 triangle modulation frequency deviation will not exceed 0.6% down-spread from the nominal clock frequency (+0.0% / -0.5%). An example of the amount of down spread relative to the nominal clock frequency can be seen in the frequency domain, as shown in Figure 4B. The ratio of this width to the fundamental frequency is typically 0.4%, and will not exceed 0.6%. The resulting spectral reduction will be greater than 7dB, as shown in Figure 4B. It is important to note the ICS8431I-21 7dB minimum spectral reduction is the component-specific EMI reduction, and will not necessarily be the same as the system EMI reduction.
Fnom
- 10 dBm
B
A
(1 - ) Fnom
= .4%
0.5/fm 1/fm
FIGURE 4A. TRIANGLE FREQUENCY MODULATION
8431AMI-21
FIGURE 4B. 200MHZ CLOCK OUTPUT
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IN
FREQUENCY DOMAIN
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(A) SPREAD-SPECTRUM OFF (B) SPREAD-SPECTRUM ON
Integrated Circuit Systems, Inc.
ICS8431I-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
in Figure 5B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types and the density of the P.C. board.
LAYOUT GUIDELINE
The schematic of the ICS8431I-21 layout example used in this layout guideline is shown in Figure 5A. The ICS8431I-21 recommended PCB board layout for this example is shown
Logic Input Pin Examples
VCC=3.3V
VCC
SP=Spare, not installed
RU1 1K C6 0.01uF U1 C8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 M0 M1 M2 M3 M4 M5 M6 M7 M8 SSC_CTL0 SSC_CTL1 VEE TEST_IO VCC nP_LOAD VCC XTAL_IN XTAL_OUT NC NC VCCA VEE MR DIV_SEL VCCO FOUT nFOUT VEE 28 27 26 25 24 23 22 21 20 19 18 17 16 15 22pF RD1 SP X1 C7 22pF R5 VCCA VCC C3 0.01uF C4 10uF 10 Zo = 50 Ohm VCC
Set Logic Input to '1'
VCC
Set Logic Input to '0'
RU2 SP
VCC
To Logic Input pins
RD2 1K
To Logic Input pins
VCC
R1 125
R3 125 +
VCC
C1 0.1uF
ICS8431I-21 ICS8431-21
C2 0.1uF
Zo = 50 Ohm
-
R2 84
R4 84
FIGURE 5A. SCHEMATIC EXAMPLE
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The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
ICS8431I-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
* Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. * Make sure no other signal traces are routed between the clock trace pair. * The matching termination resistors should be located as close to the receiver input pins as possible. The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination scheme can also be used but is not shown in the example.
POWER
AND
GROUNDING
Place the decoupling capacitors C1, C2 and C6, as close as possible to the power pins. If space allows, placment of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R5, C3, and C4 should be placed as close to the VCCA pin as possible.
CLOCK TRACES
AND
TERMINATION
Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. * The 50 output trace pair should have same length.
CRYSTAL
The crystal X1 should be located as close as possible to the pins 25 (XTAL_OUT) and 26 (XTAL_IN). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.
C8
GND U1 ICS8431-21
C6
VCC Signals VIA X1
C3
C4
R5
C7 C2 Zo=50 Ohm
C1
Zo=50 Ohm
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8431I-21
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ICS8431I-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8431I-21. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8431I-21 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 155mA = 537.1mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 1 * 30mW = 30mW
Total Power_MAX (3.465V, with all outputs switching) = 537.1mW + 30mW = 567.1mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.567W * 39.7C/W = 107.5C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
Table 7. THERMAL RESISTANCE JA
FOR
28-PIN SOIC, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 76.2C/W 46.2C/W
200
60.8C/W 39.7C/W
500
53.2C/W 36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS8431I-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V
OL_MAX
CCO_MAX
(VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V - (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= Pd_H = [(V OH_MAX CCO_MAX CCO_MAX OH_MAX OH_MAX CCO_MAX OH_MAX L CCO _MAX L [(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(V - (V - 2V))/R ] * (V
L
OL_MAX
CCO_MAX
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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ICS8431I-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
FOR
28 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 76.2C/W 46.2C/W
200
60.8C/W 39.7C/W
500
53.2C/W 36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8431I-21 is: 4790
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REV. A AUGUST 2, 2005
Integrated Circuit Systems, Inc.
ICS8431I-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
28 LEAD SOIC
PACKAGE OUTLINE - M SUFFIX
FOR
TABLE 9. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 17.70 7.40 1.27 BASIC 10.65 0.75 1.27 8 Millimeters MINIMUM 28 2.65 -2.55 0.51 0.32 18.40 7.60 MAXIMUM
Reference Document: JEDEC Publication 95, MS-013, MO-119
8431AMI-21
www.icst.com/products/hiperclocks.html
15
REV. A AUGUST 2, 2005
Integrated Circuit Systems, Inc.
ICS8431I-21
350MHZ, LOW JITTER, CRYSTAL OSCILLATORTO-3.3V LVPECL FREQUENCY SYNTHESIZER
Marking Package 28 Lead SOIC 28 Lead SOIC 28 Lead "Lead-Free" SOIC 28 Lead "Lead-Free" SOIC Shipping Packaging Tube 1000 tape & reel Tube 1000 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS8431AMI-21 ICS8431AMI-21T ICS8431AMI-21LF ICS8431AMI-21LFT ICS8431AMI-21 ICS8431AMI-21 TBD TBD
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8431AMI-21
www.icst.com/products/hiperclocks.html
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REV. A AUGUST 2, 2005

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