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Integrated Circuit Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
FEATURES
* 2 differential 2.5V/3.3V LVPECL / ECL bank outputs * 2 differential clock input pairs * PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Maximum output frequency: >3GHz * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLKx input * Output skew: 13ps (typical) * Part-to-part skew: 85ps (typical) * Propagation delay: 485ps (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -2.375V to -3.8V * -40C to 85C ambient operating temperature * Pin compatible with MC100EP210 and MC100LVEP210
GENERAL DESCRIPTION
The ICS853210 is a low skew, high performance dual 1 - t o -5 Differential-to-2.5V/3.3V HiPerClockSTM LVPECL/ECL Fanout Buffer and a member of the HiPerClockSTMfamily of High Performance Clock Solutions from ICS. The ICS853210 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and par t-to-par t skew characteristics make the ICS853210 ideal for those clock distribution applications demanding well defined performance and repeatability.
ICS
BLOCK DIAGRAM
PCLKA nPCLKA QA0 nQA0 QA1 nQA1 QA2 nQA2 QA3 nQA3 QA4 nQA4
PIN ASSIGNMENT
nQA3 nQA4 nQB0 nQB1 QA3 QA4 QB0 QB1
24 23 22 21 20 19 18 17 VCCO nQA2 QA2 nQA1 QA1 nQA0 QA0 25 26 27 28 29 30 31 32 1
VCC
16 15 14
VCCO QB2 nQB2 QB3 nQB3 QB4 nQB4 VCCO
ICS853210
13 12 11 10 9
nPCLKB
PCLKA
VBB
QB2 nQB2 V BB QB3 nQB3 QB4 nQB4
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
853210AY
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1
nPCLKA
PCLKB
VEE
REV. A NOVEMBER 12, 2003
nc
PCLKB nPCLKB
QB0 nQB0 QB1 nQB1
VCCO
2
3
4
5
6
7
8
Integrated Circuit Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Type Power Unused Input Input Output Input Input Power Power Output Output Output Output Output Output Output Output Output Output Description Core supply pin. No connect. Pulldown Non-inver ting differential clock input. Pullup/ Clock input. VCC/2 default when left floating. Pulldown Bias voltage. Pulldown Non-inver ting differential clock input. Pullup/ Clock input. VCC/2 default when left floating. Pulldown Negative supply pin. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8 9, 25, 32 10, 11 12, 13 14, 15 17, 18 19, 20 21, 22 23, 24 26, 27 28, 29 30, 31 Name VCC nc PCLKA nPCLKA V BB PCLKB nPCLKB V EE VCCO nQB4, QB4 nQB3, QB3 nQB2, QB2 nQB1, QB1 nQB0, QB0 nQA4, QA4 nQA3, QA3 nQA2, QA2 nQA1, QA1 nQA0, QA0
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN RVCC/2 Parameter Input Pulldown Resistor Pullup/Pulldown Resistors Test Conditions Minimum Typical 75 50 Maximum Units K K
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs PCLKA or PCLKB 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nPCLKA or nPCLKB 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Outputs QA0:QA4, nQA0:nQA4, QB0:QB4 nQB0:nQB4 HIGH LOW HIGH LOW HIGH HIGH LOW LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
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REV. A NOVEMBER 12, 2003
Integrated Circuit Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) -0.5V to VCC + 0.5V 0.5V to VEE - 0.5V 50mA 100mA 0.5mA -65C to 150C 47.9C/W (0 lfpm) to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character-
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current VBB Sink/Source, IBB Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40C to +85C
istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol VCC I EE Parameter Core Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 Maximum 3.8 80 Units V mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol VOH VOL VIH VIL VBB VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 PCLK0, PCLK1 Input Low Current nPCLK0, nPCLK1 Min
2.175 1.405 2.075 1.43 1.86 150 1.2 800
-40C Typ
2.275 1.545
Max
2.38 1.68 2.36 1.765 1.98 1200 3.3 150
Min
2.225 1.425 2.075 1.43 1.86 150 1.2
25C Typ
2.295 1.52
Max
2.37 1.615 2.36 1.765 1.98
Min
2.295 1.44 2.075 1.43 1.86 150 1.2
85C Typ
2.33 1.535
Max
2.365 1.63 2.36 1.765 1.98
Units
V V V V V
800
1200 3.3 150
800
1200 3.3 150
mV
V A A A
-10 -150
-10 -150
-10 -150
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
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REV. A NOVEMBER 12, 2003
Integrated Circuit Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
-40C Min
1.375 0.605 1.275 0.63 150 1.2 800
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol VOH VOL VIH VIL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 Input Low Current PCLK0, PCLK1 25C Max
1.58 0.88 1.56 0.965 1200 2.5 150 -10 -10
85C Max
1.57 0.815 1.56 0.965
Typ
1.475 0.745
Min
1.425 0.625 1.275 0.63 150 1.2
Typ
1.495 0.72
Min
1.495 0.64 1.275 0.63 150 1.2
Typ
1.53 0.735
Max
1.565 0.83
Units
V V V V
-0.83
0.965 800 1200 2.5 150
800
1200 2.5 150
mV
V A A A
-10
-150 -150 -150 nPCLK0, nPCLK1 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -2.375 TO -3.8V
Symbol VOH VOL VIH VIL VBB VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 Input Low Current PCLK0, PCLK1 -40C Min
-1.125 -1.895 -1.225 -1.87 -1.44 150 VEE+1.2V 800
25C Max
-0.92 -1.62 -0.94 -1.535 -1.32 1200 0 150
85C Max
-0.93 -1.685 -0.94 -1.535 -1.32
Typ
-1.025 -1.755
Min
-1.075 -1.875 -1.225 -1.87 -1.44 150 VEE+1.2V
Typ
-1.005 -1.78
Min
-1.005 -1.86 -1.225 -1.87 -1.44 150 VEE+1.2V
Typ
-0.97 -1.765
Max
-0.935 -1.67 -0.94 -1.535 -1.32
Units
V V V V V
800
1200 0 150
800
1200 0 150
mV
V A A A
-10 -150
-10 -150
-10 -150
nPCLK0, nPCLK1 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
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REV. A NOVEMBER 12, 2003
Integrated Circuit Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
OR
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -2.375 TO -3.8V
Symbol fMAX tP LH tPHL Parameter Output Frequency Propagation Delay, Low-to-High; NOTE 1 Propagation Delay, @ 2.5V High-to-Low; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time 20% to 80% 115 415 400 Min
VCC = 2.375 TO 3.8V; VEE = 0V
25C Max 520 540 25 160 260 130 Min 430 425 Typ >3 485 490 13 85 190 545 550 25 160 250 145 435 445 Max Min 85C Typ >3 515 515 13 85 190 585 585 25 160 235 Max Units GHz ps ps ps ps ps
-40C Typ >3 470 470 13 85 188
tsk(o) tsk(pp)
tR/tF
All parameters tested 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A NOVEMBER 12, 2003
Integrated Circuit Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC, VCCO
Qx
SCOPE
VCC
LVPECL
nQx
nPCLKA, nPCLKB
V
PP
Cross Points
V
CMR
VEE
PCLKA, PCLKB V EE
-0.375V to -1.8V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
nQx Qx nQy Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nPCLKA, nPCLKB PCLKA, PCLKB
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
nQA0:nQA4, nQB0:nQB4, QA0:QA4, QB0:QB4,
tp
LH
tp
HL
OUTPUT RISE/FALL TIME
853210AY
PROPAGATION DELAY
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REV. A NOVEMBER 12, 2003
Integrated Circuit Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
Figure 1A shows an example of the differential input that can be wired to accept single ended levels. The reference voltage level V BB generated from the device is connected to the
negative input. The C1 capacitor should be located as close as possible to the input pin.
VCC(or VDD)
CLK_IN
PCLK VBB nPCLK
FIGURE 1A. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1B shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 1B. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. A NOVEMBER 12, 2003
Integrated Circuit Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50 FOUT FIN
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
Zo = 50 84 84
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
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REV. A NOVEMBER 12, 2003
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ICS853210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V
VCCO=2.5V
2.5V
VCCO=2.5V
R1 250
R3 250
+
Zo = 50 Ohm
Zo = 50 Ohm
+
Zo = 50 Ohm
Zo = 50 Ohm
-
2,5V LVPECL Driv er
2,5V LVPECL Driv er
R2 62.5
R4 62.5
R1 50
R2 50
R3 18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL Driv er
R1 50
R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. A NOVEMBER 12, 2003
Integrated Circuit Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS PCLKx/nPCLKx input driven by the most common driver types. The input interfaces
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK
Zo = 60 Ohm
2.5V
3.3V
2.5V
R3 120
SSTL
R2 50
R4 120
PCLK
Zo = 60 Ohm
Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK
nPCLK
HiPerClockS PCLK/nPCLK
R1 120
R2 120
FIGURE 4A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V 3.3V
R3 125
R4 125
PCLK
3.3V
Zo = 50 Ohm
LVDS
R5 100
Zo = 50 Ohm
C1
R3 1K
R4 1K
PCLK
C2
Zo = 50 Ohm
nPCLK
LVPECL
R1 84
R2 84
HiPerClockS Input
Zo = 50 Ohm
nPCLK
HiPerClockS PC L K /n PC LK
R1 1K
R2 1K
FIGURE 4C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
3.3V LVPECL
Zo = 50 Ohm
C1
R3 84
R4 84
PCLK
Zo = 50 Ohm
C2
nPCLK
HiPerClockS PCLK/nPCLK
R5 100 - 200
R6 100 - 200
R1 125
R2 125
FIGURE 4E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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REV. A NOVEMBER 12, 2003
Integrated Circuit Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853210. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS853210 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 80mA = 304mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 10 * 30.94mW = 309.4mW
Total Power_MAX (3.8V, with all outputs switching) = 304mW + 309.4mW = 613.4mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.613W * 42.1C/W = 110.8C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
32-PIN LQFP, FORCED CONVECTION
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV. A NOVEMBER 12, 2003
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3. Calculations and Equations.
ICS853210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
RL
50 VCCO - 2V
Figure 5. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CCO_MAX
- 0.935V
-V
OH_MAX
) = 0.935V =V - 1.67V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.67V
Pd_H = [(V
OH_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO _MAX
-V
OH_MAX
)=
[(2V - 0.935V)/50] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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REV. A NOVEMBER 12, 2003
Integrated Circuit Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853210 is: 437
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REV. A NOVEMBER 12, 2003
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ICS853210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
853210AY
www.icst.com/products/hiperclocks.html
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REV. A NOVEMBER 12, 2003
Integrated Circuit Systems, Inc.
ICS853210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Marking ICS853102AY ICS853210AY Package 32 lead LQFP 32 lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS853210AY ICS853210AYT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853210AY
www.icst.com/products/hiperclocks.html
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REV. A NOVEMBER 12, 2003

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