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PD-97177A
RADIATION HARDENED LOGIC LEVEL POWER MOSFET SURFACE MOUNT (SMD-2)
Product Summary
Part Number IRHLNA77064 IRHLNA73064 Radiation Level 100K Rads (Si) 300K Rads (Si) RDS(on) 0.012 0.012 ID 56A* 56A*
IRHLNA77064 60V, N-CHANNEL
TECHNOLOGY
SMD-2
International Rectifier's R7 TM Logic Level Power MOSFETs provide simple solution to interfacing CMOS and TTL control circuits to power devices in space and other radiation environments. The threshold voltage remains within acceptable operating limits over the full operating temperature and post radiation. This is achieved while maintaining single event gate rupture and single event burnout immunity. These devices are used in applications such as current boost low signal source in PWM, voltage comparator and operational amplifiers.
Features:
n n n n n n n n n n
5V CMOS and TTL Compatible Fast Switching Single Event Effect (SEE) Hardened Low Total Gate Charge Simple Drive Requirements Ease of Paralleling Hermetically Sealed Ceramic Package Surface Mount Light Weight
Absolute Maximum Ratings
Parameter
ID @VGS = 4.5V,TC = 25C ID @VGS = 4.5V,TC = 100C IDM PD @ TC = 25C VGS EAS IAR EAR dv/dt TJ T STG Continuous Drain Current Continuous Drain Current Pulsed Drain Current A Max. Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy A Avalanche Current A Repetitive Avalanche Energy A Peak Diode Recovery dv/dt A Operating Junction Storage Temperature Range Pckg. Mounting Surface Temp. Weight * Current is limited by package For footnotes refer to the last page 56* 56* 224 250 2.0 10 402 56 25 6.9 -55 to 150 300 (for 5s) 3.3 (Typical)
Pre-Irradiation
Units A
W
W/C
V mJ A mJ V/ns C g
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04/06/07
IRHLNA77064
Pre-Irradiation
Electrical Characteristics @ Tj = 25C (Unless Otherwise Specified)
Parameter
BVDSS Drain-to-Source Breakdown Voltage BV DSS /T J Temperature Coefficient of Breakdown Voltage RDS(on) Static Drain-to-Source On-State Resistance VGS(th) Gate Threshold Voltage VGS(th)/TJ Gate Threshold Voltage Coefficient gfs Forward Transconductance IDSS Zero Gate Voltage Drain Current
Min
60 -- -- 1.0 -- 32 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Typ Max Units
-- 0.07 -- -- -6.6 -- -- -- -- -- -- -- -- -- -- -- -- 4.0 10220 2343 40 0.56 -- -- 0.012 2.0 -- -- 1.0 10 100 -100 151 30 70 51 170 110 17 -- -- -- -- V V/C V mV/C S A nA
Test Conditions
VGS = 0V, ID = 250A Reference to 25C, ID = 1.0mA VGS = 4.5V, ID = 56A A VDS = VGS, ID = 250A V DS = 10V, IDS = 56A A VDS= 48V ,VGS=0V VDS = 48V, VGS = 0V, TJ = 125C VGS = 10V VGS = -10V VGS = 4.5V, ID = 56A VDS = 30V VDD = 30V, ID = 56A, VGS = 4.5V, RG = 2.35
IGSS IGSS Qg Q gs Q gd td(on) tr td(off) tf LS + LD Ciss C oss C rss Rg
Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Total Gate Charge Gate-to-Source Charge Gate-to-Drain (`Miller') Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance
nC
ns
nH
pF
Measured from the center of drain pad to center of source pad VGS = 0V, VDS = 25V f = 100KHz f = 1.0MHz, open drain
Source-Drain Diode Ratings and Characteristics
Parameter
IS ISM VSD t rr Q RR Continuous Source Current (Body Diode) Pulse Source Current (Body Diode) A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge
Min Typ Max Units
-- -- -- -- -- -- -- -- -- -- 56* 224 1.2 214 1.16
Test Conditions
A
V ns C Tj = 25C, IS = 56A, VGS = 0V A Tj = 25C, IF =56A, di/dt 100A/s VDD 30V A
ton Forward Turn-On Time * Current is limited by package
Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD.
Thermal Resistance
Parameter
RthJC RthJ-PCB Junction-to-Case Junction-to-PC board
Min Typ Max Units
-- -- -- 1.6 0.5 --
C/W
Test Conditions
soldered to a 2 square copper-cladboard
Note: Corresponding Spice and Saber models are available on International Rectifier Web site. For footnotes refer to the last page
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Radiation Characteristics Pre-Irradiation
IRHLNA77064
International Rectifier Radiation Hardened MOSFETs are tested to verify their radiation hardness capability. The hardness assurance program at International Rectifier is comprised of two radiation environments. Every manufacturing lot is tested for total ionizing dose (per notes 5 and 6) using the TO-3 package. Both pre- and post-irradiation performance are tested and specified using the same drive circuitry and test conditions in order to provide a direct comparison.
Table 1. Electrical Characteristics @ Tj = 25C, Post Total Dose Irradiation AA
Parameter
BVDSS V GS(th) IGSS IGSS IDSS RDS(on) RDS(on) VSD Drain-to-Source Breakdown Voltage Gate Threshold Voltage Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Zero Gate Voltage Drain Current Static Drain-to-Source On-State Resistance (TO-3) Static Drain-to-Source On-state Resistance (SMD-2) Diode Forward Voltage Upto 300K Rads (Si)1
Min
60 1.0 -- -- -- -- -- --
Max
Units
V nA A V
Test Conditions
VGS = 0V, ID = 250A VGS = VDS , ID = 250A VGS = 10V VGS = -10V VDS = 48V, VGS=0V VGS = 4.5V, ID = 56A VGS = 4.5V, ID = 56A V GS = 0V, ID = 56A
-- 2.0 100 -100 10 0.01 0.012 1.2
1. Part numbers IRHLNA77064, IRHLNA73064
International Rectifier radiation hardened MOSFETs have been characterized in heavy ion environment for Single Event Effects (SEE). Single Event Effects characterization is illustrated in Fig. a and Table 2.
Table 2. Single Event Effect Safe Operating Area
Ion LET
(MeV/(mg/cm )) Br I Au 37 60 84
2
Energy Range
(MeV) 305 370 390 (m) 39 34 30 0V 60 60 60 -3V 60 60 60 -4V 50 60 60 -5V 45 60 50
VDS (V)
@VGS= @VGS= @VGS= @VGS= @VGS= @VGS= @VGS= @VGS= @VGS=
-6V 40 30 25
-7V 30 20 -
-8V 25 10
-9V 20 10 -
-10V 15 -
80 60 VDS 40 20 0 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 VGS Br I Au
Fig a. Single Event Effect, Safe Operating Area
For footnotes refer to the last page
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IRHLNA77064
Pre-Irradiation
1000
VGS TOP 10V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V BOTTOM 2.5V
1000
ID, Drain-to-Source Current (A)
100
ID, Drain-to-Source Current (A)
100 2.5V 10
VGS 10V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V BOTTOM 2.5V TOP
10
2.5V
60s PULSE WIDTH Tj = 25C 1 0.1 1 10 100 VDS, Drain-to-Source Voltage (V)
60s PULSE WIDTH Tj = 150C 1 0.1 1 10 100 VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
2.0
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID = 56A
1.6
ID, Drain-to-Source Current (A)
100
T J = 150C
1.2
0.8
T J = 25C VDS = 25V 15 60s PULSE WIDTH 2.5 3 3.5 4 4.5 5
0.4
VGS = 4.5V
0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160
10
VGS, Gate-to-Source Voltage (V)
T J , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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Pre-Irradiation
IRHLNA77064
RDS(on), Drain-to -Source On Resistance (m )
ID = 56A 25 20 15 10 5 T J = 25C 0 2 3 4 5 6 7 8 9 10 11 12
RDS(on), Drain-to -Source On Resistance ( m)
30
13 12 11 10 9 8 7 Vgs = 4.5V 6 0 20 40 60 80 100 ID, Drain Current (A) TJ = 25C T J = 150C
T J = 150C
VGS, Gate -to -Source Voltage (V)
Fig 5. Typical On-Resistance Vs Gate Voltage
Fig 6. Typical On-Resistance Vs Drain Current
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
85
2.5
VGS(th) Gate threshold Voltage (V)
ID = 1.0mA
2.0
1.5
75
1.0
0.5
ID = 50A ID = 250A ID = 1.0mA ID = 150mA
65 -60 -40 -20 0 20 40 60 80 100 120 140 160
0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160
T J , Temperature ( C )
T J , Temperature ( C )
Fig 7. Typical Drain-to-Source Breakdown Voltage Vs Temperature
Fig 8. Typical Threshold Voltage Vs Temperature
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IRHLNA77064
Pre-Irradiation
20000 18000 16000
C oss = C ds + C gd
C, Capacitance (pF)
14000 12000 10000 8000 6000 4000 2000 0 1 10 100
VGS, Gate-to-Source Voltage (V)
VGS = 0V, f = 100 KHz C iss = C gs + C gd, C ds SHORTED C rss = C gd
12 ID = 56A 10 8 6 4 2 0 0 30 60 90 120 150 180 210 240 270 300 QG, Total Gate Charge (nC) VDS = 48V VDS = 30V VDS = 12V
Ciss Coss
Crss
FOR TEST CIRCUIT SEE FIGURE 16
VDS, Drain-to-Source Voltage (V)
Fig 9. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 10. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
120
LIMITED BY PACKAGE
ISD, Reverse Drain Current (A)
100
ID , Drain Current (A)
100 T J = 150C 10
T J = 25C
80
60
40
1 VGS = 0V 0.1 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VSD , Source-to-Drain Voltage (V)
20
0
25
50
75
100
125
150
TC , Case Temperature (C)
Fig 11. Typical Source-to-Drain Diode Forward Voltage
Fig 12. Maximum Drain Current Vs. Case Temperature
6
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Pre-Irradiation
IRHLNA77064
1
Thermal Response ( Z thJC )
D = 0.50 0.20
0.1
P DM t1
0.10 0.05 0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE )
t2
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.0001 0.001 0.01 0.1 1
0.01 1E-005
t 1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
EAS , Single Pulse Avalanche Energy (mJ)
800
OPERATION IN THIS AREA LIMITED BY R DS(on)
ID, Drain-to-Source Current (A)
700 600 500 400 300 200 100 0
100
100s
ID 25A 35.4A BOTTOM 56A TOP
1ms 10 Tc = 25C Tj = 150C Single Pulse 1 1 10 VDS , Drain-to-Source Voltage (V) 100 10ms
25
50
75
100
125
150
Starting T J , Junction Temperature (C)
Fig 14. Maximum Safe Operating Area
Fig 15a. Maximum Avalanche Energy Vs. Drain Current
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IRHLNA77064
Pre-Irradiation
V(BR)DSS
15V
tp
VDS
L
DRIVER
RG
VGS 20V
. D.U.T
IAS tp
+ - VDD
A
0.01
I AS
Fig 15c. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
Fig 15b. Unclamped Inductive Test Circuit
4.5V
QG
12V
50K .2F .3F
QGS VG
QGD
VGS
3mA
D.U.T.
+ V - DS
Charge
Fig 16a. Basic Gate Charge Waveform VDS VGS RG VGS
Pulse Width 1 s Duty Factor 0.1 %
IG
ID
Current Sampling Resistors
Fig 16b. Gate Charge Test Circuit
VDS 90%
RD
D.U.T.
VDD
+
-
10% VGS
td(on) tr t d(off) tf
Fig 17a. Switching Time Test Circuit
Fig 17b. Switching Time Waveforms
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Pre-Irradiation
IRHLNA77064
Footnotes:
A Repetitive Rating; Pulse width limited by
maximum junction temperature. A VDD = 25V, starting TJ = 25C, L= 0.26mH Peak IL = 56A, VGS = 10V A ISD 56A, di/dt 350A/s, VDD 60V, TJ 150C
A Pulse width 300 s; Duty Cycle 2% A Total Dose Irradiation with VGS Bias.
10 volt VGS applied and V DS = 0 during irradiation per MIL-STD-750, method 1019, condition A. A Total Dose Irradiation with VDS Bias. 48 volt VDS applied and V GS = 0 during irradiation per MlL-STD-750, method 1019, condition A.
Case Outline and Dimensions -- SMD-2
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 IR LEOMINSTER : 205 Crawford St., Leominster, Massachusetts 01453, USA Tel: (978) 534-5776 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. Data and specifications subject to change without notice. 04/2007
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