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K7B803625M K7B801825M
Document Title
256Kx36 & 512Kx18 Synchronous SRAM
256Kx36 & 512Kx18-Bit Synchronous Burst SRAM
Revision History
Rev. No. 0.0 0.1 History Initial draft Change DC Characteristics. ISB value from 60mA to 90mA at -8 ISB value from 50mA to 80mA at -9 ISB value from 40mA to 70mA at -10 ISB1 value from 10mA to 30mA ISB2 value from 10mA to 30mA 1. Changed tCD from 8.0ns to 8.5ns at -8 2. Changed tCYC from 13.0ns to 12.0ns at -10 3. Changed DC condition at Icc and parameters ICC ; from 300mA to 350mA at -8, from 260mA to 300mA at -9, from 220mA to 260mA at -10, ISB ; from 90mA to 130mA at -8, from 80mA to 120mA at -9, from 70mA to 110mA at -10, 1. ADD 119BGA(7x17 Ball Grid Array Package) . 2. ADD x32 organization. Add VDDQ Supply voltage( 2.5V ) Changed VOL Max value from 0.2V to 0.4V at 2.5V I/O. 1. Final Spec Release. 2. Remove x32 organization. 1. Remove VDDQ supply voltage(2.5V) 1. Changed ICC from 350mA to 330mA at -8. 2. Add bin -7. (tCD 7.5ns). 1. Add VDDQ supply voltage(2.5V) 1. Changed tCYC from 12ns to 10ns at -9. Draft Date April. 10 . 1998 Aug. 31. 1998 Remark Preliminary Preliminary
0.2
Sep. 09. 1998
Preliminary
0.3
Oct. 15. 1998
Preliminary
0.4 0.5 1.0
Dec. 10. 1998 Dec. 23. 1998 Jan. 29. 1999
Preliminary Preliminary Final
2.0 3.0
Feb. 25. 1999 Mar. 30. 1999
Final Final
4.0 5.0
May. 13. 1999 Nov. 19. 1999
Final Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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November 1999 Rev 5.0
K7B803625M K7B801825M
256Kx36 & 512Kx18 Synchronous SRAM
256Kx36 & 512Kx18-Bit Synchronous Burst SRAM
FEATURES
* Synchronous Operation. * On-Chip Address Counter. * Self-Timed Write Cycle. * On-Chip Address and Control Registers. * 3.3V+0.165V/-0.165V Power Supply. * I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O * 5V Tolerant Inputs Except I/O Pins. * Byte Writable Function. * Global Write Enable Controls a full bus-width write. * Power Down State via ZZ Signal. * LBO Pin allows a choice of either a interleaved burst or a linear burst. * Three Chip Enables for simple depth expansion with No Data Contention only for TQFP. * Asynchronous Output Enable Control. * ADSP, ADSC, ADV Burst Control Pins. * TTL-Level Three-State Output. * 100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package)
GENERAL DESCRIPTION
The K7B803625M and K7B801825M are 9,437,184-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 256K(512K) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the systems burst sequence and are controlled by the burst address advance(ADV) input. LBO pin is DC operated and determines burst sequence(linear or interleaved). ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The K7B803625M and K7B801825M are fabricated using SAMSUNGs high performance CMOS technology and is available in a 100pin TQFP and 119BGA package. Multiple power and ground pins are utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER Cycle Time Clock Access Time Output Enable Access Time Symbol -75 -85 -90 -10 Unit tCYC tCD tOE 8.5 10 10 12 ns
7.5 8.5 9.0 10.0 ns 3.5 3.5 3.5 3.5 ns
LOGIC BLOCK DIAGRAM
CLK LBO CONTROL REGISTER ADV ADSC BURST CONTROL LOGIC BURST ADDRESS COUNTER A0~A1 A0~A17 or A0~A18 ADDRESS REGISTER A2~A17 or A2~A18 A0~A1
256Kx36 , 512Kx18 MEMORY ARRAY
ADSP
CS1 CS2 CS2 GW BW WEx (x=a,b,c,d or a,b) OE ZZ
DATA-IN REGISTER CONTROL REGISTER
CONTROL LOGIC
OUTPUT BUFFER
DQa0 ~ DQd7 or DQa0 ~ DQb7 DQPa ~ DQPd DQPa,DQPb
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November 1999 Rev 5.0
K7B803625M K7B801825M
PIN CONFIGURATION(TOP VIEW)
256Kx36 & 512Kx18 Synchronous SRAM
ADSC ADSP
WEd
WEb
WEa
WEc
ADV 83
CLK
CS1
CS2
CS2
VDD
GW
VSS
BW
OE
A6
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
VDD
A5
A4
A3
A2
A1
A0
A17
A10
A11
A12
A13
A14
A15
PIN
SYMBOL A0 - A17 PIN NAME Address Inputs TQFP PIN NO. SYMBOL VDD VSS N.C. DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~Pd VDDQ VSSQ PIN NAME Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs TQFP PIN NO. 15,41,65,91 17,40,67,90 14,16,38,39,42,66 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 32,33,34,35,36,37,43 44,45,46,47,48,49,50 81,82,99,100 ADV Burst Address Advance 83 ADSP Address Status Processor 84 ADSC Address Status Controller 85 CLK Clock 89 CS1 Chip Select 98 CS2 Chip Select 97 CS2 Chip Select 92 WEx(x=a,b,c,d) Byte Write Inputs 93,94,95,96 OE Output Enable 86 GW Global Write Enable 88 BW Byte Write Enable 87 ZZ Power Down Input 64 LBO Burst Mode Control 31
LBO
VSS
Output Power Supply (2.5V or 3.3V) Output Ground
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. 2. The pin 42 is reserved for address bit for the 16Mb .
A16
50
DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 N.C. VDD N.C. VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 DQPd
81
A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
K7B803625M(256Kx36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPb DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS N.C. VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa
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November 1999 Rev 5.0
K7B803625M K7B801825M
PIN CONFIGURATION(TOP VIEW)
256Kx36 & 512Kx18 Synchronous SRAM
ADSC
ADSP
WEb
WEa
ADV 83
N.C.
N.C.
CLK
CS1
CS2
CS2
VDD
GW
VSS
BW
OE
A6
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
VDD
A5
A4
A3
A2
A1
A0
A18
A11
A12
A13
A14
A15
A16
PIN NAME
SYMBOL A0 - A18 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37,43 44,45,46,47,48,49,50 80,81,82,99,100 83 84 85 89 98 97 92 93,94 86 88 87 64 31 SYMBOL VDD VSS N.C. PIN NAME Power Supply(+3.3V) Ground No Connect TQFP PIN NO. 15,41,65,91 17,40,67,90 1,2,3,6,7,14,16,25,28,29, 30,38,39,42,51,52,53,56, 57,66,75,78,79,95,96 58,59,62,63,68,69,72,73 8,9,12,13,18,19,22,23 74,24 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76
ADV ADSP ADSC CLK CS1 CS2 CS2 WEx OE GW BW ZZ LBO
Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control
LBO
VSS
DQa0 ~ a7 DQb0 ~ b7 DQPa, Pb VDDQ VSSQ
Data Inputs/Outputs
Output Power Supply (2.5V or 3.3V) Output Ground
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. 2. The pin 42 is reserved for address bit for the 16Mb .
A17
50
N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. DQb0 DQb1 VSSQ VDDQ DQb2 DQb3 N.C. VDD N.C. VSS DQb4 DQb5 VDDQ VSSQ DQb6 DQb7 DQPb N.C. VSSQ VDDQ N.C. N.C. N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
K7B801825M(512Kx18)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A10 N.C. N.C. VDDQ VSSQ N.C. DQPa DQa7 DQa6 VSSQ VDDQ DQa5 DQa4 VSS N.C. VDD ZZ DQa3 DQa2 VDDQ VSSQ DQa1 DQa0 N.C. N.C. VSSQ VDDQ N.C. N.C. N.C.
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November 1999 Rev 5.0
K7B803625M K7B801825M
256Kx36 & 512Kx18 Synchronous SRAM
119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7B803625M(256Kx36)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ 2 A CS2 A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQPd A NC NC 3 A A A VSS VSS VSS WEc VSS NC VSS WEd VSS VSS VSS LBO A NC 4 ADSP ADSC VDD NC CS1 OE ADV GW VDD CLK NC BW A1* A0* VDD A NC 5 A A A VSS VSS VSS WEb VSS NC VSS WEa VSS VSS VSS NC A NC 6 A A A DQPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A NC NC 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL A A0, A1 ADV ADSP ADSC CLK CS1 CS2 WEx (x=a,b,c,d) OE GW BW ZZ LBO PIN NAME Address Inputs Burst Count Address Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Byte Write Inputs VDD VSS N.C. DQa DQb DQc DQd DQPa~Pd VDDQ Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control SYMBOL PIN NAME Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outpus Output Power Supply (2.5V or 3.3V)
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November 1999 Rev 5.0
K7B803625M K7B801825M
256Kx36 & 512Kx18 Synchronous SRAM
119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)
K7B801825M(512Kx18)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC NC VDDQ 2 A CS2 A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A NC 3 A A A VSS VSS VSS WEb VSS NC VSS VSS VSS VSS VSS LBO A NC 4 ADSP ADSC VDD NC CS1 OE ADV GW VDD CLK NC BW A1* A0* VDD NC NC 5 A A A VSS VSS VSS VSS VSS NC VSS WEa VSS VSS VSS NC A NC 6 A A A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC 7 VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ
Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL A A0,A1 ADV ADSP ADSC CLK CS1 CS2 WEx (x=a,b) OE GW BW ZZ LBO PIN NAME Address Inputs Burst Count Address Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Byte Write Inputs VDD VSS N.C. DQa DQb DQPa~Pb VDDQ SYMBOL PIN NAME Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outpus Output Power Supply (2.5V or 3.3V)
Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control
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November 1999 Rev 5.0
K7B803625M K7B801825M
FUNCTION DESCRIPTION
256Kx36 & 512Kx18 Synchronous SRAM
The K7B803625M and K7B801825M are synchronous SRAM designed to support the burst address accessing sequence of the Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins. The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV. When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally. Read cycles are initiated with ADSP(or ADSC) using the new external address clocked into the on-chip address register when both GW and BW are high or when BW is low and WEa, WEb, WEc, and WEd are high. When ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. the data of cell array accessed by the current address are projected to the output pins. Write cycles are also initiated with ADSP(or ADSC) and are differentiated into two kinds of operations; All byte write operation and individual byte write operation. All byte write occurs by enabling GW(independent of BW and WEx.), and individual byte write is performed only when GW is high and BW is low. In K7B803625M, a 256Kx36 organization, WEa controls DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and DQPb, WEc controls DQc0 ~ DQc7 and DQPc and WEd controls DQd0 ~ DQd7 and DQPd. CS1 is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded. ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address increases internally for the next access of the burst when ADV is sampled low. Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is Low, linear burst sequence is selected. And this pin is High, Interleaved burst sequence is selected.
BURST SEQUENCE TABLE
LBO PIN HIGH First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 0 1 1 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3 A0 0 1 0 1
(Interleaved Burst)
Case 4 A1 1 1 0 0 A0 1 0 1 0
Fourth Address
BQ TABLE
LBO PIN LOW First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 1 1 0 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3 A0 0 1 0 1 A1 1 0 0 1
(Linear Burst)
Case 4 A0 1 0 1 0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
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November 1999 Rev 5.0
K7B803625M K7B801825M
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1 H L L L L L L L X H X H X H X H CS2 X L X L X H H H X X X X X X X X CS2 X X H X H L L L X X X X X X X X ADSP ADSC X L L X X L H H H X H X H X H X L X X L L X L L H H H H H H H H ADV X X X X X X X X L L L L H H H H
256Kx36 & 512Kx18 Synchronous SRAM
WRITE X X X X X X L H H H L L H H L L
CLK
ADDRESS ACCESSED N/A N/A N/A N/A N/A External Address External Address External Address Next Address Next Address Next Address Next Address Current Address Current Address Current Address Current Address
OPERATION Not Selected Not Selected Not Selected Not Selected Not Selected Begin Burst Read Cycle Begin Burst Write Cycle Begin Burst Read Cycle Continue Burst Read Cycle Continue Burst Read Cycle Continue Burst Write Cycle Continue Burst Write Cycle Suspend Burst Read Cycle Suspend Burst Read Cycle Suspend Burst Write Cycle Suspend Burst Write Cycle
Notes : 1. X means "Dont Care".
2. The rising edge of clock is symbolized by .
3. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE( x36)
GW H H H H H H L BW H L L L L L X WEa X H L H H L X WEb X H H L H L X WEc X H H H L L X WEd X H H H L L X OPERATION READ READ WRITE BYTE a WRITE BYTE b WRITE BYTE c and d WRITE ALL BYTEs WRITE ALL BYTEs
Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
WRITE TRUTH TABLE(x18)
GW H H H H H L BW H L L L L X WEa X H L H L X WEb X H H L L X OPERATION READ READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ALL BYTEs
Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
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November 1999 Rev 5.0
K7B803625M K7B801825M
ASYNCHRONOUS TRUTH TABLE
Operation Sleep Mode Read Write Deselected ZZ H L L L L OE X L H X X
256Kx36 & 512Kx18 Synchronous SRAM
I/O STATUS High-Z DQ High-Z Din, High-Z High-Z
Notes 1. X means "Dont Care". 2. ZZ pin is pulled down internally 3. For write cycles that following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 4. Sleep Mode means power down state of which stand-by current does not depend on cycle time. 5. Deselected means power down state of which stand-by current depends on cycle time.
ABSOLUTE MAXIMUM RATINGS*
PARAMETER Voltage on VDD Supply Relative to VSS Voltage on VDDQ Supply Relative to VSS Voltage on Input Pin Relative to VSS Voltage on I/O Pin Relative to VSS Power Dissipation Storage Temperature Operating Temperature Storage Temperature Range Under Bias SYMBOL VDD VDDQ VIN VIO PD TSTG TOPR TBIAS RATING -0.3 to 4.6 VDD -0.3 to 4.6 -0.3 to VDDQ+0.5 1.4 -65 to 150 0 to 70 -10 to 85 UNIT V V V V W C C C
*Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O(0C TA 70C)
PARAMETER Supply Voltage Ground SYMBOL VDD VDDQ VSS MIN 3.135 3.135 0 Typ. 3.3 3.3 0 MAX 3.465 3.465 0 UNIT V V V
OPERATING CONDITIONS at 2.5V I/O(0C TA 70C)
PARAMETER Supply Voltage Ground SYMBOL VDD VDDQ VSS MIN 3.135 2.375 0 Typ. 3.3 2.5 0 MAX 3.465 2.9 0 UNIT V V V
CAPACITANCE*(TA=25C, f=1MHz)
PARAMETER Input Capacitance Output Capacitance
*Note : Sampled not 100% tested.
SYMBOL CIN COUT
TEST CONDITION VIN=0V VOUT=0V
MIN -
MAX 6 8
UNIT pF pF
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November 1999 Rev 5.0
K7B803625M K7B801825M
256Kx36 & 512Kx18 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0C to +70C)
Parameter Input Leakage Current(except ZZ) Output Leakage Current Symbol IIL IOL Test Conditions VDD=Max ; VIN=VSS to VDD Output Disabled, Vout=VSS to VDDQ -75 Operating Current ICC Device Selected, IOUT=0mA, ZZVIL , Cycle Time tCYC Min -85 -90 -10 -75 Device deselected, IOUT=0mA, ISB Standby Current ISB1 ISB2 Output Low Voltage(3.3V I/O) Output High Voltage(3.3V I/O) Output Low Voltage(2.5V I/O) Output High Voltage(2.5V I/O) Input Low Voltage(3.3V I/O) Input High Voltage(3.3V I/O) Input Low Voltage(2.5V I/O) Input High Voltage(2.5V I/O) VOL VOH VOL VOH VIL VIH VIL VIH All Inputs=fixed (VDD-0.2V or 0.2V) Device deselected, IOUT=0mA, ZZVDD-0.2V, f=Max, All InputsVIL or VIH IOL=8.0mA IOH=-4.0mA IOL=1.0mA IOH=-1.0mA ZZVIL, f=Max, All Inputs0.2V or VDD-0.2V -85 -90 -10 Device deselected, IOUT=0mA, ZZ0.2V, f=0, Min -2 -2 2.4 2.0 -0.3* 2.0 -0.3* 1.7 Max +2 +2 350 330 300 260 140 130 120 120 30 30 0.4 0.4 0.8 VDD+0.5** 0.7 VDD+0.5** mA mA V V V V V V V V 3 3 mA mA 1,2 Unit A A Notes
Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing. 2. Data states are all zero. 3. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V VIH
VSS
VSS-1.0V 20% tCYC(MIN)
TEST CONDITIONS
(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70C)
PARAMETER Input Pulse Level(for 3.3V I/O) Input Pulse Level(for 2.5V I/O) Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O) Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O) Input and Output Timing Reference Levels for 3.3V I/O Input and Output Timing Reference Levels for 2.5V I/O Output Load VALUE 0 to 3.0V 0 to 2.5V 1.0V/ns 1.0V/ns 1.5V VDDQ/2 See Fig. 1
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November 1999 Rev 5.0
K7B803625M K7B801825M
Output Load(A)
256Kx36 & 512Kx18 Synchronous SRAM
Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) RL=50 +3.3V for 3.3V I/O /+2.5V for 2.5V I/O VL=1.5V for 3.3V I/O VDDQ/2 for 2.5V I/O Dout 353 / 1538 319 / 1667
Dout Zo=50
30pF*
5pF*
* Including Scope and Jig Capacitance Fig. 1
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0C to +70C)
PARAMETER Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width Clock Low Pulse Width Address Setup to Clock High Address Status Setup to Clock High Data Setup to Clock High Write Setup to Clock High (GW, BW, WEX) Address Advance Setup to Clock High Chip Select Setup to Clock High Address Hold from Clock High Address Status Hold from Clock High Data Hold from Clock High Write Hold from Clock High (GW, BW, WEX) Address Advance Hold from Clock High Chip Select Hold from Clock High ZZ High to Power Down ZZ Low to Power Up SYMBOL tCYC tCD tOE tLZC tOH tLZOE tHZOE tHZC tCH tCL tAS tSS tDS tWS tADVS tCSS tAH tSH tDH tWH tADVH tCSH tPDS tPUS -75 MIN 8.5 2.5 2.5 0 2.5 2.5 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 2 2 MAX 7.5 3.5 3.5 4.0 MIN 10 2.5 2.5 0 3.0 3.0 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 2 2 -85 MAX 8.5 3.5 3.5 5.0 MIN 10 2.5 2.5 0 3.0 3.0 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 2 2 -90 MAX 9.0 3.5 3.5 5.0 MIN 12 2.5 2.5 0 3.0 3.0 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 2 2 -10 MAX 10 3.5 4.0 6.0 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cycle cycle
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
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November 1999 Rev 5.0
TIMING WAVEFORM OF READ CYCLE
tCH tCL
CLOCK
tSH tCYC
K7B803625M K7B801825M
tSS
ADSP
tSS tSH
ADSC
tAH A2 tWS tWH A3
BURST CONTINUED WITH NEW BASE ADDRESS
tAS
ADDRESS
A1
256Kx36 & 512Kx18 Synchronous SRAM
- 12 tCSH tADVS tADVH
(ADV INSERTS WAIT STATE)
WRITE
tCSS
CS
ADV
OE
tOE tHZOE tCD tOH Q2-1 Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 Q1-1 tHZC Q3-4
tLZOE
Data Out
Dont Care Undefined
November 1999 Rev 5.0
NOTES : WRITE = L means GW = L, or GW = H, BW = L, WEx.= L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
TIMING WAVEFORM OF WRTE CYCLE
tCH tCL
CLOCK
tSH tCYC
K7B803625M K7B801825M
tSS
ADSP
tSS tSH
ADSC
tAH A1 A2
(ADSC EXTENDED BURST)
tAS
ADDRESS
A3 tWS tWH
WRITE
tCSH
256Kx36 & 512Kx18 Synchronous SRAM
- 13 (ADV SUSPENDS BURST)
tCSS
CS
tADVS tADVH
ADV
OE
tDS D1-1 tLZOE Q0-4
Dont Care Undefined
tDH D2-2 D2-2 D2-3 D2-4 D3-1 D3-2 D3-3 D3-4
Data In
D2-1
November 1999 Rev 5.0
Data Out
Q0-3
TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED, ADSC=HIGH)
tCH tCL
CLOCK
tSS tSH tCYC
K7B803625M K7B801825M
ADSP tAS
tAH A2 A3 tWS tWH A1
ADDRESS
WRITE
256Kx36 & 512Kx18 Synchronous SRAM
- 14 tADVS tADVH tDS D2-1 tOE tHZOE tLZOE Q1-1 Q3-1 tCD tLZC tDH
CS
ADV
OE
Data In
tHZC
tOH Q3-2 Q3-3 Q3-4
Data Out
November 1999 Rev 5.0
Dont Care Undefined
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED, ADSP=HIGH)
tCH tCL
CLOCK
tSH tCYC
K7B803625M K7B801825M
tSS
ADSC
tWS A2 tWS tWH A3 A4 A5 A6 A7 A8 tWH A9
ADDRESS
A1
WRITE
tCSH
tCSS
CS
256Kx36 & 512Kx18 Synchronous SRAM
- 15 tOE tHZOE Q1-1 Q2-1 Q3-1 Q4-1 tDS D5-1 D6-1
ADV
OE
tCD Q8-1 tDH D7-1 tOH Q9-1
tLZOE
Data Out
Data In
Dont Care Undefined
November 1999 Rev 5.0
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSP CONTROLLED, ADSC=HIGH)
tCH tCL
CLOCK
tCYC
K7B803625M K7B801825M
tSS
tSH
ADSP
tAS A2 A3 A4 A5 A6 A7 A8 tAH A9
ADDRESS
A1
WRITE
tCSS
tCSH
256Kx36 & 512Kx18 Synchronous SRAM
- 16 tHZOE Q1-1 Q2-1 Q3-1 Q4-1 tDS D5-1 D6-1 tDH
CS
ADV
OE
tCD Q8-1 tOH Q9-1
tOE
tLZOE
Data Out
Data In
D7-1
Dont Care Undefined
November 1999 Rev 5.0
TIMING WAVEFORM OF POWER DOWN CYCLE
tCH tCL
CLOCK
tSH tCYC
tSS
K7B803625M K7B801825M
ADSP
ADSC
tAH A2 tWS tWH
tAS
ADDRESS
A1
WRITE
tCSH
tCSS
256Kx36 & 512Kx18 Synchronous SRAM
- 17 tOE tHZC Q1-1 tPDS
ZZ Setup Cycle Sleep State
CS
ADV
OE
tLZOE tHZOE
Data In
D2-1
D2-2
Data Out
tPUS
ZZ Recovery Cycle Normal Operation Mode
ZZ
Dont Care Undefined
November 1999 Rev 5.0
K7B803625M K7B801825M
APPLICATION INFORMATION
DEPTH EXPANSION
256Kx36 & 512Kx18 Synchronous SRAM
The Samsung 256Kx36 Synchronous Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.
Data Address
I/O[0:71] A[0:18] A[18] A[0:17] Address Data CS2 CS2 CLK A[18] A[0:17] Address Data CS2 CS2 256Kx36 SB SRAM (Bank 0) CLK ADSC WEx OE CS1 ADSP ADV ADSP 256Kx36 SB SRAM (Bank 1)
CLK
Microprocessor
Address CLK Cache Controller
ADSC WEx OE CS1 ADV
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH)
CLOCK
tSS tSH
ADSP
tAS tAH A2 tWS tWH
ADDRESS [0:n] WRITE
A1
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
tADVS tADVH
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
ADV
OE
tOE tHZC Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC Q2-1
*Notes : n = 14 32K depth , 16 128K depth , 18 512K depth 15 64K depth 17 256K depth
Data Out (Bank 0) Data Out (Bank 1)
tLZOE
Q2-2
Q2-3
Q2-4
Dont Care Undefined
- 18 -
November 1999 Rev 5.0
K7B803625M K7B801825M
APPLICATION INFORMATION
DEPTH EXPANSION
256Kx36 & 512Kx18 Synchronous SRAM
The Samsung 512Kx18 Synchronous Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic. Data Address I/O[0:71] A[0:19] A[19] A[0:18] A[19] A[0:18]
CLK
Address Data CS2 CS2
Address Data CS2 CS2
Microprocessor
Address CLK Cache Controller
CLK ADSC WEx OE CS1 ADV
512Kx18 SB SRAM (Bank 0)
CLK ADSC WEx OE CS1
512Kx18 SB SRAM (Bank 1)
ADSP
ADV
ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH)
CLOCK
tSS tSH
ADSP
tAS tAH A2 tWS tWH
ADDRESS [0:n] WRITE
A1
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
tADVS tADVH
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
ADV
OE
tOE tHZC Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC Q2-1
*Notes : n = 14 32K depth , 16 128K depth , 18 512K depth , 15 64K depth 17 256K depth 19 1M depth
Data Out (Bank 0) Data Out (Bank 1)
tLZOE
Q2-2
Q2-3
Q2-4
Dont Care Undefined
- 19 -
November 1999 Rev 5.0
K7B803625M K7B801825M
PACKAGE DIMENSIONS
100-TQFP-1420A
22.00 20.00
0.30 0.20
256Kx36 & 512Kx18 Synchronous SRAM
Units ; millimeters/Inches
0~8
0.10 0.127 + 0.05 -
16.00
0.30
14.00 0.20
0.10 MAX
(0.83) 0.50 0.10 #1 0.65 0.30 0.10 0.10 MAX (0.58)
1.40 0.50 0.10
0.10
1.60 MAX
0.05 MIN
- 20 -
November 1999 Rev 5.0
K7B803625M K7B801825M
119BGA PACKAGE DIMENSIONS
14.000.10
256Kx36 & 512Kx18 Synchronous SRAM
1.27
1.27
22.000.10 Indicator of Ball(1A) Location
20.500.10
C1.00
C0.70 0.7500.15
0.600.10 12.500.10
1.50REF 0.600.10 NOTE : 1. All Dimensions are in Millimeters. 2. Solder Ball to PCB Offset : 0.10 MAX. 3. PCB to Cavity Offset : 0.10 MAX.
- 21 -
November 1999 Rev 5.0

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