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19-3232; Rev 0; 4/04
KIT ATION EVALU E AILABL AV
Dual, 8-Bit, 165Msps, Current-Output DAC
General Description
The MAX5852 dual, 8-bit, 165Msps digital-to-analog converter (DAC) provides superior dynamic performance in wideband communication systems. The device integrates two 8-bit DAC cores, and a 1.24V reference. The MAX5852 supports single-ended and differential modes of operation. The dynamic performance is maintained over the entire 2.7V to 3.6V power-supply operating range. The analog outputs support a -1.0V to +1.25V compliance voltage. The MAX5852 can operate in interleaved data mode to reduce the I/O pin count. This allows the converter to be updated on a single, 8-bit bus. The MAX5852 features digital control of channel gain matching to within 0.4dB in sixteen 0.05dB steps. Channel matching improves sideband suppression in analog quadrature modulation applications. The onchip 1.24V bandgap reference includes a control amplifier that allows external full-scale adjustments of both channels through a single resistor. The internal reference can be disabled and an external reference may be applied for high-accuracy applications. The MAX5852 features full-scale current outputs of 2mA to 20mA and operates from a 2.7V to 3.6V single supply. The DAC supports three modes of power-control operation: normal, low-power standby, and complete power-down. In power-down mode, the operating current is reduced to 1A. The MAX5852 is packaged in a 40-pin thin QFN with exposed paddle (EP) and is specified for the extended (-40C to +85C) temperature range. Pin-compatible, lower speed, and higher resolution versions are also available. Refer to the MAX5853 (10 bit, 80Msps), the MAX5851 (8 bit, 80Msps), and the MAX5854 (10 bit, 165Msps) data sheets for more information. See Table 4. 8-Bit, 165Msps Dual DAC Low Power 190mW with IFS = 20mA at fCLK = 165MHz 2.7V to 3.6V Single Supply Full Output Swing and Dynamic Performance at 2.7V Supply Superior Dynamic Performance 67dBc SFDR at fOUT = 40MHz Programmable Channel Gain Matching Integrated 1.24V Low-Noise Bandgap Reference Single-Resistor Gain Control Interleaved Data Mode Single-Ended and Differential Clock Input Modes Miniature 40-Pin Thin QFN Package, 6mm x 6mm EV Kit Available--MAX5852 EV Kit
Features
MAX5852
Ordering Information
PART TEMP RANGE PIN-PACKAGE 40 Thin QFN-EP* MAX5852ETL -40C to +85C *EP = Exposed paddle.
Pin Configuration
OUTNA OUTNB OUTPA OUTPB
TOP VIEW
AGND AVDD
AGND
AVDD
40 39 38 37 36 35 34 33 32 31
REFO
30 CVDD 29 CGND 28 CLK 27 CVDD 26 CLKXN 25 CLKXP 24 DCE 23 CW 22 N.C. 21 N.C.
DA7/PD DA6/DACEN DA5/IDE DA4/REN DA3/G3 DA2/G2 DA1/G1 DA0/G0 N.C. N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 EP
Applications
Communications VSAT, LMDS, MMDS, WLAN, Point-to-Point Microwave Links Wireless Base Stations Quadrature Modulation Direct Digital Synthesis (DDS) Instrumentation/ATE
MAX5852
DB7
DB5
DB4
DVDD
DB3
DGND
DB2
DB1
REFR
DB6
THIN QFN
________________________________________________________________ Maxim Integrated Products
DB0
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual, 8-Bit, 165Msps, Current-Output DAC MAX5852
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ...................................................... -0.3V to +4V DVDD to DGND...................................................... -0.3V to +4V CVDD to CGND...................................................... -0.3V to +4V AVDD to DVDD .............................................................-4V to +4V AVDD to CVDD .............................................................-4V to +4V DVDD to CVDD .............................................................-4V to +4V AGND to DGND.....................................................-0.3V to +0.3V AGND to CGND.....................................................-0.3V to +0.3V DGND to CGND ....................................................-0.3V to +0.3V DA7-DA0, DB7-DB0, CW, DCE to DGND ...............-0.3V to +4V CLK to CGND ..........................................-0.3V to (CVDD + 0.3V) CLKXN, CLKXP to CGND.........................................-0.3V to +4V REFR, REFO to AGND .............................-0.3V to (AVDD + 0.3V) OUTPA, OUTNA to AGND ..........(AVDD - 4.8V) to (AVDD + 0.3V) OUTPB, OUTNB to AGND ..........(AVDD - 4.8V) to (AVDD + 0.3V) Maximum Current into Any Pin (excluding power supplies) ..........................................50mA Continuous Power Dissipation (TA = +70C) 40-Pin QFN (derate 26.3mW/C above +70C) .........2105mW Operating Temperature Range ..........................-40C to +85C Storage Temperature Range ..............................65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA +25C guaranteed by production test. TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error (See Also Gain Error Definition Section) Gain-Error Temperature Drift DYNAMIC PERFORMANCE fCLK = 165MHz, AOUT = -1dBFS Spurious-Free Dynamic Range to Nyquist SFDR fCLK = 100MHz, AOUT = -1dBFS fCLK = 25MHz, AOUT = -1dBFS fOUT = 10MHz fOUT = 20MHz fOUT = 40MHz fOUT = 10MHz fOUT = 20MHz fOUT = 30MHz fOUT = 1MHz 64.3 67 66 67 67 67 66 64 68 70 67 63 dBc dBc dBc N INL DNL VOS GE Internal reference (Note1) External reference Internal reference External reference RL = 0 Guaranteed monotonic, RL = 0 8 -0.25 -0.15 -0.1 -10 -5.5 0.05 0.05 0.02 1.5 0.7 150 100 +0.25 +0.15 +0.1 +8 +5.0 Bits LSB LSB LSB %FSR ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
fCLK = 165MHz, fOUT = 10MHz, AOUT = -1dBFS, span = 10MHz Spurious-Free Dynamic Range Within a Window SFDR fCLK = 100MHz, fOUT = 5MHz, AOUT = -1dBFS, span = 4MHz fCLK = 25MHz, fOUT = 1MHz, AOUT = -1dBFS, span = 2MHz Multitone Power Ratio to Nyquist MTPR 8 tones at 400kHz spacing, fCLK = 78MHz, fOUT = 15MHz to 18.2MHz
2
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Dual, 8-Bit, 165Msps, Current-Output DAC
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA +25C guaranteed by production test. TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER Multitone Spurious-Free Dynamic Range Within a Window SYMBOL CONDITIONS 8 tones at 2.1MHz spacing, fCLK = 165MHz, fOUT = 28.3MHz to 45.2MHz, span = 50MHz fCLK = 165MHz, AOUT = -1dBFS Total Harmonic Distortion to Nyquist (2nd- Through 8th-Order Harmonics Included) THD fCLK = 100MHz, AOUT = -1dBFS fCLK = 25MHz, AOUT = -1dBFS Output Channel-to-Channel Isolation Channel-to-Channel Gain Mismatch Channel-to-Channel Phase Mismatch fOUT = 10MHz fOUT = 10MHz, G[3:0] = 1000 fOUT = 10MHz fCLK = 165MHz, fOUT = 10MHz, IFS = 20mA Signal-to-Noise Ratio to Nyquist SNR fCLK = 165MHz, fOUT = 10MHz, IFS = 5mA fCLK = 65MHz, fOUT = 10MHz, IFS = 20mA fCLK = 65MHz, fOUT = 10MHz, IFS = 5mA Maximum DAC Conversion Rate Glitch Impulse Output Settling Time Output Rise Time Output Fall Time ANALOG OUTPUT Full-Scale Output Current Range Output Voltage Compliance Range Output Leakage Current REFERENCE Internal-Reference Output Voltage VREFO REN = 0 1.13 1.24 1.32 V Shutdown or standby mode IFS 2 -1.00 -5 20 +1.25 +5 mA V A tS To 0.1% error band (Note 3) 10% to 90% (Note 3) 90% to 10% (Note 3) fDAC Interleaved mode disabled, IDE = 0 Interleaved mode enabled, IDE = 1 165 82.5 fOUT = 10MHz fOUT = 20MHz fOUT = 40MHz fOUT = 10MHz fOUT = 20MHz fOUT = 30MHz fOUT = 1MHz MIN TYP 61 -71 -72 -72 -71 -74 -69 -69 90 0.025 0.05 50.5 50.5 51 51 200 100 5 12 2.2 2.2 Msps pV*s ns ns ns dB dB dB Degrees dBc MAX UNITS dBc
MAX5852
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3
Dual, 8-Bit, 165Msps, Current-Output DAC MAX5852
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA +25C guaranteed by production test. TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER Internal-Reference Supply Rejection Internal-Reference OutputVoltage Temperature Drift Internal-Reference Output Drive Capability External-Reference Input Voltage Range Current Gain IFS/IREF 0.65 x DVDD 0.3 x DVDD -1 3 0.65 x CVDD 0.3 x CVDD -1 3 0.9 x CVDD 0.1 x CVDD +1 +1 LOGIC INPUTS (DA7-DA0, DB7-DB0, CW) Digital Input-Voltage High Digital Input-Voltage Low Digital Input Current Digital Input Capacitance VIH VIL IIN CIN V V A pF TCVREFO SYMBOL CONDITIONS AVDD varied from 2.7V to 3.6V REN = 0 REN = 0 REN = 1 0.10 MIN TYP 0.5 50 50 1.2 32 1.32 MAX UNITS mV/V ppm/C A V mA/mA
SINGLE-ENDED CLOCK INPUT/OUTPUT AND DCE INPUT (CLK, DCE) Digital Input-Voltage High Digital Input-Voltage Low Digital Input Current Digital Input Capacitance Digital Output-Voltage High Digital Output-Voltage Low VIH VIL IIN CIN VOH VOL DCE = 1 DCE = 1 DCE = 1 DCE = 1 DCE = 0, ISOURCE = 0.5mA, Figure 1 DCE = 0, ISINK = 0.5mA, Figure 1 V V A pF V V
DIFFERENTIAL CLOCK INPUTS (CLKXP/CLKXN) Differential Clock Input Internal Bias Differential Clock Input Swing Clock Input Impedance POWER REQUIREMENTS Analog Power-Supply Voltage Digital Power-Supply Voltage Clock Power-Supply Voltage AVDD DVDD CVDD 2.7 2.7 2.7 3 3 3 3.6 3.6 3.6 V V V Measured single ended 0.5 5 CVDD/2 V V k
4
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Dual, 8-Bit, 165Msps, Current-Output DAC
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA +25C guaranteed by production test. TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS IFS = 20mA, single-ended clock mode Analog Supply Current (Note 2) IAVDD IFS = 20mA, differential clock mode IFS = 2mA, single-ended clock mode IFS = 2mA, differential clock mode Digital Supply Current (Note 2) IDVDD IFS = 20mA, single-ended clock mode IFS = 20mA, differential clock mode Single-ended clock mode (DCE = 1) Differential clock mode (DCE = 0) IAVDD + IDVDD+ ICVDD IAVDD + IDVDD + ICVDD Single-ended clock mode (DCE = 1) Total Power Dissipation (Note 2) PTOT Differential clock mode (DCE = 0) Standby Shutdown TIMING CHARACTERISTICS (Figure 5, Figure 6) Propagation Delay DAC Data to CLK Rise/Fall Setup Time (Note 4) DAC Data to CLK Rise/Fall Hold Time (Note 4) Control Word to CW Rise Setup Time Control Word to CW Rise Hold Time CW High Time CW Low Time DACEN = 1 to VOUT Stable Time (Coming Out of Standby) tDCS tDCH tCS tCW tCWH tCWL tSTB Single-ended clock mode (DCE = 1) Differential clock mode (DCE = 0) Single-ended clock mode (DCE = 1) Differential clock mode (DCE = 0) 1.2 2.7 0.8 -0.5 2.5 2.5 5 5 3 1 Clock cycles ns ns ns ns ns ns s IFS = 20mA IFS = 2mA IFS = 20mA IFS = 2mA MIN TYP 43.2 43.2 5 5 6 6 13.8 23.7 3.1 1 190 74 219 104 9.3 0.003 11.1 mW 209 3.7 16.5 6.9 mA MAX 46 mA UNITS
MAX5852
Clock Supply Current (Note 2) Total Standby Current Total Shutdown Current
ICVDD ISTANDBY ISHDN
mA mA A
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5
Dual, 8-Bit, 165Msps, Current-Output DAC MAX5852
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, fDAC = 165Msps, differential clock, external reference, VREF = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA +25C guaranteed by production test. TA < +25C guaranteed by design and characterization. Typical values are at TA = +25C.)
PARAMETER PD = 0 to VOUT Stable Time (Coming Out of Power-Down) Maximum Clock Frequency at CLKXP/CLKXN Input Clock High Time Clock Low Time CLKXP Rise to CLK Output Rise Delay CLKXP Fall to CLK Output Fall Delay SYMBOL tSHDN fCLK tCXH tCXL tCDH tCDL CLKXP or CLKXN input CLKXP or CLKXN input DCE = 0 DCE = 0 165 CONDITIONS MIN TYP 500 200 1.5 1.5 2.7 2.7 MAX UNITS s MHz ns ns ns ns
Note 1: Note 2: Note 3: Note 4:
Including the internal reference voltage tolerance and reference amplifier offset. fDAC = 165Msps, fOUT = 10MHz. Measured single-ended with 50 load and complementary output connected to AGND. Guaranteed by design, not production tested.
0.5mA
TO OUTPUT PIN 5pF
1.6V
0.5mA
Figure 1. Load Test Circuit for CLK Outputs
6
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Dual, 8-Bit, 165Msps, Current-Output DAC MAX5852
Typical Operating Characteristics
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, differential clock, IFS = 20mA, differential output, TA = +25C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 165MHz)
MAX5852 toc01
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 100MHz)
MAX5852 toc02
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 25MHz)
75 70 65 SFDR (dBc) 60 55 50 45 40 35 30 -12dBFS -6dBFS 0dBFS
MAX5852 toc03
80 75 70 65 SFDR (dBc) 0dBFS
80 75 70 65 SFDR (dBc) 60 55 50 45 40 35 30 -12dBFS 0dBFS -6dBFS
80
60 55 50 45 40 35 30 0 10 20 30 40 50 60 70 80 90 fOUT (MHz) -12dBFS -6dBFS
0
5
10 15 20 25 30 35 40 45 50 fOUT (MHz)
0
2
4
6
8
10
12
14
fOUT (MHz)
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 200MHz)
MAX5852 toc04
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 165MHz)
MAX5852 toc05
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 165MHz)
75 70 65 SFDR (dBc) AVDD = DVDD = CVDD = 3.6V AVDD = DVDD = CVDD = 3.3V
MAX5852 toc06
80 75 70 65 SFDR (dBc) 0dBFS -6dBFS
80 75 70 65 SFDR (dBc) 60 55 50 45 40 35 30 IFS = 5mA IFS = 20mA IFS = 10mA
80
60 55 50 45 40 35 30 0 10 20 30 40 50 60 70 80 90 100 fOUT (MHz) -12dBFS
60 55 50 45 40 35 30
AVDD = DVDD = CVDD = 3V AVDD = DVDD = CVDD = 2.7V
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
fOUT (MHz)
fOUT (MHz)
SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE (fCLK = 165MHz)
MAX5852 toc07
TWO-TONE INTERMODULATION DISTORTION (fCLK = 165MHz, 2.5MHz WINDOW)
-10 -20 AMPLITUDE (dBm) -30 -40 -50 -60 -70 -80 -90 -100 2fOUT1 - fOUT2 2fOUT2 - fOUT1 fOUT2 fOUT1 fOUT1 = 4.8541MHz, fOUT2 = 5.0555MHz
MAX5852 toc08
80 75 70 65 SFDR (dBc) 60 55 50 45 40 35 30 -40 -15 10 35 60
0
85
3.6
3.9
4.2
4.5
4.8
5.1
5.4
5.7
6.0
TEMPERATURE (C)
fOUT (MHz)
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7
Dual, 8-Bit, 165Msps, Current-Output DAC MAX5852
Typical Operating Characteristics (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, differential clock, IFS = 20mA, differential output, TA = +25C, unless otherwise noted.)
EIGHT-TONE SFDR PLOT (fCLK = 165MHz, 50MHz WINDOW)
MAX5852 toc09
SINGLE-TONE SFDR (fCLK = 165MHz, 10MHz WINDOW)
MAX5852 toc10
SINGLE-TONE SFDR (fCLK = 100MHz, 4MHz WINDOW)
-10 -20 AMPLITUDE (dBm) -30 -40 -50 -60 -70 -80 -90 -100 fOUT = 4.8667MHz AOUT = -1dBFS
MAX5852 toc11
0 -10 -20 AMPLITUDE (dBm) -30 -40 -50 -60 -70 -80 -90 -100 11.7 fT1 fT8 fT4 fT3 fT2 fT5 fT6 fT7
0 -10 -20 AMPLITUDE (dBm) -30 -40 -50 -60 -70 -80 -90 -100 fOUT = 9.1667MHz AOUT = -1dBFS
0
31.7 41.7 51.7 61.7 fOUT (MHz) fT5 = 38.7002MHz fT1 = 28.3667MHz fT6 = 41.0333MHz fT2 = 30.3667MHz fT7 = 43.2000MHz fT3 = 32.7001MHz fT8 = 45.3667MHz fT4 = 34.5333MHz
21.7
4
5
6
7
8
9
10 11 12 13 14
2.8
3.3
3.8
4.3
4.8
5.3
5.8
6.3
6.8
fOUT (MHz)
fOUT (MHz)
SINGLE-TONE SFDR (fCLK = 25MHz, 2MHz WINDOW)
MAX5852 toc12
SINGLE-TONE SFDR (fCLK = 165MHz, NYQUIST WINDOW)
0 -10 -20 -30 AMPLITUDE (dBm) -40 -50 -60 -70 -80 -90 -100 -110 -120 fOUT = 9.9159MHz AOUT = -1dBFS
MAX5852 toc13 MAX5852 toc15
0 -10 -20 AMPLITUDE (dBm) -30 -40 -50 -60 -70 -80 -90 -100 0.1 0.5 0.9 1.3 1.7 fOUT = 0.9667MHz AOUT = -1dBFS
2.1
0.5
8.25MHz/div fOUT (MHz)
82.5
fOUT (MHz)
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
0.15 0.10 DNL (LSB) INL (LSB) 0.05 0 -0.05 -0.10 -0.15 -0.20 0 32 64 96 128 160 192 224 256 DIGITAL INPUT CODE
MAX5852 toc14
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE
0.10 0.08 0.05 0.03 0 -0.03 -0.05 -0.08 -0.10 0 32 64 96 128 160 192 224 256 DIGITAL INPUT CODE
0.20
8
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Dual, 8-Bit, 165Msps, Current-Output DAC MAX5852
Typical Operating Characteristics (continued)
(AVDD = DVDD = CVDD = 3V, AGND = DGND = CGND = 0, external reference, differential clock, IFS = 20mA, differential output, TA = +25C, unless otherwise noted.)
POWER DISSIPATION vs. CLOCK FREQUENCY (fOUT = 10MHz, AOUT = 0dBFS)
MAX5852 toc16
POWER DISSIPATION vs. SUPPLY VOLTAGES (fCLK = 165MHz, fOUT = 10MHz)
MAX5852 toc17
REFERENCE VOLTAGE vs. SUPPLY VOLTAGES
1.21480 REFERENCE VOLTAGE (V) 1.21470 1.21460 1.21450 1.21440 1.21430 1.21420 1.21410
MAX5852 toc18
230 220 POWER DISSIPATION (mW) 210 200 190 180 170 160 150 20 45 70 95 fCLK (MHz) 120 145 SINGLE-ENDED CLOCK DRIVE DIFFERENTIAL CLOCK DRIVE
260 250 POWER DISSIPATION (mW) 240 230 220 210 200 190 180 170 160 SINGLE-ENDED CLOCK DRIVE DIFFERENTIAL CLOCK DRIVE
1.21490
170
2.70
2.85
3.00
3.15
3.30
3.45
3.60
1.21400 2.70
2.85
3.00
3.15
3.30
3.45
3.60
SUPPLY VOLTAGES (V)
SUPPLY VOLTAGES (V)
REFERENCE VOLTAGE vs. TEMPERATURE
1.218 REFERENCE VOLTAGE (V) 1.216 1.214 1.212 1.210 1.208 1.206 1.204 -40 -15 10 35 60 85 TEMPERATURE (C)
MAX5852 toc19
DYNAMIC RESPONSE RISE TIME
MAX5852 toc20
1.220
100mV/div
10ns/div
DYNAMIC RESPONSE FALL TIME
MAX5852 toc21
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY (fCLK = 165MHz)
75 70 65 SFDR (dBc) 60 55 50 45 40 35 30 SINGLE-ENDED CLOCK DRIVE 0 10 20 30 40 50 60 70 80 90 -12dBFS -6dBFS 0dBFS
MAX5852 toc22
80
100mV/div
10ns/div
fOUT (MHz)
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9
Dual, 8-Bit, 165Msps, Current-Output DAC MAX5852
Pin Description
PIN 1 2 3 4 5 6 7 8 9, 10, 21, 22 11 12 13 14 15 16 17 18 19 20 23 24 NAME DA7/PD DA5/IDE DA4/REN DA3/G3 DA2/G2 DA1/G1 DA0/G0 N.C. DB7 DB6 DB5 DB4 DB3 DVDD DGND DB2 DB1 DB0 CW DCE Channel A Input Data Bit 7 (MSB)/Power-Down Channel A Input Data Bit 5/Interleaved Data Enable Channel A Input Data Bit 4/Reference Enable. Setting REN = 0 enables the internal reference. Setting REN = 1 disables the internal reference. Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 3 Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 2 Channel A Input Data Bit 1/Channel A Gain Adjustment Bit 1 Channel A Input Data Bit 0 (LSB)/Channel A Gain Adjustment Bit 0 No Connection. Do not connect to these pins. Channel B Input Data Bit 7 (MSB) Channel B Input Data Bit 6 Channel B Input Data Bit 5 Channel B Input Data Bit 4 Channel B Input Data Bit 3 Digital Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details. Digital Ground Channel B Input Data Bit 2 Channel B Input Data Bit 1 Channel B Input Data Bit 0 (LSB) Active-Low Control Word Write Pulse. The control word is latched on the rising edge of CW. Active-Low Differential Clock Enable Input. Drive DCE low to enable differential clock inputs CLKXP and CLKXN. Drive DCE high to disable the differential clock inputs and enable the singleended CLK input. Positive Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP and CLKXN are disabled. Connect CLKXP to CGND when the differential clock is disabled. Negative Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP and CLKXN are disabled. Connect CLKXN to CVDD when the differential clock is disabled. Clock Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details. Single-Ended Clock Input/Output. With the differential clock disabled (DCE = 1), CLK becomes a singleended conversion clock input. With the differential clock enabled (DCE = 0), CLK is a single-ended output that mirrors differential clock inputs CLKXP and CLKXN. See the Clock Modes section for more information on CLK. Clock Ground Reference Input/Output. REFO serves as a reference input when the internal reference is disabled. If the internal 1.24V reference is enabled, REFO serves as an output for the internal reference. When the internal reference is enabled, bypass REFO to AGND with a 0.1F capacitor. FUNCTION
DA6/DACEN Channel A Input Data Bit 6/DAC Enable Control
25 26 27, 30
CLKXP CLKXN CVDD
28
CLK
29 31
CGND REFO
10
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Dual, 8-Bit, 165Msps, Current-Output DAC
Pin Description (continued)
PIN 32 33, 39 34 35 36, 40 37 38 -- NAME REFR AVDD OUTNB OUTPB AGND OUTNA OUTPA EP FUNCTION Full-Scale Current Adjustment. To set the output full-scale current, connect an external resistor RSET between REFR and AGND. The output full-scale current is equal to 32 x VREFO/RSET. Analog Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details. Channel B Negative Analog Current Output Channel B Positive Analog Current Output Analog Ground Channel A Negative Analog Current Output Channel A Positive Analog Current Output Exposed Paddle. Connect EP to the common point of all ground planes.
MAX5852
Detailed Description
DVDD DGND CW DA0/G0 DA2/G2 DA3/G3 DA4/REN DA5/IDE DA6/DACEN DA7/PD DACA INPUT REGISTER CONTROL WORD DA1/G1 DIGITAL POWER MANAGEMENT ANALOG POWER MANAGEMENT AVDD AGND
MAX5852
8-BIT DACA
OUTPA OUTNA
CHANNEL A GAIN CONTROL INPUT DATA INTERLEAVER
G0 G1 G2 G3
The MAX5852 dual, high-speed, 8-bit, current-output DAC provides superior performance in communication systems requiring low-distortion analog-signal reconstruction. The MAX5852 combines two DACs and an onchip 1.24V reference (Figure 2). The current outputs of the DACs can be configured for differential or singleended operation. The full-scale output current range is adjustable from 2mA to 20mA to optimize power dissipation and gain control. The MAX5852 accepts an input data and a DAC conversion rate of 165MHz. The inputs are latched on the rising edge of the clock whereas the output latches on the following rising edge. The MAX5852 features three modes of operation: normal, standby, and power-down (Table 2). These modes allow efficient power management. In power-down, the MAX5852 consumes only 1A of supply current. Wake-up time from standby mode to normal DAC operation is 3s.
IDE
DB0 DACB INPUT REGISTER DB1 DB2 DB3 DB4 DB5 DB6 DB7 DCE CLKXP CLKXN CLK CVDD CGND
OPERATING MODE CONTROLLER
DACEN PD OUTPB OUTNB
Programming the DAC
8-BIT DACB
REFO CLOCK DISTRIBUTION 1.24V REFERENCE AND CONTROL AMPLIFIER REFR
CLOCK POWER MANAGEMENT
RSET REN AGND
An 8-bit control word routed through channel A's data port programs the gain matching, reference, and the operational mode of the MAX5852. The control word is latched on the rising edge of CW. CW is independent of the DAC clock. The DAC clock can always remain running, when the control word is written to the DAC. Table 1 and Table 2 represent the control word format and function. The gain on channel A can be adjusted to achieve gain matching between two channels in a user's system. The gain on channel A can be adjusted from -0.4dB to +0.35dB in steps of 0.05dB by using bits G3 to G0 (see Table 3).
Figure 2. Simplified Diagram ______________________________________________________________________________________ 11
Dual, 8-Bit, 165Msps, Current-Output DAC MAX5852
Table 1. Control Word Format and Function
MSB PD CONTROL WORD PD DACEN IDE DACEN IDE REN G3 FUNCTION Power-Down. The part enters power-down mode if PD = 1. DAC Enable. When DACEN = 0 and PD = 0, the part enters standby mode. Interleaved Data Mode. IDE = 1 enables the interleaved data mode. In this mode, digital data for both channels is applied through channel A in a multiplexed fashion. Channel B data is written on the falling edge of the clock signal and channel A data is written on the rising edge of the clock signal. Reference Enable Bit. REN = 0 activates the internal reference. REN = 1 disables the internal reference and requires the user to apply an external reference between 0.1V to 1.32V. Bit 3 (MSB) of Gain Adjust Word Bit 2 of Gain Adjust Word Bit 1 of Gain Adjust Word Bit 0 (LSB) of Gain Adjust Word G2 G1 LSB G0
REN G3 G2 G1 G0
Table 2. Configuration Modes
MODE Normal operation; noninterleaved inputs; internal reference active Normal operation; noninterleaved inputs; internal reference disabled Normal operation; interleaved inputs; internal reference disabled Standby Power-down Power-up PD DACEN IDE REN
Device Power-Up and States of Operation
At power-up, the MAX5852's default configuration is internal reference, noninterleaved input mode with a gain of 0dB and a fully operational converter. In shutdown, the MAX5852 consumes only 1A of supply current, and in standby the current consumption is 3.1mA. Wake-up time from standby mode to normal operation is 3s.
0
1
0
0
0
1
0
1
Clock Modes
The MAX5852 allows both single-ended CMOS and differential clock mode operation, and supports update rates of up to 165Msps. These modes are selected through an active-low control line called DCE. In singleended clock mode (DCE = 1), the CLK pin functions as an input, which accepts a user-provided single-ended clock signal. Data is written to the converter on the rising edge of the clock. The DAC outputs (previous data) are updated simultaneously on the same edge. If the DCE pin is pulled low, the MAX5852 will operate in differential clock mode. In this mode, the clock signal has to be applied to differential clock input pins CLKXP/CLKXN. The differential input accepts an input range of 0.5VP-P and a common-mode range of 1V to (CVDD - 0.5V), making the part ideal for low- input amplitude clock drives. CLKXP/CLKXN also help to minimize the jitter, and allow the user to connect a crystal oscillator directly to MAX5852.
0 0 1 0
1 0 X 1
1 X X X
1 X X X
X = Don't care.
Table 3. Gain Difference Setting
GAIN ADJUSTMENT ON CHANNEL A (dB) +0.4 0 -0.35 G3 0 1 1 G2 0 0 1 G1 0 0 1 G0 0 0 1
12
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Dual, 8-Bit, 165Msps, Current-Output DAC MAX5852
OPTIONAL EXTERNAL BUFFER FOR HEAVIER LOADS
AVDD 10F 0.1F AGND AVDD 1.24V BANDGAP REFERENCE REFO CURRENTSOURCE ARRAY IFS
MAX4040
1.24V BANDGAP REFERENCE REFO
REN = 0
REN = 1
MAX6520
CCOMP* REFR AGND IREF = VREF RSET AGND RSET IREF CURRENTSOURCE ARRAY IFS EXTERNAL 1.2V REFERENCE
REFR
IREF
MAX5852
AGND RSET
*COMPENSATION CAPACITOR (CCOMP 100nF)
MAX5852
AGND
Figure 3. Setting IFS with the Internal 1.24V Reference and the Control Amplifier
Figure 4. MAX5852 with External Reference
The CLK pin now becomes an output, and provides a single-ended replica of the differential clock signal, which may be used to synchronize the input data. Data is written to the device on the rising edge of the CLK signal.
External Reference
To disable the internal reference of the MAX5852, set REN = 1. Apply a temperature-stable, external reference to drive the REFO pin and set the full-scale output (Figure 4). For improved accuracy and drift performance, choose a fixed-output voltage reference such as the 1.2V, 25ppm/C MAX6520 bandgap reference.
Internal Reference and Control Amplifier
The MAX5852 provides an integrated 50ppm/C, 1.24V, low-noise bandgap reference that can be disabled and overridden with an external reference voltage. REFO serves either as an external reference input or an integrated reference output. If REN =0, the internal reference is selected and REFO provides a 1.24V (50A) output. Buffer REFO with an external amplifier, when driving a heavy load. The MAX5852 also employs a control amplifier designed to simultaneously regulate the full-scale output current (I FS ) for both outputs of the devices. Calculate the output current as: IFS = 32 IREF where I REF is the reference output current (I REF = VREFO / RSET) and IFS is the full-scale output current. R SET is the reference resistor that determines the amplifier output current of the MAX5852 (Figure 3). This current is mirrored into the current-source array where IFS is equally distributed between matched current segments and summed to valid output current readings for the DACs.
Detailed Timing
The MAX5852 accepts an input data and the DAC conversion rate of up to 165Msps. The input latches on the rising edge of the clock, whereas the output latches on the following rising edge. Figure 5 depicts the write cycle of the two DACs in noninterleaved mode. The MAX5852 can also operate in an interleaved data mode. Programming the IDE bit with a high level activates this mode (Tables 1 and 2). In interleaved mode, data for both DAC channels is written through input port A. Channel B data is written on the falling edge of the clock signal and then channel A data is written on the following rising edge of the clock signal. Both DAC outputs (channel A and B) are updated simultaneously on the next following rising edge of the clock. In interleaved data mode, the maximum input data rate per channel is half of the rate in noninterleaved mode. The interleaved data mode is attractive for applications where lower data rates are acceptable and interfacing on a single 8-bit bus is desired (Figure 6).
13
______________________________________________________________________________________
Dual, 8-Bit, 165Msps, Current-Output DAC MAX5852
tCXH CLKXN CLKXP tCDL tCDH CLK OUTPUT CW tCXL
tCWL
tDCS
tDCH
tCS
tCW
DA0-DA7
DACA - 1
DACA
DACA + 1
DACA + 2
CONTROL WORD
DACA + 3
OUTNA DACA - 1 OUTPA tDCS DB0-DB7 DACB - 1 tDCH DACB + 1 DACB + 2 XXXX DACB + 3 DACA DACA + 1 DACA + 2
XXXX
(CONTROL WORD DATA)
DACA + 3
DACB
OUTNB DACB - 1 OUTPB DACB DACB + 1 DACB + 2 XXXX DACB + 3
Figure 5. Timing Diagram for Noninterleaved Data Mode (IDE = 0)
tCXL CLKXN CLKXP tCDH tCDL
tCXH
CLK OUTPUT CW
tCWL
tDCS
tDCH
tDCS
tDCH
tCS
tCW
DA0-DA7
DACA
DACB + 1
DACA + 1
CONTROL WORD
DACB + 2
DACA + 2
OUTNA DACA - 1 OUTPA OUTNB DACB - 1 OUTPB DACB DACB + 1 DACA DACA + 1
Figure 6. Timing Diagram for Interleaved Data Mode (IDE = 1) 14 ______________________________________________________________________________________
Dual, 8-Bit, 165Msps, Current-Output DAC MAX5852
AVDD DVDD CVDD 50 OUTPA DA0-DA7
AVDD DVDD CVDD VOUTA, SINGLE ENDED DA0-DA7 100 50 OUTPA
1/2 MAX5852
OUTNA 50
1/2 MAX5852
OUTNA 50
8
8
50 OUTPB DB0-DB7
VOUTB, SINGLE ENDED DB0-DB7
50 OUTPB
1/2
100
1/2 MAX5852
OUTNB 50
8
MAX5852
OUTNB 50 AGND DGND CGND
8
AGND DGND CGND
Figure 7. Application with Output Transformer (Coilcraft TTWB3010-1) Performing Differential-to-Single-Ended Conversion
Figure 8. Application with DC-Coupled Differential Outputs
Applications Information
Differential-to-Single-Ended Conversion
The MAX5852 exhibits excellent dynamic performance to synthesize a wide variety of modulation schemes, including high-order QAM modulation with OFDM. Figure 7 shows a typical application circuit with output transformers performing the required differential-to-single-ended signal conversion. In this configuration, the MAX5852 operates in differential mode, which reduces even-order harmonics, and increases the available output power.
extend from 10MHz down to several hundred kilohertz. DC-coupling is desirable to eliminate long discharge time constants that are problematic with large, expensive coupling capacitors. Analog quadrature upconverters have a DC common-mode input requirement of typically 0.7V to 1.0V. The MAX5852 differential I/Q outputs can maintain the desired full-scale level at the required 0.7V to 1.0V DC common-mode level when powered from a single 2.85V (5%) supply. The MAX5852 meets this low-power requirement with minimal reduction in dynamic range while eliminating the need for level-shifting resistor networks.
Differential DC-Coupled Configuration
Figure 8 shows the MAX5852 output operating in differential, DC-coupled mode. This configuration can be used in communications systems employing analog quadrature upconverters and requiring a baseband sampling, dual-channel, high-speed DAC for I/Q synthesis. In these applications, information bandwidth can
Power Supplies, Bypassing, Decoupling, and Layout
Grounding and power-supply decoupling strongly influence the MAX5852 performance. Unwanted digital crosstalk can couple through the input, reference, power-supply, and ground connections, which can affect dynamic specifications, like signal-to-noise ratio
15
______________________________________________________________________________________
Dual, 8-Bit, 165Msps, Current-Output DAC
or spurious-free dynamic range. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5852. Observe the grounding and power-supply decoupling guidelines for highspeed, high-frequency applications. Follow the powersupply and filter configuration to realize optimum dynamic performance. Use of a multilayer printed circuit (PC) board with separate ground and power-supply planes is recommended. Run high-speed signals on lines directly above the ground plane. The MAX5852 has separate analog and digital ground buses (AGND, CGND, and DGND, respectively). Provide separate analog, digital, and clock ground sections on the PC board with only one point connecting the three planes. The ground connection points should be located underneath the device and connected to the exposed paddle. Run digital signals above the digital ground plane and analog/clock signals above the analog/clock ground plane. Digital signals should be kept away from sensitive analog, clock, and reference inputs. Keep digital signal paths short and metal trace lengths matched to avoid propagation delay and data skew mismatch. The MAX5852 includes three separate power-supply inputs: analog (AV DD ), digital (DV DD ), and clock (CVDD). Use a single linear regulator power source to branch out to three separate power-supply lines (AVDD, DV DD , CV DD ) and returns (AGND, DGND, CGND). Filter each power-supply line to the respective return line using LC filters comprising ferrite beads and 10F capacitors. Filter each supply input locally with 0.1F ceramic capacitors to the respective return lines. Note: To maintain the dynamic performance of the Electrical Characteristics, ensure the voltage difference between DV DD , AV DD , and CV DD does not exceed 150mV. In this package, the data converter die is attached to an EP lead frame with the back of this frame exposed at the package bottom surface, facing the PC board side of the package. This allows a solid attachment of the package to the PC board with standard infrared (IR) flow soldering techniques. A specially created land pattern on the PC board, matching the size of the EP (4.1mm 4.1mm), ensures the proper attachment and grounding of the DAC. Designing vias* into the land area and implementing large ground planes in the PC board design allows for highest performance operation of the DAC. Use an array of 3 3 vias (0.3mm diameter per via hole and 1.2mm pitch between via holes) for this 40-pin thin QFN-EP package (package code: T4066-1).
MAX5852
Dynamic Performance Parameter Definitions
Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of all essential harmonics (within a Nyquist window) of the input signal to the fundamental itself. This can be expressed as: 2 2 2 2 V2 + V3 + V4 ... + ...VN THD = 20 x log V1
where V1 is the fundamental amplitude, and V2 through VN are the amplitudes of the 2nd through Nth order harmonics. The MAX5852 uses the first seven harmonics for this calculation. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of their next-largest spectral component. SFDR is usually measured in dBc with respect to the carrier frequency amplitude or in dBFS with respect to the DAC's full-scale range. Depending on its test condition, SFDR is observed within a predefined window or to Nyquist. Multitone Power Ratio (MTPR) A series of equally spaced tones are applied to the DAC with one tone removed from the center of the range. MTPR is defined as the worst-case distortion (usually a 3rd-order harmonic product of the fundamental frequencies), which appears as the largest spur at the frequency of the missing tone in the sequence. This test can be performed with any number of input tones; however, four and eight tones are among the most common test conditions for CDMA- and GSM/EDGE-type applications.
Thermal Characteristics and Packaging
Thermal Resistance 40-lead thin QFN-EP: JA = 38C/W The MAX5852 is packaged in a 40-pin thin QFN-EP package, providing greater design flexibility, increased thermal efficiency, and optimized AC performance of the DAC. The EP enables the implementation of grounding techniques, which are necessary to ensure highest performance operation.
*Vias connect the land pattern to internal or external copper planes. 16 ______________________________________________________________________________________
Dual, 8-Bit, 165Msps, Current-Output DAC
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc of either output tone to the worst 3rd-order (or higher) IMD products. Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles to its new output value to within the converter's specified accuracy. Glitch Impulse A glitch is generated when a DAC switches between two codes. The largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011...111 to 100...000. This occurs due to timing variations between the bits. The glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. The glitch impulse is usually specified in pV-s.
MAX5852
Static Performance Parameter Definitions
Integral Nonlinearity (INL) Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between an actual step height and the ideal value of 1 LSB. A DNL error specification no more negative than -1 LSB guarantees monotonic transfer function.
Table 4. Part Selection Table
PART MAX5851 MAX5852 MAX5853 MAX5854 SPEED (Msps) 80 165 80 165 RESOLUTION 8 bit, dual 8 bit, dual 10 bit, dual 10 bit, dual
Offset Error
Offset error is the current flowing from positive DAC output when the digital input code is set to zero. Offset error is expressed in LSBs. Gain Error A gain error is the difference between the ideal and the actual full-scale output current on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. The ideal current is defined by reference voltage at 32 x VREFO / RSET.
Chip Information
TRANSISTOR COUNT: 9035 PROCESS: CMOS
______________________________________________________________________________________
17
Dual, 8-Bit, 165Msps, Current-Output DAC MAX5852
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN 6x6x0.8.EPS
E2 L e
D2 D D/2 k
C L
b D2/2
E/2 E2/2 E (NE-1) X e
C L
k
e (ND-1) X e
L
e L
C L C L
L1 L
e
A1
A2
A
PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
E
1
2
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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