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Aug. 2003 Edition 0.2
ASSP Dual Serial Input PLL Frequency Synthesizer(Small Package)
MB15F74UV
DESCRIPTION
The Fujitsu MB15F74UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000MHz and a 2000MHz prescalers. A 64/65 or a 128/129 for the 4000MHz prescaler, and a 32/33 or a 64/65 for the 2000MHz prescaler can be selected for the prescaler that enables pulse swallow operation. The latest BiCMOS process is used, as a result a supply current is typically 9.0mA typ. at 3.0V. The supply voltage range is from 2.7V to 3.6V. A refined charge pump supplies well-balanced output current with 1.5mA and 6mA selectable by serial data. The data format and the function as fast locking are same as the previous one MB15F74UL. The new package(BCC18) decreases a mount area of MB15F74UV about 50% comparing with the former BCC20(for dual PLL, MB15F74UL). MB15F74UV is ideally suited for wireless mobile communications, such as W-CDMA.
FEATURES
* Very small package: BCC18 (2.4*2.7*0.45mm) * High frequency operation: RF synthesizer : 4000MHz max IF synthesizer : 2000MHz max * Low power supply voltage: VCC = 2.7 to 3.6 V * Ultra Low power supply current : ICC = 9.0 mA typ. (VCC = 3.0V, Ta=25C, SW=0 in RF, IF locking state) * Direct power saving function : Power supply current in power saving mode Typ. 0.1 A(Vcc=3.0V, Ta=25C), Max. 10 A(Vcc=3.0V) * Dual modulus prescaler : 4000MHz prescaler(64/65 or 128/129) / 2000MHz prescaler(32/33 or 64/65) * Serial input 14-bit programmable reference divider: R = 3 to 16,383 * Serial input programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 3 to 2,047 * On-chip phase comparator for fast lock and low noise * On-chip phase control for phase comparator * Operating temperature: Ta = -40 to 85C * Sireal data format compatible with MB15F74UL
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i im
y. ar n
18-pad, Plastic BCC
(LCC-18P-M05)
1
MB15F74UV
PIN ASSIGNMENT
Aug. 2003 Edition 0.2
Clock OSCIN Data GND finIF XfinIF GNDIF VccIF DoIF 1 2 3 4 5 6 7 8 9 TOP VIEW 18 17 16 15 14 13 12 11 10 LE finRF XfinRF GNDRF VCCRF
DoRF
PSIF PSRF LD/fout
LCC-18P-M05
2
Aug. 2003 Edition 0.2
MB15F74UV
PIN DESCRIPTIONS
Pin No. 1 2 3 4 5 6 7 Pin name GND finIF XfinIF GNDIF VccIF DoIF PSIF I/O I I O I Descriptions Ground for OSC input buffer and the shift registor circuit. Prescaler input pin for the IF-PLL section. Connection to an external VCO should be AC coupling. Prescaler complimentary input for the IF-PLL section. This pin should be grounded via a capacitor. Ground for the IF-PLL section. Power supply voltage input pin for the IF-PLL section(except for the charge pump circuit), the shift register and the oscillator input buffer. When power is OFF, latched data of IF-PLL is lost. Charge pump output for the IF-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. Power saving mode control for the IF-PLL section. This pin must be set at "L" Power-ON. (Open is prohibited.) PSIF = "H" ; Normal mode PSIF = "L" ; Power saving mode Lock detect signal output(LD)/ phase comparator monitoring outut (fout). The output signal is selected by a LDS bit in a serial data. LDS bit = "1" ; outputs fout signal LDS bit = "0" ; outputs LD sihnal Power saving mode control for the RF-PLL section. This pin must be set at "L" Power-ON. (Open is prohibited.) PSRF = "H" ; Normal mode PSRF = "L" ; Power saving mode Charge pump output for the RF-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. Power supply voltage input pin for the RF-PLL section(except for the charge pump circuit). Ground for the RF-PLL section. Prescaler complimentary input for the RF-PLL section. This pin should be grounded via a capacitor. Prescaler input pin for the RF-PLL. Connction to an external VCO should be AC coupling. Load enable signal input (with the schmitt trigger circuit.) When LE is set "H", data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. Serial data input (with the schmitt trigger circuit.) A data is transferred to the corresponding latch (IF-ref counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in a serial data. Clock input for the 23-bit shift register (with the schmitt trigger circuit.) One bit data is shifted into the shift register on a rising edge of the clock. The programmable reference divider input. TCXO should be connected with a AC coupling capacitor.
8
LD/fout
O
9 10 11 12 13 14 15
PSRF DoRF VccRF GNDRF XfinRF finRF LE
I O I I I
16
Data
I
17 18
Clock OSCIN
I I
3
MB15F74UV
BLOCK DIAGRAM
VCCIF 5 GNDIF 4
Aug. 2003 Edition 0.2
PSIF 7
Intermittent mode control
(IF-PLL)
3-bit latch LDS SWIF FCIF
7-bit latch Binary 7-bit swallow counter
(IF-PLL)
11-bit latch Binary 11-bit programmable counter(IF-PLL)
fpIF
Phase comp.
(IF-PLL)
Charge Current pump Switch (IF-PLL)
6 DoIF
Prescaler
finIF 2 XfinIF 3 (IF-PLL)
32/22,64/65 2-bit latch T1 T2 14-bit latch Binary 14-bit programmable ref. counter(IF-PLL)
frIF
1-bit latch C/P setting current
Lock Det.
(IF-PLL) LDIF
OSCin 18
Fast lock
tuning
AND OR Binary 14-bit programmable ref. counter(RF-PLL) 14-bit latch
frRF
T1
T2
C/P setting current 1-bit latch Lock Det.
(RF-PLL)
Selector LD frIF frRF fpIF fpRF
8 LD/fout
2-bit latch
finRF 14 XfinRF 13
Prescaler
(RF-PLL)
64/65, 128/129 LDS SWRF FCRF Intermittent mode control
(RF-PLL)
Binary 7-bit swallow counter
(RF-PLL)
Binary 11-bit programmable counter(RF-PLL) 11-bit latch
Phase comp.
(RF-PLL)
Fast lock
tuning
PSRF 9
fpRF
Charge Current pump Switch (RF-PLL)
10 DoRF
3-bit latch
7-bit latch
LE 15
Schmitt circuit
Latch selector
Data 16
Schmitt circuit Schmitt circuit
C N 1
C N 2
Clock 17
23-bit shift register
1 GND
11 VccRF
12 GNDRF
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Aug. 2003 Edition 0.2
MB15F74UV
ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol VCC VI VO VDO Tstg Rating -0.5 to +4.0 -0.5 to VCC +0.5 GND to Vcc GND to Vcc -55 to +125 Unit V V V V C LD/fout Do Remark
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Input voltage Operating temperature Symbol VCC VI Ta Value Min. 2.7 GND -40 Typ. 3.0 - - Max. 3.6 VCC +85 Unit V V C Remark VCCRF = VCCIF
Handling Precautions
(1) VccRF and,VccIF must supply equal voltage. Even if either RF-PLL or IF-PLL is not used, power must be supplied to both VccRF and VccIF to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. (2) To protect against damage by electrostatic discharge, note the following handling precautions: -Store and transport devices in conductive containers. -Use properly grounded workstations, tools, and equipment. -Turn off power before inserting or removing this device into or from a socket. -Protect leads with conductive sheet, when transporting a board mounted device.
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MB15F74UV
ELECTRICAL CHARACTERISTICS
Aug. 2003 Edition 0.2
(VCC = 2.7 to 3.6 V, Ta = -40 to +85C) Parameter Symbol ICCIF Power supply current*1 ICCRF Power saving current*9 finIF*3 Operating frequency finRF*3 OSCIN finIF Input sensitivity finRF OSCIN "H" level Input voltage "L" level Input voltage "H" level Input voltage PS "L" level Input voltage "H" level Input current "L" level Input current "H" level output voltage "L" level output voltage "H" level output voltage "L" level output voltage High impedance cutoff current "H"level Output current "L" level Output current DoIF DoRF DoIF DoRF LD/fout Data, Clock, LE, PS LD/fout VIL IIH*4 IIL*4 VOH VOL VDOH VDOL IOFF IOH*4 IDOL - - - VCC=2.7V, IOH=-1mA VCC=2.7V, IOL=1mA VCC=2.7V, IDOH=-0.5mA VCC=2.7V, IDOL=0.5mA VCC=2.7V, VOFF=0.5V to Vp-0.5V VCC = 2.7V VCC = 2.7V Data, Clock, LE IPSIF IPSRF finIF finRF fosc PfinIF PfinRF VOSC VIH VIL VIH Condition finIF=2000MHz VccIF=3.0V finRF=2500MHz VccRF=3.0V PSIF=PSRF= "L" PSIF=PSRF= "L" IF PLL RF PLL - IF PLL, 50 system RF PLL, 50 system - Schmitt trigger input Schmitt trigger input - Value Min. 2.1 5.7 - - 200 2000 3 -15 -10 0.5 Vcc x 0.7+0.4 - Vccx 0.7 - -1.0 -1.0 Vcc - 0.4 - Vcc - 0.4 - - - 1.0 Typ. 2.5 6.5 0.1*2 0.1 - - - - - - - - - - - - - - - - - - -
*2
Max. 3.2 8.4 10 10 2000 4000 40 +2 +2 1.5 - Vccx 0.3-0.4 - Vccx 0.3 +1.0 +1.0 - 0.4 - 0.4 2.5 -1.0 -
Unit mA mA A A MHz MHz MHz dBm dBm Vp-p
V
V
A
V
V
nA mA
(Continued)
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Aug. 2003 Edition 0.2
MB15F74UV
(VCC = 2.4 to 3.6 V, Ta = -40 to +85C) Parameter Symbol Condition VCC=2.7 V VDOH=Vcc /2 Ta= 25C VCC=2.7 V VDOL=Vcc/2 Ta= 25C VDO=Vcc/2 0.5V < VDO < Vcc-0.5V -40C < Ta < 85 C, VDO=Vcc/2 CS bit ="1" CS bit ="0" CS bit ="1" CS bit ="0" Value Min. -8.2 -2.2 4.1 0.8 - - - Typ. -6.0 -1.5 6.0 1.5 3 10 5 Max. -4.1 -0.8 8.2 2.2 - - - % % % mA Unit
"H"level Output current DoTX*8 DoRX "L" level Output current IDOL/IDOH Charge pump current rate vs VDO vs Ta
IDOH*4
IDOL IDOMT*5 IDOVD*6 IDOTA*7
*1: *2: *3: *4: *5: *6: *7: *8: *9:
Conditions; fosc=12.8MHz, Ta = 25C, SW="L" in locking state. Vcc=2.7V, fosc=12.8MHz, Ta = 25C, in power saving mode. AC coupling. 1000pF capacitor is connected under the condition of min. operating frequency. The symbol "-"(minus) means direction of current flow. Vcc=3.0V, Ta=25C ( ||I3| - |I4|| ) / [( |I3| + |I4| )/2] x 100(%) Vcc=3.0V, Ta=25C [( ||I2| - |I1|| ) /2 ] / [( |I1| + |I2| )/2] x 100(%) (Applied to each IDOL, IDOH) Vcc=3.0V, [(||IDO(85C)| - |IDO(-40C)||) /2] / [(|IDO(85C)| + |IDO(-40C)|) /2] x 100(%) (Applied to each IDOL, IDOH) When Charge pump current is measured, set LDS="0", T1="0" and T2="1". PSIF=PSRF=GND (VIL=GND and VIH=Vcc for Clock, Data, LE)
I2 I3 I1 IDOL IDOH
I4 I2 0.5 Vcc/2 Output voltage(V)
I1
Vcc-0.5
Vcc
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MB15F74UV
FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation: fVCO = {(P x N) + A} x fOSC / R fVCO: P: N: A: fOSC: R: Output frequency of external voltage controlled oscillator (VCO) Preset divide ratio of dual modulus prescaler (32 or 64 for IF-PLL, 64 or 128 for RF-PLL) Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) Preset divide ratio of binary 7-bit swallow counter (0 A 127, condition;A < N) Reference oscillation frequency Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
Aug. 2003 Edition 0.2
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL sections, programmable reference dividers of IF/RF-PLL sections are controlled individually. Serial data of binary data is entered through Data pin. On a rising edge of clock, one bit of serial data is transferred into the shift register. On a rising edge of load enable signal , the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.
Table1. Control Bit
Control bit
CN1 CN2
Destination of serial data
The programmable reference counter for the IF-PLL. The programmable reference counter for the RF-PLL. The programmable counter and the swallow counter for the IF-PLL The programmable counter and the swallow counter for the RF-PLL
0 1 0 1
0 0 1 1
Shift Register Configuration
Programmable Reference Counter
LSB Data Flow 1 C N 1 2 C N 2 3 T 1 4 T 2 5 R 1 6 R 2 7 R 3 8 R 4 9 R 5 10 R 6 11 R 7 12 R 8 13 R 9 14 R 10 15 R 11 16 R 12 17 R 13 18 R 14 19 20 C S X 21 X 22 X 23 X MSB
CN1, 2 : Control bit [Table. 1] R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383) [Table. 2] T1, 2 : LD/fout output setting bit [Table. 3] CS : Charge pump current select bit [Table. 8] X : Dummy bits(Set "0" or "1") NOTE: Data input with MSB first.
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Aug. 2003 Edition 0.2
MB15F74UV
Programmable Counter
LSB 1 C N 1 2 C N 2 3 L D S 4 S W 5 F C 6 A 1 7 A 2 8 A 3 Data Flow 9 A 4 10 A 5 11 A 6 12 A 7 13 N 1 14 N 2 15 N 3 16 N 4 17 N 5 18 N 6 19 N 7 20 N 8 21 N 9 22 N 10 MSB 23 N 11
IF/RF IF/RF
: Control bit : Divide ratio setting bits for the programmable counter (3 to 2,047) : Divide ratio setting bits for the swallow counter (0 to 127) : Divide ratio setting bit for the prescaler (32/33 or 64/65 for the SWIF, 64/65 or 128/129 for the SWRF) : Phase control bit for the phase detector(IF : FCIF, RF : FCRF) FCIF/RF LDS : LD/fout signal select bit NOTE: Data input with MSB first.
CN1, 2 N1 to N11 A1 to A7 SWIF/RF
[Table. 1] [Table. 4] [Table. 5] [Table. 6] [Table. 7] [Table. 3]
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio (R) 3 4 16383 R 14 0 0 1 R 13 0 0 1 R 12 0 0 1 R 11 0 0 1 R 10 0 0 1 R 9 0 0 1 R 8 0 0 1 R 7 0 0 1 R 6 0 0 1 R 5 0 0 1 R 4 0 0 1 R 3 0 1 1 R 2 1 0 1 R 1 1 0 1
Note: * Divide ratio less than 3 is prohibited.
Table.3 LD/fout output Selectable Bit Setting
LD/fout pin state LD output frIF fout output frRF fpIF fpRF LDS 0 0 0 1 1 1 1 T1 0 1 1 0 1 0 1 T2 0 0 1 0 0 1 1
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MB15F74UV
Table.4 Binary 11-bit Programmable Counter Data Setting
Divide ratio (N) 3 4 2047 N 11 0 0 1 N 10 0 0 1 N 9 0 0 1 N 8 0 0 1 N 7 0 0 1 N 6 0 0 1 N 5 0 0 1 N 4 0 0 1 N 3 0 1 1 N 2 1 0 1 N 1 1 0 1
Aug. 2003 Edition 0.2
Note: * Divide ratio less than 3 is prohibited.
Table.5 Binary 7-bit Swallow Counter Data Setting
Divide ratio (N) 0 1 127 A 7 0 0 1 A 6 0 0 1 A 5 0 0 1 A 4 0 0 1 A 3 0 0 1 A 2 0 0 1 A 1 0 1 1
Note: * Divide ratio (A) range = 0 to 127
Table. 6 Prescaler Data Setting
SW = "1" Prescaler divide ratio IF-PLL RF-PLL 32/33 64/65 SW = "0" 64/65 128/129
Table. 7 Phase Comparator Phase Switching Data Setting
FCIF,RF = 1 fr > fp fr = fp fr < fp VCO polarity H Z L
1
FCIF,RF = 0 L Z H 2
VCO Output Frequency
1
DoIF,RF
Note: * Z = High-impedance * Depending upon the VCO and LPF polarity, FC bit should be set.
2
VCO Input Voltage
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Aug. 2003 Edition 0.2
MB15F74UV
Table. 8 Charge Pump Current Setting
CS 1 0 Current value + 6.0 mA + 1.5 mA
4. Power Saving Mode (Intermittent Mode Control Circuit) Table 9. PS Pin Setting
PS pin H L Normal mode Power saving mode Status
The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the single PLL, the lock detector, LD, remains high, indicating a locked condition. For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table. Setting the PS pin high, releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. Note: When power (VCC) is first applied, the device must be in standby mode.
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MB15F74UV
Note: * PS pin must be set at "L" for Power ON.
Aug. 2003 Edition 0.2
OFF
tv > 1s Vcc
ON
Clock Data LE tps > 100ns PS
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power ON (2) Set serial data 1s later after power supply remains stable(Vcc > 2.2V). (3) Relase power saving mode (PS: L H) 100nS later after setting serial data.
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Aug. 2003 Edition 0.2
MB15F74UV
SERIAL DATA INPUT TIMING
1st data Control bit Invalid data 2nd data
Data
MSB
LSB
Clock
LE t1 t7 t2 t3 t4 t5 t6 On the rising edge of the clock, one bit of data is transferred into the shift register.
Parameter
t1 t2 t3 t4
Min.
20 20 30 30
Typ.
- - - -
Max.
- - - -
Unit
ns ns ns ns
Parameter
t5 t6 t7
Min.
100 20 100
Typ.
- - -
Max.
- - -
Unit
ns ns ns
Note: LE should be "L" when the data is transferred into the shift register.
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MB15F74UV
PHASE DETECTOR OUTPUT WAVEFORM
Aug. 2003 Edition 0.2
frIF/RF
fpIF/RF
tWU LD (FC bit = 1) H DoIF/RF Z
tWL
L
(FC bit = 0) DoIF/RF Z
LD Output Logic Table
IF-PLL section
Locking state / Power saving state Locking state / Power saving state Unlocking state Unlocking state
RF-PLL section
Locking state / Power saving state Unlocking state Locking state / Power saving state Unlocking state
LD output
H L L L
Note: * Phase error detection range = -2 to +2 * Pulses on DoIF/RF signals are output to prevent dead zone. * LD output becomes low when phase error is tWU or more. * LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. * tWU and tWL depend on OSCin input frequency as follows. tWU > 2/fosc: i.e. tWU > 156.3ns when foscin = 12.8 MHz tWL < 4/fosc: i.e. tWL < 312.5ns when foscin = 12.8 MHz
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Aug. 2003 Edition 0.2
MB15F74UV
TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCin)
S.G
Controller
(Divide ratio setting)
50
S.G 1000pF OSCIN Clock Data 50 GND finIF XfinIF 1000pF GNDIF VccIF DoIF
S.G
1 2 3
18
17
16
15 14 13
LE finRF XfinRF GNDRF VccRF DoRF
50
MB15F74UV
4 5 6 7 8 9 12 11 10
1000pF
PSIF LD/fout PSRF VccRF 0.1 0.1
Oscilloscope
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MB15F74UV
APPLICATION EXAMPLE
Aug. 2003 Edition 0.2
1000pF
TCXO
From controller
OSCIN Clock Data GND 1000pF finIF XfinIF 1000pF GNDIF VccIF DoIF
1 2 3 4 5 6
18
17
16
15 14 13
LE 1000pF finRF XfinRF GNDRF VccRF DoRF 0.1 1000pF
MB15F74UV
12 11
7
8
9
10
PSIF LD/fout PSRF
0.1
LPF Lock Det. LPF
VCO
Output
VCO
Output
Clock, Data, LE: Schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation when open-circuited in the input).
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Aug. 2003 Edition 0.2
MB15F74UV
PACKAGE DIMENSION
BCC18(LCC-18P-M05)
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