 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Freescale Semiconductor Technical Data Document Number: MC33793 Rev 13.0, 11/2006 Distributed System Interface (DSI) Sensor Interface The 33793 is a slave Distributed System Interface (DSI) device that is optimized as a sensor interface. The device contains circuits to power sensors such as accelerometers and to digitize the analog level from the sensor. The device is controlled by commands over the DSI bus and returns measured data over the bus. Features * Conforms to DSI Specification Version 1 * 4-Channel, 8-Bit Analog-to-Digital Converter (ADC) * 4 Pins Configurable as Analog or Logic Inputs or as Logic Outputs * Provides Regulated +5.0 V Output for Sensor Power from Bus * Additional High-Drive Logic Output * Undervoltage Fault Detection and Signaling * On-Board Clock (No External Elements Required) * Field-Programmable Address * Default and Field-Programmable as a DSI Daisy Chain Device * Recognizes Reverse Initialization for Open Bus Fault Tolerance * Detects Short to Battery on Bus Switch and Prevents Its Closure * Pb-Free Packaging Designated by Suffix Code EF 33793/A DISTRIBUTED SYSTEM INTERFACE SCALE 2:1 D SUFFIX EF SUFFIX (Pb-FREE) 98ASB42566B 16-PIN SOICN ORDERING INFORMATION Device MC33793D/R2 MCZ33793EF/R2 MCZ33793AEF/R2 -40C to 150C 16 SOICN Temperature Range (TJ) Package 33790 GND DSIO X-Y Accelerometer Error Test X Y GND VCC 33793 BUSIN BUSRTN I/O0 I/O1 I/O2 I/O3 BUSOUT H_Cap REGOUT LOGOUT AGND Multiple DSI Slaves 33793 BusIN Figure 1. 33793 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. (c) Freescale Semiconductor, Inc., 2006. All rights reserved. DEVICE VARIATIONS DEVICE VARIATIONS Table 1. Device Variations Freescale Part No. MCZ33793EF/R2 MCZ33793AEF/R2 Other Significant Device Variations Existing capacity Capacity expansion 33793 2 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM HCAP Rectifiers BUSIN Bus Switch 0 - 35 V Bi-Directional Forward Receiver Data Response Current 0 -11 mA 7.0 mA/S Received Message from MCU Oscillator 4.0 MHz DataOut <3:0> BUSOUT Reverse Receiver Data Frame Frame BUSRTN Bandgap Reference Bandgap Reference Bus Return Logic Command Decode State Machine Response Generation 4 LOGOUT Power Management 5.0 V Regulator BG Reference Bias Currents Supply Comparators POR Logic Out High Current Buffer I/O Buffers DataOut <0> IO0 IO1 IO2 IO3 DataOut <1> Address A<3:0> 4 Bits NVM DataOut <2> I/O0 I/O1 I/O2 I/O<3:0> I/O3 GND SEL DataOut <3> 4:1 MUX ADC 8 Bits Undervoltage Detector BG Figure 2. 33793 Simplified Internal Block Diagram 33793 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS PIN CONNECTIONS BUSRTN I/O0 AGND I/O1 AGND I/O3 NC I/O2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 BUSOUT NC BUSIN NC H_CAP REGOUT NC LOGOUT Figure 3. 33793 Pin Connections Table 2. 33793 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 10. Pin Number 1 2 3, 5 4 6 7, 10, 13, 15 8 Pin Name BUSRTN I/O0 AGND I/O1 I/O3 NC I/O2 Pin Function Power Input/Output Ground Input/Output Input/Output No Connect Input/Output Formal Name Bus Return Logic I/O Analog Ground Logic I/O Logic I/O No Connect Logic I/O Definition This pin provides the common return for power and signalling. This pin can be used to provide a logic level output, a logic input, or an analog-to-digital (A/D) input. This pin is the low reference level and power return for the analog-todigital converter (ADC). This pin can be used to provide a logic level output, a logic input, or an A/D input. This pin can be used to provide a logic level output, a logic input, or an A/D input. These pins have no internal connections. This pin can be used to provide a logic level output, a logic input, or an A/D input. This is a logic output with higher pull-up drive capability than the standard logic I/O. This pin provides a regulated 5.0 V output. The power is derived from the bus. A capacitor attached to this pin is charged by the bus during bus idle and supplies current to run the device and for external devices via the REGOUT pin during non-idle periods. This pin attaches to the bus and responds to initialization commands. This pin attaches to the bus and responds to reverse initialization commands. 9 11 12 LOGOUT REGOUT H_CAP Output Output Output Logic Out Regulator Output Holding Capacitor 14 16 BUSIN BUSOUT Input Output DSI Bus Input DSI Bus Output 33793 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS I/O Pin Voltage I/O Pin Current BUSIN, BUSOUT, BUSRTN, and H_CAP Voltage BUSIN, BUSOUT, BUSRTN, and H_CAP Current (Continuous) ESD Protection (1) Symbol Value Unit VIO IIO VIN IIN VESD1 VESD2 -0.3 to VREGOUT + 0.5 5.0 -0.3 to 40 250 2000 200 V mA V mA V Human Body Model Machine Model THERMAL RATINGS Storage Temperature Operating Junction Temperature Peak Package Reflow Temperature During Reflow Thermal Resistance Junction to Case (2), (3) TSTG TJ TPPRT RJC -55 to 150 -40 to 150 Note 3. 150 C C C C/W Notes 1. ESD1 performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 2. 3. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33793 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions -0.3 V VBUSIN or VBUSOUT 30 V, 5.5 V < VH_CAP < 30 V, -40C < TA < 85C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic Internal Quiescent Current Drain VH_CAP = 25 V, Logout = 0, I/O = Input BUSIN or BUSOUT to H_CAP Rectifier Voltage Drop IBUSIN or IBUSOUT = 15 mA IBUSIN or IBUSOUT = 100 mA BUSIN + BUSOUT Bias Current VBUSIN or VBUSOUT = 8.0 V, VH_CAP = 9.0 V VBUSIN or VBUSOUT = 0.5 V, VH_CAP = 25 V Rectifier Leakage Current VBUSIN or VBUSOUT = 5.0 V, VH_CAP = 25 V Reg0ut 5.5 V > VH_CAP > 25 V, IRO = 12 mA RegOut Line Regulation IRO = 12 mA, 5.5 V > VH_CAP > 25 V RegOut Load Regulation IRO = 0 to 12 mA, 5.5 V > VH_CAP > 25 V Undervoltage Lockout Proportional to unloaded VREGOUT Bus Switch Resistance VBI = 8.0 V, IBO = -80 mA (Bus Switch Active) I/O0 and I/O3 Pull-Down Current 0 < VBUSIN or VBUSOUT < 1.0 V I/O1 and I/O2 Pull-Up Current VRO < VBUSIN or VBUSOUT < VRO - 1.0 V BUSIN and BUSOUT Logic Thresholds Low High Logic Duty Cycle (assured by design) Logic 0 Logic 1 BUSIN + BUSOUT Response Current VBUSIN and/or VBUSOUT = 4.0 V ADC Code Conversion Error (INL) ADC Full-scale Error I/O Logic Input Thresholds Logic High Logic Low VIH VIL 0.7 - 0.54 0.51 - 0.3 ADCINL ADCFS DCL DCH IRSP 9.9 - - 11 - - 12.1 < 1.0 3 LSB counts VRO 10 60 33 67 40 90 mA VTHL VTHH 2.8 5.5 3.0 6.0 3.2 6.5 % IPU -7.0 -11 -13 V IPD 7.0 11 13 A RSW - 4.0 8.0 A VUVL 0.93 0.95 0.97 VRLD - 2.3 100 VRO VRLINE - 71 180 mV VREG 4.75 5.0 5.25 mV IRLKG -20 - 100 V IBIAS -100 - - - 100 20 A VRECT - - 0.75 0.9 1.0 1.2 A Symbol IQ - - 3.0 V Min Typ Max Unit mA 33793 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions -0.3 V VBUSIN or VBUSOUT 30 V, 5.5 V < VH_CAP < 30 V, -40C < TA < 85C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic I/O Logic Output Levels Output Low (IL = 1.0 mA) Output High (IL = -500 A) LOGOUT Output Levels Output Low (IL = 500 A) Output High (IL = -10 mA, 6.2 V < VH_CAP < 25 V) Output High (IL = -100 A, 6.2 V < VH_CAP < 25 V) Programming Time From Positive Edge of BUSIN or BUSOUT > VTHH on Program Command to Following Command Negative Transition < VTHH NVM BUSIN or BUSOUT Programming Voltage NVMVP VLOL VLOH1 VLOH2 TPROG 100 22.25 200 - 1000 30 V 0 4.7 - 0.2 5.0 - 0.5 5.3 VRO+0.5 ms VOL VOH 0 0.8 0.08 0.985 0.5 1.0 V VRO V Symbol Min Typ Max Unit 33793 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions -0.3 V VBUSIN or VBUSOUT 30 V, 5.5 V VH_CAP 30 V, -40C TA 85C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted. Characteristic Initialization to Bus Switch Closing Loss of Signal Reset Time Maximum Time Below Frame Threshold ADC Code Conversion Time (Go, No-Go Test) BUSIN and BUSOUT Response Current Transition Time 1.0 mA to 9.0 mA Transition, 9.0 mA to 1.0 mA BUSIN or BUSIN Timing to Response Current BUSIN or BUSOUT Negative Voltage Transition = 3.0 V to IRSPH = 7.0 mA BUSIN or BUSOUT Negative Voltage Transition = 3.0 V to IRSPL = 5.0 mA tRSPH tRSPL - - - - 3.3 3.3 tADC tITR - 7.0 10 s Symbol tBS tTO - - - - 100 27 s mA/s Min 100 Typ 150 Max 200 Unit s ms 33793 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS Frame Threshold BUSIN/BUSOUT End of Initialization Command Closed BUS Switch Open tBS Frame Threshold tTO Internal Reset Reset Figure 4. Bus Switch and Reset Timing 9.0 mA 7.0 mA 9.0 mA 5.0 mA 1.0 mA RESPONSE CURRENT tITR 1.0 mA tITR tRSPH BUSIN/BUSOUT 3.0 V 3.0 V tRSPL Figure 5. Response Current Timing 33793 Analog Integrated Circuit Device Data Freescale Semiconductor 9 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33793 is designed to be used with a sensor at a location that is remote from a centralized MCU. This device provides power, measurement, and communications between the remote sensor and the centralized MCU over a DSI bus. Sensors such as accelerometers can be powered from the regulated output of the device, and the resulting analog value from the sensor can be converted from an analog level to a digital value for transmission over the DSI bus in response to a query from the MCU. Four I/O lines can be configured by the central MCU over the DSI bus as analog inputs, digital inputs, or digital outputs. This allows more than one sensor to be remotely controlled and measured by a single 33793. Additionally, a high drive logic output is provided that can be used to power other low-power sensors. Power is passed from BUSIN or BUSOUT through onboard rectifiers to a storage capacitor (referred to as the H_CAP). The H_CAP stores energy during the highest voltage excursions of the BUSIN or BUSOUT pin (idle) and supplies energy to power the device during low excursions of BUSIN and BUSOUT. The Regulator supplies an on-board regulated voltage for internal use, and the Power on Reset (POR) circuit provides a reset signal during low-voltage conditions and during power up/down. Some current is available for low-power sensors. Data from the Central Control Unit (CCU) is applied to the BUSIN and/or BUSOUT pins as voltage levels that are sensed by the Level Detection circuitry. The Serial Decoder detects these transitions and decodes the incoming data. The Control Logic provides overall control of the 33793. It controls diagnostic testing and formats responses to commands with the message encoder. Responses are formed via a switched current source that is slew-rate controlled. The one-time programmable (OTP) memory array provides the nonvolatile storage for the pre-programmed address. It is accessed via the Read/Write NVM command. It has a built-in hardware lock that only allows one write. FUNCTIONAL PIN DESCRIPTION BUS RETURN (BUSRTN) This pin provides the common return for power and signalling. REGULATOR OUTPUT (REGOUT) This pin provides a regulated 5.0 V output. The power is derived from the bus. INPUT/OUTPUT (I/O0, I/O1, I/O2, I/O3) This pin can be used to provide a logic level output, a logic input, or an analog-to-digital (A/D) input. HOLDING CAPACITOR (H_CAP) A capacitor attached to this pin is charged by the bus during bus idle and supplies current to run the device and for external devices via the REGOUT pin during non-idle periods. ANALOG GROUND (AGND) This pin is the low reference level and power return for the analog-to-digital converter (ADC). DSI BUS INPUT (BUSIN) This pin attaches to the bus and responds to initialization commands. LOGIC OUT (LOGOUT) This is a logic output with higher pull-up drive capability than the standard logic I/O. DSI BUS OUTPUT (BUSOUT) This pin attaches to the bus and responds to reverse initialization commands. FUNCTIONAL INTERNAL BLOCK DESCRIPTION Refer to Figure 2, 33793 Internal Block Diagram, page 3, for a simplified representation of the 33793's components. voltage at H_CAP will not drop below the frame threshold during signaling. RECTIFIER This rectifier or switch peak detects the bus signal into an external capacitor attached to H_CAP. The capacitor supplies power during signaling while the input voltage is at a lower level. The voltage waveform at BUSIN and/or BUSOUT and the size of the filter capacitor at H_CAP must be such that the 33793 POR The 33793 leaves the reset state when the voltage on H_CAP rises above the Power-ON Reset threshold. TIMEOUT A timeout timer keeps track of the length of the time when the input is not in idle mode. If this time exceeds a limit, the Analog Integrated Circuit Device Data Freescale Semiconductor 10 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION part is reset. The purpose of this is to allow the part to reset itself if the connection to the master is lost or if power is removed from the system. circuit limits the rise and fall time of current loading the bus by controlling the current sinking element. SWITCHED CURRENT SOURCE 5.0 V REGULATOR The 5.0 V regulator supplies internal power for the device and also provides approximately 6.0 mA through the REGOUT pin to power an external sensor. A "1" data return bit will be signaled by turning on a fixed current source. During signaling time, the 33793 will be using power from H_CAP and not loading the bus for power. The current will be drawn from either BUSIN or BUSOUT or split between them. The split can be in any proportion as long as the total is correct. The current source is turned off whenever the bus is at Idle level. UNDERVOLTAGE DETECTOR The undervoltage detector monitors the output voltage of the 5.0 V regulator. If the REGOUT voltage drops too low for accurate A/D operation, a signal is sent to the control logic. The control logic will interpret this signal and, in response to a command, report a status indicating an undervoltage condition to have existed. When received, the command will clear the signal after having read the status. If the voltage is too low when the A/D conversion was completed, the returned value will be zero (binary 00000000). LEVEL DETECTOR The level detector contains comparators to determine if the BUSIN or BUSOUT is at idle, logic high, or logic low. The inputs from BUSIN and BUSOUT are sensed by the device so that if either side is driven by the signaling waveform while the other is not, the signaling will be detected. This circuit also provides a signal to indicate if the signal is being received on the BUSOUT pin. If a "reverse initialization" command is received, it can only be acted upon if the device is not already initialized and if the signal is present on BUSOUT. IO PINS 0 TO 3 The IO pins can serve as logic inputs, logic outputs, or analog inputs. At power-up or after a clear, the pins are all logic inputs and can be used to measure an analog level value for an analog value request command. The pins can be individually configured as logic inputs or outputs by the IO Control command. If the pin is configured as a logic output, reading the analog value will return the analog level the output is being driven to. SERIAL DECODER The Serial Decoder monitors transitions on the BUSIN or BUSOUT. When the 33793 is Idle and supplying power to itself and the external device(s) (via REGOUT), the input to BUSIN will be in the Idle state. A transition from this level to Signal Low (through Signal High) will start the process of decoding a word of data. BUSIN is driven from Signal Low to Signal High for each bit and back to Signal Low to start the next bit. The determination of whether the bit was a one or a zero is made by determining whether it spent more time low (a zero) or high (a one). The end of the word is signaled by a transition at the end of the last bit from Signal High to Idle. The advantage of this method is that it will accept data over a wide range of rates and is not dependent on an accurate clock. The controller will typically indicate a logic zero by spending 2/3 of the bit period at Signal Low and 1/3 at Signal High. A logic one would be 1/3 of the bit period at Signal Low and 2/3 at Signal High. ANALOG-TO-DIGITAL CONVERTER The ADC is an 8-bit successive approximation type using on-board capacitive division. It uses the Clk signal from the on-board oscillator for sequencing. The ADC uses REGOUT as a full-scale reference voltage and ground AGND for a zero-level reference. The ADC signals when it has made a valid conversion by asserting a signal to the controller. If this signal is not asserted when a value is being captured by the controller, the controller will signal that an invalid A/D value was obtained. The value of "0" (binary 00000000) is reserved by the control logic to signal an error. A value of "0" from the ADC will be reported as "1" (binary 00000001) by the control logic. SERIAL ENCODER The Serial Encoder accepts the digitized value from the ADC and formatting/data from the Control Logic. A logic transition from Idle to Signal High and then to Signal Low at BUSIN will cause the first bit to be presented to the current switch (Response Loading). A transition to Signal High and back to Signal Low will cause the next bit to be presented to the current switch. This will continue until a transition back to Idle turns off the current switch. CONTROL LOGIC The control logic performs the digital operations carried out by this device. Its principle functions include: * Decoding input instructions. * Control the general purpose I/O and LOGICOUT in response to BUSIN or BUSOUT commands. * Control A/D conversions. * Form response word. * Capture and store address. * Control BUSSW. * Reset device on power-up. * Control the general purpose I/O logic configuration. 33793 SLEW The slew circuit serves to reduce EMI produced as a result of switching the bus loading current sink element. The slew Analog Integrated Circuit Device Data Freescale Semiconductor 11 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION * Read the general purpose I/O logic values and respond to request for these values. * Generating a cycle redundancy check (CRC) for the received data and transmitted data in conformance with the DSI Bus Standard. Additionally, the control logic performs error checking on the received data. If errors are found, no action is taken and no response is made. Errors include: * CRC received doesn't match CRC of received data. * Number of received bits is not 12 or 20. ADDRESSING The 33793 IC supports both runtime programmable and pre-programmed addressing as defined in the DSI Specification. Runtime programmable addressing uses the daisy chain bus connection. Pre-programmed devices may either be connected in daisy chain or in parallel on the bus wires. Programmable address devices all power up with a device address of $0 in their address register and their bus switches open. In the daisy chain, if the first device receives the initialization command device on BUSIN, it will accept the address in the command and close its switch at the end of the command. The next device in the chain will now be able to receive the initialization command on its BUSIN and will accept the next address. This proceeds down the chain until the last device is addressed. The devices can also be initialized by the reverse initialization command if the signal is applied to BUSOUT. Pre-programmed devices power up with their preprogrammed address in its address register. It will ignore all Initialization commands unless the address in the command matches its pre-programmed address. In this event the device stores the other information contained in the Initialization command. CLOCK The clock is a low-stability type with the capacitor integrated onto the die. The signaling system and all internal operations are such that no external precision timing device is needed in the normal operation of this device. BUS SWITCH (BUSSW) The bus switch passes signaling and power to all subsequent devices on the bus. It can block a voltage of either polarity up to the highest idle state level between BUSIN and BUSOUT. LOGICOUT LOGICOUT is a logic level output with enhanced high-side drive capability. 33793 12 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES A device may be permanently programmed one time with an address using a two-command sequence. The first step is satisfied on the reception of an Initialization command with address set to zero, the PA[3:0] set to the address to be programmed, and the NV bit set. This will cause the address contained in the PA[3:0] bits to be stored in the address register and the bus switch closed. The second step is taken when a Read/Write NVM command is received with the PA[3:0] bits matching the A[3:0] bits and also matching the bits stored in the 33793 address register. This will cause the 33793 to permanently store this address into an internal NVM area. MESSAGES The messages follow the format defined in the Distributed Systems Interface Specification rev 1.0 unless otherwise noted. DSI BUS COMMANDS This device can recognize and respond to both long-word and short-word commands. A command word summary is shown in Table 6. SW in the "Size" column of the table indicates short-word commands and LW indicates long-word commands. Short-word commands may also be sent in the long-word format. However, when these commands are sent in the long-word format, it is recommended that the data byte be sent as $00 to maintain future compatibility. All commands marked reserved should not be sent to 33793 slaves. Table 6. DSI Bus Commands Command Size C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Legend BS = Controls closing of the Bus Switch (1 = close). DR[3:0] = Direction of I/O. 1 = Output. G[1:0] = Group assignment (the 33793 does not use these bits). L[3:0] = Level to output on I/O if configured as outputs. LO = Logic Out level. PA[3:0] = Bus Address to set the device to. NV = Allows nonvolatile address programming if set to "1". C2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LW SW SW LW SW SW LW SW SW SW SW SW LW Initialization Request Status Request Value 0 I/O Control Request ID Information Request Value 1 Request Value 2 Clear Request Value 3 Read/Write NVM Reserved Reserved Clear Logic Out Set Logic Out Reserved Reverse Initialization NV BS G1 G0 PA3 PA2 PA1 PA0 - - - - - - - - - - - - - - - - Description D7 NV - - L3 - - - - - 1 D6 BS - - L2 - - - - - 1 D5 G1 - - L1 - - - - - 1 D4 G0 - - L0 - - - - - 1 D3 PA3 - - DR3 - - - - - PA3 D2 PA2 - - DR2 - - - - - PA2 D1 PA1 - - DR1 - - - - - PA1 D0 PA0 - - DR0 - - - - - PA0 Data 33793 Analog Integrated Circuit Device Data Freescale Semiconductor 13 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES LONG- AND SHORT-WORD RESPONSES The device responds to Long-word commands with long-word responses and short-word commands with short-word responses. Responses are sent during the next message following the command. A long-word response summary is found in Table 7 and a short-word response summary is found in Table 8, page 15. Table 7. Long-Word Response Summary CMD hex 0 1 2 3 4 5 6 7 8 9 A B C D E F Legend A[3:0] = Address bits. The slave address. B[7:0] = 8-bit A/D value. BF = Bus Fault BS = Status of the Bus Switch (1 = close). DR[3:0] = I/O direction bits (1 = Output). G[1:0] = Group assignment (the 33793 does not use these bits). IO[3:0] = Logic level of I/O. L[3:0] = Level to output on I/O if configured as outputs. LO = Logic Out level at the Logic Out pin. NV = Allows nonvolatile address programming if set to "1". PA[3:0] = Bus Address to set the device to. U = Undervoltage Flag. V[2:0] = Version number. Command Description Initialization Request Status Request Value 0 I/O Control Request ID Request Value 1 Request Value 2 Clear Request Value 3 Read/Write NVM Reserved Reserved Clear Logic Out Set Logic Out Reserved Reverse Initialization A3 A2 A1 A0 0 0 0 BF NV BS G1 G0 PA3 PA2 PA1 PA0 A3 A3 A2 A2 A1 A1 A0 A0 0 0 0 0 0 0 0 0 NV NV U U LO LO BS BS IO3 IO3 IO2 IO2 IO1 IO1 IO0 IO0 A3 A3 A2 A2 A1 A1 A0 A0 0 0 0 0 0 0 A3 A3 A3 A3 A3 A3 A3 A2 A2 A2 A2 A2 A2 A2 A1 A1 A1 A1 A1 A1 A1 A0 A0 A0 A0 A0 A0 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Response BF 0 0 0 0 0 0 NV NV B7 L3 V2 B7 B7 BS U B6 L2 V1 B6 B6 G1 LO B5 L1 V0 B5 B5 G0 BS B4 L0 0 B4 B4 PA3 IO3 B3 DR3 0 B3 B3 PA2 IO2 B2 DR2 0 B2 B2 PA1 IO1 B1 DR1 1 B1 B1 PA0 IO0 B0 DR0 1 B0 B0 No Response 0 0 B7 1 B6 1 B5 1 B4 1 B3 PA3 B2 PA2 B1 PA1 B0 PA0 33793 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION DSI COMMANDS AND RESPONSES Table 8. Short-Word Response Summary Command 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Legend B[7:0] = 8-bit A/D value. BS = Status of the Bus Switch (1 = close). LO = Logic Out level at the Logic Out pin. IO[3:0] = Logic level of I/O. NV = Allows nonvolatile address programming if set to "1". PA[3:0] = Bus Address to set the device to. U = Undervoltage Flag. V[2:0] = Version number. Command Description Initialization Request Status Request Value 0 I/O Control Request ID Information Request Value 1 Request Value 2 Clear Request Value 3 Read/Write NVM Reserved Reserved Clear Logic Out Set Logic Out Reserved Reverse Initialization Not Valid NV NV U U LO LO BS BS IO3 IO3 IO2 IO2 IO1 IO1 IO0 IO0 B7 B6 B5 V2 B7 B7 V1 B6 B6 V0 B5 B5 0 B4 B4 NV B7 U B6 LO B5 Response Not Valid BS B4 IO3 B3 IO2 B2 IO1 B1 IO0 B0 Not Valid 0 B3 B3 0 B2 B2 1 B1 B1 1 B0 B0 No Response B4 B3 B2 B1 B0 Not Valid DSI COMMANDS AND RESPONSES INITIALIZATION COMMAND The Initialization command must be sent to the 33793 before it may commence communications over the bus. The command may be used three ways. The first is to initialize a programmable address device. The second is the first step in assigning a pre-programmed address. The third is to initialize a pre-programmed device. For the first case this command is sent to address zero with the NV bit set to zero. The command will be received by the next daisy chain device with its bus switch open. Reception of this command will assign the device address and group number. For the second case the Initialization command is sent the same as the first except that the NV bit is set to one. Table 9. Initialization Command Format Data NV BS G1 G0 PA3 PA2 PA1 PA0 A3 Address A2 A1 A0 0 Command 0 0 0 X3 CRC X2 X1 X0 Reception of the command will assign the device address and group number. A Read/Write NVM command then may be sent to complete the setting of a pre-programmed address. A pre-programmed device must be initialized by putting its address in both PA3:PA0 and A3:A0 fields. Once a device has received an initialization command, it will ignore further initialization commands unless it has received a Clear command or undergone a power-up reset. If BS = 1 and no faults are detected, initialization will cause the bus switch to close. The command format is found in Table 9. 33793 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DEVICE OPERATION DSI COMMANDS AND RESPONSES Table 9. Initialization Command Format Legend A[3:0] = Address bits. The slave address. BS = Bus Switch Position (1 = closed). G[1:0] = Group bits (unused). NV = Nonvolatile Memory Write. The value of the NV bit in the slave. PA[3:0] = Bus Address to set the device to. X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the master. INITIALIZATION RESPONSE This response message is sent during the next message following a valid Initialization command to the addressed Table 10. Initialization Response Format High Byte A3 Legend A[3:0] = Address bits. The slave address. BF = Bus Fault. Bus out short to battery detected. BS = Bus Switch Position (1 = closed). G[1:0] = Group bits (unused). A2 A1 A0 0 0 0 BF NV BS device. The response is shown in Table 10. Because this is a long-word only command, the short-word response is invalid. Low Byte G1 G0 PA3 PA2 PA1 PA0 X3 X2 CRC X1 X0 NV = Nonvolatile Memory Write. The value of the NV bit in the slave. PA[3:0] = Bus Address to set the device to. X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the slave. REQUEST STATUS COMMAND This command will cause the addressed device to return the status of the NV, U, and BS bits and the logic levels of the Table 11. Request Status Command Format Data - Legend A[3:0] = Address bits. The address of the selected device. An address value of "0000" is ignored by all devices. - - - - - - - A3 I/O and LOGICOUT. The command format is found in Table 11. Address A2 A1 A0 0 Command 0 0 1 X3 CRC X2 X1 X0 X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the master. REQUEST STATUS RESPONSE This response message is sent during the next message following a valid Request Status command to the addressed Table 12. Request Status Response Format High Byte A3 A2 A1 A0 0 0 0 0 NV U LO device. The response format is found in Table 12. The high byte is omitted during the short-word response. No response is generated if the command address field was $0. Low Byte BS IO3 IO2 IO1 IO0 X3 CRC X2 X1 X0 Legend A[3:0] = Address bits. The slave address. BS = Bus Switch Position (1 = closed). LO = Logic out driven level. IO[3:0] = Values at logic I/Os. NV = Nonvolatile Memory Write. The value of the NV bit in the slave. U = Undervoltage indicated true by a "1". X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the slave. REQUEST VALUE n COMMAND This command will cause the analog level at one of the four I/O lines to be measured and returned on the following command. The command format is found in Table 13. The analog input measured is defined in Table 14. 33793 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION DSI COMMANDS AND RESPONSES Table 13. Request Value n Command Format Data - Legend A[3:0] = Address bits. The address of the selected device. An address value of "0000" is ignored by all devices. C[3:0] = Command number. X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the master. - - - - - - - A3 Address A2 A1 A0 C3 Command C2 C1 C0 X3 CRC X2 X1 X0 REQUEST VALUES RESPONSE Table 14. Analog Input Selection Command 0010 0101 0110 1000 A/D Input I/O0 I/O1 I/O2 I/O3 This response is an 8-bit value representing the value measured by the ADC. The selection of "n" is a function of the command. This is shown in Table 15. The read will be completed during the idle period and will represent the voltage at the end of the command. If an undervoltage condition exists at any time during the command or the measurement has not completed properly, a value of "00000000" will be returned. This is a reserved value to indicate a problem with the measurement. The minimum valid level reported will be "00000001". No response is generated if the command address field was $0. Table 15. Request Values Response Format High Byte A3 Legend A[3:0] = Address bits. The address of the selected device. An address value of "0000" is ignored by all devices. D[7:0] = Measured value (MSB = D7). X[3:0] = Cyclic Redundancy Check (CRC). A2 A1 A0 0 0 0 0 D7 D6 D5 Low Byte D4 D3 D2 D1 D0 X3 CRC X2 X1 X0 I/O CONTROL COMMAND This register controls the I/O ports. When the "DR" bits are set, the corresponding I/O is enabled as an output. The "L" bit Table 16. I/O Control Command Format Data L3 Legend A[3:0] = Address bits. DR[3:0] = I/O direction bits. 1 = Output. All bits are set to "0" by reset/clear. L2 L1 L0 DR3 DR2 DR1 DR0 A3 settings control the level of the corresponding I/O if it is enabled as an output. The format of this command is shown in Table 16. Address A2 A1 A0 0 Command 0 1 1 X3 CRC X2 X1 X0 L[3:0] = Level to output on I/O if configured as output. All bits are set to "0" by reset/clear X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the master. I/O CONTROL RESPONSE The response indicates which I/O has been configured as outputs and their current values. The values returned will be the values programmed. The values at the pins will not be the ones that were programmed if the pin has been forced to the opposite state. The response format is shown in Table 17. No response is generated if the command address field was $0. Table 17. I/O Control Response Format High Byte Low Byte CRC 33793 Analog Integrated Circuit Device Data Freescale Semiconductor 17 FUNCTIONAL DEVICE OPERATION DSI COMMANDS AND RESPONSES Table 17. I/O Control Response Format A3 Legend A[3:0] = Address bits. DR[3:0] = I/O enabled as outputs (1 = enabled as output). L[3:0] = Programmed values. X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the slave. A2 A1 A0 0 0 0 0 L3 L2 L1 L0 DR3 DR2 DR1 DR0 X3 X2 X1 X0 REQUEST ID COMMAND This command will cause the device ID information to be read from internal storage and returned to the master during Table 18. Request ID Command Format Data - Legend A[3:0] = Address bits. The address of the selected device. An address value of "0000" is ignored by all devices. - - - - - - - A3 the response to the next message. The command format is found in Table 18. Address A2 A1 A0 0 Command 1 0 0 X3 CRC X2 X1 X0 X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the master. REQUEST ID RESPONSE This response message is sent during the next message following a valid long-word Request ID command to the Table 19. Request ID Response Format Address A3 A2 A1 A0 0 Status 0 0 0 V2 V1 V0 addressed device. The response format is found in Table 19. The high byte is omitted during the short-word response. No response is generated if the command address field was $0. Data 0 0 0 1 1 X3 CRC X2 X1 X0 Legend A[3:0] = Address bits. The slave address. V[2:0] = Device version number. The silicon version number of the device. For this device the device type is 00011 as indicated by the lowest bits. X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the slave. CLEAR COMMAND This command will open the bus switch and reset all registers to the reset state. The command format is found in Table 20. No response is generated for the Clear command. Table 20. Clear Command Format Data - Legend A[3:0] = Address bits. The address of the selected device. An address value of "0000" clears all devices. X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the master. - - - - - - - A3 Address A2 A1 A0 0 Command 1 1 1 X3 CRC X2 X1 X0 READ/WRITE NVM COMMAND If the NV bit has been set by a previous Initialization command and the NVM has not been programmed previously, this command will permanently program the device's one-time programmable address and return the programmed value during the next message time. Once 33793 programmed, this nonvolatile address is used to set the device address register on the next and all subsequent power-ups. If the device is not blank, this command will return the programmed value during the next message time. Programming the NVM address to $0 is allowed. This ensures that the device always acts as a dynamically 18 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION DSI COMMANDS AND RESPONSES addressable device and would be immune to any inadvertent future NVM programming sequences. Table 21. Read/Write NVM Command Format Data 1 Legend A[3:0] = Address bits. These bits are the address of the device previously sent with the Initialization command. They must match the address in the PA[3:0] field and the address stored in the device address register. 1 1 1 PA3 PA2 PA1 PA0 A3 Reads and writes are long-word commands only. The command format is found in Table 21. Address A2 A1 A0 1 Command 0 0 1 X3 CRC X2 X1 X0 PA[3:0] = Program Address bits. These bits are the address that is to be programmed into the slave. X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the master. READ/WRITE NVM RESPONSE This response message is sent during the next message following a valid Read/Write NVM command to the addressed Table 22. Read/Write NVM Response Format High Byte A3 Legend A[3:0] = Address bits. The slave address. PA[3:0] = Programmed Address bits. The address that was programmed into the NVM address bits of the slave. A2 A1 A0 0 0 0 0 1 1 1 device. The response format is found in Table 22. The high byte is omitted during the short-word response. No response is generated if the command address field was $0. Low Byte 1 PA3 PA2 PA1 PA0 X3 CRC X2 X1 X0 X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the slave. CLEAR LOGIC OUT COMMAND The Clear Logic Out command sets the Logic Out pin to a logic low. The compliment to this command is the Set Logic Table 23. Clear Logic Out Command Format Data - Legend A[3:0] = Address bits. The address of the selected device. - - - - - - -A3 Out. The Logic Out is also cleared at power-up or following a Clear command. The format of the Clear Logic Out command is shown in Table 23. Address A2 A1 A0 1 Command 1 0 0 X3 CRC X2 X1 X0 X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the master. CLEAR LOGIC OUT RESPONSE This response message is sent during the next message following a valid Clear Logic Out command to the addressed Table 24. Clear Logic Out Response Format High Byte A3 A2 A1 A0 0 0 0 0 NV U LO device. The response is shown in Table 24. No response is generated if the command address field was $0. Low Byte BS IO3 IO2 IO1 IO0 X3 CRC X2 X1 X0 Legend A[3:0] = Address bits. The slave address. BS = Bus Switch Position (1=closed). LO = Logic out driven level. IO[3:0] = Values at logic I/Os. NV = Nonvolatile Memory Write. The value of the NV bit in the slave. U = Undervoltage indicated true by a "1". X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the slave. 33793 Analog Integrated Circuit Device Data Freescale Semiconductor 19 FUNCTIONAL DEVICE OPERATION DSI COMMANDS AND RESPONSES SET LOGIC OUT COMMAND The Set Logic Out command sets the Logic Out pin to a logic high. The compliment to this command is the Clear Table 25. Set Logic Out Command Format Data Legend A[3:0] = Address bits. The address of the selected device. A3 Logic Out. The Logic Out is cleared at power-up or following a Clear command. The format of the Clear Logic Out command is shown in Table 25. Address A2 A1 A0 1 Command 1 0 1 X3 CRC X2 X1 X0 X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the master. SET LOGIC OUT RESPONSE This response message is sent during the next message following a valid Set Logic Out command to the addressed Table 26. Set Logic Out Response Format High Byte A3 Legend A[3:0] - Address bits. The slave address. BS = Bus Switch Position (1=closed) IO[3:0] = Values at logic I/Os. LO = Logic out driven level. A2 A1 A0 0 0 0 0 NV U device. The response is shown in Table 26. No response is generated if the command address field was $0. Low Byte LO BS IO3 IO2 IO1 IO0 X3 CRC X2 X1 X0 NV = Nonvolatile Memory Write. The value of the NV bit in the slave. U = Undervoltage indicated true by a "1". X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the slave. REVERSE INITIALIZATION The Reverse Initialization is similar to the Initialization command and will only work under the condition that it has not already been initialized. The command may be used three ways. The first is to initialize a programmable address device. The second is the first step in assigning a preprogrammed address. The third is to initialize a preprogrammed device. For the first case this command is sent to address zero with the NV bit set to zero. The command will be received by the next daisy chain device with its bus switch open. Reception of this command will assign the device address and the group number. Reception of this command will also cause the bus switch to close if BS = 1 and no fault is detected. Table 27. Reverse Initialization Command Format Data NV BS G1 G0 PA3 PA2 PA1 PA0 A3 For the second case the Initialization command is sent the same as the first except that the NV bit is set to one. Reception of the command will assign the device address and the group number and cause the bus switch to close if BS = 1 and there are no faults. A Read/Write NVM command then may be sent to complete the setting of a preprogrammed address. A pre-programmed device must be initialized by putting its address in both PA3:PA0 and A3:A0 fields. Once a device has received a reverse initialization command, it will ignore further reverse initialization commands or initialization commands unless it has received a Clear command or undergone a power-up reset. The command format is found in Table 27. Address A2 A1 A0 1 Command 1 1 1 X3 CRC X2 X1 X0 33793 20 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION DSI COMMANDS AND RESPONSES Table 27. Reverse Initialization Command Format Legend A[3:0] = Address bits. These bits are the slave address. For programmable devices these bits are all set to zero. For preprogrammed devices these bits contain the pre-programmed address and must match the PA[3:0] bits. NV = Nonvolatile Memory Write. When set to a one, this bit allows a subsequent NVM command to store a nonvolatile address. When set to a zero, NVM programming is disallowed. Once a permanent address has been stored in the device, setting the NV bit to a one has no effect. G[1:0] = Group bits. These bits are the group number for the slave. X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the These bits are not used by this device and should be set to "0". master. PA[3:0] = Program Address bits. These bits are the address that is to be stored into the slave's address register. REVERSE INITIALIZATION RESPONSE This response message is sent during the next message following a valid Reverse Initialization command to the addressed device. The response is shown in Table 28. Since Table 28. Reverse Initialization Response Format High Byte A3 Legend A[3:0] = Address bits.The slave address. BF = Bus Fault. BUSIN short to battery detected. BS = Controls closing of the Bus Switch (1=close). A2 A1 A0 0 0 0 BF NV BS this is a long-word only command, the short-word response is invalid. No response is generated if the command address field was $0. Low Byte G1 G0 PA3 PA2 PA1 PA0 X3 X2 CRC X1 X0 NV = Nonvolatile Memory Write. The value of the NV bit in the slave. PA[3:0] = Bus Address to set the device to. X[3:0] = Cyclic Redundancy Check (CRC). The CRC as calculated by the G[1:0] = Group bits. Not used on this part, will be set to "0". The slave. group number programmed into the slave. 33793 Analog Integrated Circuit Device Data Freescale Semiconductor 21 TYPICAL APPLICATIONS TYPICAL APPLICATIONS H_CAP Rectifiers 1.0 F Typical BUSIN Bus Switch 0 - 35 V Bi-Directional Forward Receiver Data Response Current 0 -11 mA 7.0 mA/S Received Message from MCU Oscillator 4.0 MHz DataOut <3:0> BUSOUT Reverse Receiver Data Frame Frame BUSRTN Bandgap Reference Bandgap Reference Bus Return Logic Command Decode State Machine Response Generation 4 LOGOUT Power Management 5.0 V Regulator BG Reference Bias Currents Supply Comparators POR Logic Out High Current Buffer REGOUT 4.7 F I/O Buffers DataOut <0> IO0 IO1 IO2 IO3 DataOut <1> Address A<3:0> 4 Bits NVM DataOut <2> I/O0 I/O1 I/O2 I/O<3:0> I/O3 GND SEL 4:1 MUX DataOut <3> ADC 8 Bits Undervoltage Detector BG COMMUNICATION FORMAT DSI messages are composed of individual words separated by a frame delay. Transfers are full duplex. Command messages from the master occur at the same time as responses from the slaves. Slave responses to commands occur during the next command message. This allows slaves Master time to decode the command, retrieve the information and prepare to send it to the master. A bus traffic example is shown in Figure 6. The example shows three commands separated by the minimum frame delay followed by a command after a longer delay. Slave Figure 6. Bus Traffic Example 33793 22 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS In case there is a bus error (due to induced noise or a bus fault), both the master and slave devices will read bad data. The slave reacts to bad data by not sending a response during the next frame. The master will detect a CRC error once it receives the corrupted data sent by the slave, and once again when the slave fails to respond. This is illustrated in Figure 7. When this error occurs, the system software needs to acknowledge this condition and resend a command (any command of same size) so that it can receive the CRC Error previous response just prior to the bus fault condition (in this case, Command N). Failure to take corrective action will result in unintended errors as shown in Figure 7. In this case, the master will miss Responses N+1 and N+2 and will mistake them for N+3 and N+4. The master should send another N+1 command after the error is acknowledged to re-synchronize the commandresponse sequence. Bus Error CRC Error Data misinterpreted by Master Master Command N Command N+1 Command N+2 Command N+3 Command N+4 Slave Response N-1 Response N No Response Response N Response N+3 CRC Error Figure 7. Bus Traffic With Receive Errors (Master Reads Incorrect Data) POWER UP RESET When power is first applied to the DSI bus, the system must allow enough time for the internal 5 volt regulator of each device to come up to a proper level. This implies that H_CAP must charge up to VRECT + 5 V, or approximately 6 volts. The time this takes is a function of the size of H_CAP, and the current drive of the Master. The following equation can be used to estimate the minimum time to wait before sending an Initialization Command: tMIN (H_CAP x 6V) / ICHARGE where ICHARGE is the charging current provided by the DSI Master. The above assumes a daisy-chain type of bus topology, and enough time must be allowed for all down-stream devices in the chain to charge up. For example, if device #1 has it's switch closed after its Initialization Command, then the system must wait for device #2 to power up before sending its Initialization Command, and so on down the line. If the devices are attached in a parallel or point-to-point bus configuration, then the total capacitor value is the sum of all H_CAPS. In addition to the charge up time, enough time must be allocated for the bus fault test (see next section). just before a device is Reverse Initialized, the BUSIN is defined as the inactive side. The test for a bus fault is only performed once during Forward or Reverse Initialization (when BS bit is set) by applying an 11mA pull-down current to the inactive side of the Bus Switch and monitoring the voltage. The fault test takes approximately 200uS. If no fault is detected, the bus switch will be closed, and if a fault is detected, the bus switch will not close. The fault test applies to both programmed and unprogrammed devices. Exception: In the case of a daisy-chain bus topology where the last device BUSOUT line connects to BUSIN of the first device (loop-back), then the fault test will NOT be executed since both BUSIN and BUSOUT are connected to active busses. It is up to the system software to run the appropriate diagnostic tests to resolve this special case. (One alternative is to use a separate DSI Master to handle the loop-back signal path. This second DSI Master is only activated in the case of a bus fault so that the last device can be accessed by means of a reverse initialization.) GLOBAL ADDRESS 0 Any time an Initialization or Reverse Initialization command is sent to the 33793 with an address of 0x0 (global address), the device behaves as follows: * Device initializes to address 0. * Bus switch remains open. This implies that in a daisychain bus topology, all devices past the first device will remain off. * NV and BS bits are not stored and have no effect. BUS FAULTS A bus fault is defined as an external voltage on the "Inactive Side" of the Bus Switch that is greater than 3V (typical). Inactive refers to the side of the bus that is not yet connected to the bus. Just before a device is Forward Initialized, the inactive side is defined as BUSOUT. Similarly, 33793 Analog Integrated Circuit Device Data Freescale Semiconductor 23 TYPICAL APPLICATIONS * Device will respond to further commands at address 0 (such as setting and clearing the I/O bits and LOGOUT) but there is no response (Master will read all zeros). If the devices are connected in a daisy chain, then only the fist device will respond. * Subsequent writes to re-initialize the device will not be possible until the device is cleared. 33793 24 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below. EF SUFFIX (PB-FREE) 16-PIN PLASTIC PACKAGE 98ASB42566B ISSUE M 33793 Analog Integrated Circuit Device Data Freescale Semiconductor 25 REVISION HISTORY REVISION HISTORY REVISION 12.0 DATE 8/2006 DESCRIPTION OF CHANGES 13.0 11/2006 Implemented Revision History page Converted to Freescale format Added PC33793EF Added Feature bullets Rewrote and enhanced Device Operation - No electrical changes Updated to the prevailing Freescale form and style Removed PC33793EF and replaced with MCZ33793EF/R2 in the Ordering Information block * Added MCZ33793AEF/R2 to the Ordering Information * Added Device Variations table on page 2 * Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 5. Added note with instructions to obtain this information from www.freescale.com. * * * * * * * 33793 26 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http:// www.freescale.com/epp. Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc., 2006. All rights reserved. MC33793 Rev 13.0 11/2006 |
Price & Availability of MC33793DR2
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |