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Freescale Semiconductor, Inc.
Order this document by MC68HC05P18A/D
Freescale Semiconductor, Inc...
MC68HC05P18A
HCMOS Microcontroller Unit
TECHNICAL DATA
For More Information On This Product, Go to: www.freescale.com
NON-DISCLOSURE
AGREEMENT
HC 5
REQUIRED
Freescale Semiconductor, Inc. Technical Data REQUIRED
Freescale Semiconductor, Inc...
AGREEMENT
NON-DISCLOSURE
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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MC68HC05P18A
Freescale Semiconductor, Inc.
Technical Data -- MC68HC05P18A
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 15 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Freescale Semiconductor, Inc...
Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . 33 Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Section 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . 49 Section 7. Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . 55 Section 8. 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Section 9. Serial Input/Output Ports (SIOP) . . . . . . . . . . 77 Section 10. EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Section 11. Analog-to-Digital (A/D) Converter . . . . . . . . 91 Section 12. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . 97 Section 13. Electrical Specifications . . . . . . . . . . . . . . . 115 Section 14. Mechanical Specifications . . . . . . . . . . . . . 125 Section 15. Ordering Information . . . . . . . . . . . . . . . . . 127
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Technical Data
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. List of Sections REQUIRED NON-DISCLOSURE
Technical Data List of Sections For More Information On This Product, Go to: www.freescale.com
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AGREEMENT
MC68HC05P18A
Freescale Semiconductor, Inc.
Technical Data -- MC68HC05P18A
Table of Contents
Section 1. General Description
1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
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1.3 1.4
Section 2. Memory Map
2.1 2.2 2.3 2.4 2.5 2.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 I/O and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
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Technical Data
NON-DISCLOSURE
1.5 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.1 Power Supply (VDD and VSS) . . . . . . . . . . . . . . . . . . . . . . . .20 1.5.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .20 1.5.2.1 Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.2.2 Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.2.3 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.3 Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.4 Port A (PA0-PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.5 Port B (PB5/SDO, PB6/SDI, and PB7/SCK) . . . . . . . . . . . .23 1.5.6 Port C (PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/VREFH) . . . . . . . . . . . . . . . . . . . . . . .23 1.5.7 Port D (PD5/CKOUT and PD7/TCAP) . . . . . . . . . . . . . . . . .23 1.5.8 Timer Output Compare (TCMP) . . . . . . . . . . . . . . . . . . . . . .23 1.5.9 Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . .24 1.5.10 CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
AGREEMENT
1.2
REQUIRED
Freescale Semiconductor, Inc. Table of Contents REQUIRED Section 3. Central Processor Unit (CPU)
3.1 3.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
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AGREEMENT
3.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.4 Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Section 4. Interrupts
4.1 4.2 4.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
NON-DISCLOSURE
4.4 Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.4.1 Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.4.2 Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.4.3 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.4.3.1 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.4.3.2 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.4.3.3 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . .44 4.4.3.4 Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .44
Section 5. Resets
5.1 5.2 5.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.4 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.4.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . .47 5.4.3 Low-Voltage Reset (LVR). . . . . . . . . . . . . . . . . . . . . . . . . . .48
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MC68HC05P18A
Freescale Semiconductor, Inc.
Table of Contents
Section 6. Operating Modes
6.1 6.2 6.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
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6.5
COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . .54
Section 7. Input/Output (I/O) Ports
7.1 7.2 7.3 7.4 7.5 7.6 7.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Section 8. 16-Bit Timer
8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Timer Operation during Wait Mode and Halt Mode . . . . . . . . .74 Timer Operating during Stop Mode . . . . . . . . . . . . . . . . . . . . .74
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Technical Data
NON-DISCLOSURE
AGREEMENT
6.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 6.4.1 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 6.4.1.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 6.4.1.2 Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.4.2 WAIT Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
REQUIRED
Freescale Semiconductor, Inc. Table of Contents REQUIRED Section 9. Serial Input/Output Ports (SIOP)
9.1 9.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
9.3 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 9.3.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 9.3.2 Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3.3 Serial Data Output (SDO). . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.4 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 9.4.1 SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 9.4.2 SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 9.4.3 SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Freescale Semiconductor, Inc...
AGREEMENT
Section 10. EEPROM
10.1 10.2 10.3 10.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 EEPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . .86 Programming/Erasing Procedures . . . . . . . . . . . . . . . . . . . . . .88
Section 11. Analog-to-Digital (A/D) Converter
11.1 11.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
NON-DISCLOSURE
11.3 Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.3.1 Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.3.2 Reference Supply Voltage (VREFH) . . . . . . . . . . . . . . . . . . .92 11.3.3 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.4 Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.5 Digital Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.5.1 Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.5.2 Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . .93 11.5.3 Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .94 11.6 11.7 A/D Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . .94 A/D Conversion Value Data Register . . . . . . . . . . . . . . . . . . . .96
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MC68HC05P18A
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Table of Contents
11.8 11.9
A/D Subsystem Operation during Wait Mode and Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 A/D Subsystem Operation during Stop Mode. . . . . . . . . . . . . .96
Section 12. Instruction Set
12.1 12.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
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12.5
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Section 13. Electrical Specifications
13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9
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Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .116 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .118 Active Reset Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .119 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . .120 SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Technical Data
NON-DISCLOSURE
12.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 12.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .102 12.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .103 12.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .104 12.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .106 12.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
AGREEMENT
12.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 12.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 12.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 12.3.7 Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 12.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
REQUIRED
Freescale Semiconductor, Inc. Table of Contents REQUIRED
13.10 PD5 Clock Out Timing (PD5 Clock Out Option Enabled) . . . .122 13.11 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Section 14. Mechanical Specifications
14.1 14.2 14.3 14.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 28-Pin Plastic Dual In-Line Package (Case #710) . . . . . . . . .126 28-Pin Small Outline Package (Case #751F) . . . . . . . . . . . . .126
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AGREEMENT
Section 15. Ordering Information
15.1 15.2 15.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
NON-DISCLOSURE
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MC68HC05P18A
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Technical Data -- MC68HC05P18A
List of Figures
Figure 1-1 1-2 1-3 2-1 2-2 2-3 3-1 3-2 3-3 3-4 3-5 3-6 4-1 5-1 5-2 6-1 7-1 7-2 7-3 7-4 Title Page
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MC68HC05P18A User Mode Memory Map . . . . . . . . . . . . . . .27 MC68HC05P18A I/O and Control Registers Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 I/O and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Index Register (X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .37 Interrupt Processing Flowchart . . . . . . . . . . . . . . . . . . . . . . . . .41 Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Stop, Halt, and Wait Modes Flowchart . . . . . . . . . . . . . . . . . . .51 Port A I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Port B I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Port C I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Port D I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
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Technical Data
NON-DISCLOSURE
AGREEMENT
MC68HC05P18A Block Diagram . . . . . . . . . . . . . . . . . . . . . . .17 User Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
REQUIRED
Freescale Semiconductor, Inc. List of Figures REQUIRED
Figure 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 9-1 9-2 9-3 9-4 9-5 Title Page
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AGREEMENT
16-Bit Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Timer Counter Registers (TMRH/TMRL) . . . . . . . . . . . . . . . . .66 Alternate Counter Registers (ACRH/ACRL) . . . . . . . . . . . . . . .66 State Timing Diagram for Timer Overflow . . . . . . . . . . . . . . . .67 State Timing Diagram for Timer Reset . . . . . . . . . . . . . . . . . . .67 Output Compare Registers (OCRH/OCRL) . . . . . . . . . . . . . . .68 Output Compare Software Initialization Example . . . . . . . . . . .69 Input Capture Registers (ICRH/ICRL) . . . . . . . . . . . . . . . . . . .70 State Timing Diagram for Input Capture . . . . . . . . . . . . . . . . . .71 Timer Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . . .72 Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . .73 SIOP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 SIOP Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . .80 SIOP Status Register (SSR). . . . . . . . . . . . . . . . . . . . . . . . . . .82 SIOP Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
10-1 EEPROM Programming Register (EEPROG) . . . . . . . . . . . . .86 11-1 A/D Status and Control Register (ADSCR). . . . . . . . . . . . . . . .94 11-2 A/D Conversion Value Data Register (ADC) . . . . . . . . . . . . . .96 13-1 SIOP Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 13-2 PD5 Clock Out Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 13-3 Power-On Reset and External Reset Timing Diagram . . . . . .124
NON-DISCLOSURE
Technical Data
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Technical Data -- MC68HC05P18A
List of Tables
Table 4-1 Title Page
Vector Address for Interrupts and Reset . . . . . . . . . . . . . . . . .40 COP Watchdog Timer Recommendations . . . . . . . . . . . . . . . .54 Port A I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Port B I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Port C I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Port D I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
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6-1 7-1 7-2 7-3 7-4
10-1 Erase Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 11-1 A/D Multiplexer Input Channel Assignments . . . . . . . . . . . . . .95 12-1 12-2 12-3 12-4 12-5 12-6 12-7 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . .102 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .103 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .105 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .106 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
15-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
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Technical Data
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. List of Tables REQUIRED NON-DISCLOSURE
Technical Data List of Tables For More Information On This Product, Go to: www.freescale.com
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AGREEMENT
MC68HC05P18A
Freescale Semiconductor, Inc.
Technical Data -- MC68HC05P18A
Section 1. General Description
1.1 Contents
1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
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1.3 1.4
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Technical Data
NON-DISCLOSURE
1.5 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.1 Power Supply (VDD and VSS) . . . . . . . . . . . . . . . . . . . . . . . .20 1.5.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .20 1.5.2.1 Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.2.2 Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.2.3 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.3 Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.4 Port A (PA0-PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.5 Port B (PB5/SDO, PB6/SDI, and PB7/SCK) . . . . . . . . . . . .23 1.5.6 Port C (PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/VREFH) . . . . . . . . . . . . . . . . . . . . . . .23 1.5.7 Port D (PD5/CKOUT and PD7/TCAP) . . . . . . . . . . . . . . . . .23 1.5.8 Timer Output Compare (TCMP) . . . . . . . . . . . . . . . . . . . . . .23 1.5.9 Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . .24 1.5.10 CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
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REQUIRED
Freescale Semiconductor, Inc. General Description REQUIRED 1.2 Introduction
The Motorola MC68HC05P18A is a low-cost microcontroller with: * * * * 4-channel, 8-bit analog-to-digital (A/D) converter 16-bit timer with output compare and input capture Serial communications port (SIOP) Computer operating properly (COP) watchdog timer
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AGREEMENT
The HC05 central processor unit (CPU) core contains: * * * * 192 bytes of random-access memory (RAM) 8064 bytes of user read-only memory (ROM) 128 bytes of electrically erasable programmable read-only memory (EEPROM) 21 input/output (I/O) pins (20 bidirectional, 1 input-only)
This device is available in: * * 28-pin plastic dual in-line package (PDIP) 28 pin small-outline integrated circuit package (SOIC)
NON-DISCLOSURE
A functional block diagram of the MC68HC05P18A is shown in Figure 1-1.
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MC68HC05P18A
Freescale Semiconductor, Inc.
General Description Introduction
COP
PH2
/2
OSC
OSC1 OSC2
CPU CONTROL RESET 68HC05 CPU IRQ
ALU
/4
16-BIT TIMER 1 INPUT CAPTURE 1 OUTPUT COMPARE PORT D LOGIC
PD7/TCAP TCMP PD5/CKOUT
ACCUMULATOR CPU REGISTERS DATA DIRECTION REGISTER INDEX REGISTER A/ D CONVERTER PC7/VREFH PC6/AD0 MUX PC5/AD1 PC4/AD2 PC3/AD3 PC2 PC1 PC0 SRAM -- 192 BYTES PA7 DATA DIRECTION REGISTER USER ROM -- 8064 BYTES PA6 PA5 PORT A PA4 PA3 PA2 PA1 PA0 PB5/SDO PB6/SDI PB7/SCK PORT B AND SIOP REGISTERS AND LOGIC VDD VSS
Freescale Semiconductor, Inc...
0 0 0 0 0 0 0 0 1 1 STK PNTR PROGRAM COUNTER CONDITION CODE 111H I NZC REGISTER
EEPROM -- 128 BYTES
Figure 1-1. MC68HC05P18A Block Diagram
NOTE:
A line over a signal name indicates an active low signal. For example, RESET is active high and RESET is active low.
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Technical Data
NON-DISCLOSURE
AGREEMENT
PORT C
REQUIRED
Freescale Semiconductor, Inc. General Description REQUIRED 1.3 Features
Features of the MC68HC05P18A include: * * * * Low-cost, HC05 core running at 2-MHz bus speed, or the 4-MHz high-speed option 28-pin DIP or SOIC package On-chip crystal/ceramic resonator 8064 bytes of user ROM including: - 48 bytes of page zero ROM - 16 bytes of user vectors * * * * * * * * * * * * * 192 bytes of on-chip RAM 128 bytes of EEPROM Low-voltage reset (LVR) Four-channel, 8-bit A/D converter Serial communications port COP watchdog timer with active pull down on RESET 16-bit timer with output compare and input capture Edge- and level-sensitive interrupt or edge-sensitive only (mask option) 20 bidirectional I/O lines and 1 input-only line Individually mask selectable pullups/interrupts on port A pins High current sink and source on two I/O pins, PC0 and PC1 Power-saving stop mode and wait mode instructions and stop conversion to halt mode (mask option) Mask option for clock output pin
NON-DISCLOSURE
Technical Data
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AGREEMENT
MC68HC05P18A General Description For More Information On This Product, Go to: www.freescale.com
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General Description Mask Options
1.4 Mask Options
The MC68HC05P18A has eight mask options: 1. IRQ is edge- and level-sensitive or edge-sensitive only. 2. SIOP MSB (most-significant bit) first or LSB (least-significant bit) first 3. SIOP clock rate set to OSC divided by 2, 4, 8, 16, 32, 64, 128, or 256
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5. Stop instruction enabled or converted to halt mode 6. Option to enable clock output pin to replace PD5 7. Option to individually enable pullups/interrupts on each of the eight port A pins 8. LVR enabled or disabled
1.5 Functional Pin Description
This subsection describes the functionality of each pin on the MC68HC05P18A package.
NOTE:
For pins connected to subsystems described in other sections, a reference to the section is given instead of a detailed functional description. The pinout is shown in Figure 1-2.
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Technical Data
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AGREEMENT
4. COP watchdog timer enabled or disabled
REQUIRED
Freescale Semiconductor, Inc. General Description REQUIRED
RESET IRQ PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 SDO/PB5 SDI/PB6 SCK/PB7 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD OSC1 OSC2 PD7/TCAP TCMP PD5/CKOUT PC0 PC1 PC2 PC3/AD3 PC4/AD2 PC5/AD1 PC6/AD0 PC7/VREFH
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AGREEMENT
Figure 1-2. User Mode Pinout
1.5.1 Power Supply (VDD and VSS) Power is supplied to the MCU through VDD and VSS . VDD is connected to a regulated +5-volt supply and VSS is connected to ground. Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, take special care to provide good power supply bypassing at the MCU. Use bypass capacitors with good high-frequency characteristics and position them as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded.
NON-DISCLOSURE
1.5.2 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the control connections for the on-chip oscillator. The OSC1 and OSC2 pins can accept: 1. A crystal or ceramic resonator, as shown in Figure 1-3 (a) 2. An external clock signal, as shown in Figure 1-3 (b)
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MC68HC05P18A
Freescale Semiconductor, Inc.
General Description Functional Pin Description
The frequency, fOSC, of the oscillator or external clock source is divided by two to produce the internal PH2 bus clock operating frequency, fOP. The oscillator cannot be turned off by software if the stop-to-halt conversion is enabled via mask option.
TO VDD OR STOP
MCU
TO VDD OR STOP
MCU
Freescale Semiconductor, Inc...
4.7 M UNCONNECTED
EXTERNAL CLOCK 37 pF 37 pF
(a)
Crystal or Ceramic Resonator Connections
(b)
External Clock Source Connections
Figure 1-3. Oscillator Connections 1.5.2.1 Crystal The circuit in Figure 1-3 (a) shows a typical oscillator circuit for an AT-cut, parallel resonant crystal.
NOTE:
The crystal manufacturer's recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable startup. The load capacitance values used in the oscillator circuit design should include all stray capacitances. Mount the crystal and components as close as possible to the pins for startup stabilization and to minimize output distortion.
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Technical Data
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AGREEMENT
OSC1
OSC2
OSC1
OSC2
REQUIRED
Freescale Semiconductor, Inc. General Description REQUIRED
1.5.2.2 Ceramic Resonator In cost-sensitive applications, a ceramic resonator can be used in place of the crystal. The circuit in Figure 1-3 (a) can be used for a ceramic resonator.
NOTE:
The crystal manufacturer's recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable startup. The load capacitance values used in the oscillator circuit design should include all stray capacitances. Mount the resonator and components as close as possible to the pins for startup stabilization and to minimize output distortion.
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AGREEMENT
1.5.2.3 External Clock An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3 (b).
1.5.3 Reset (RESET) Driving this input low resets the MCU to a known startup state. As an output pin, the RESET pin indicates that an internal MCU reset has occurred. The RESET pin contains an internal Schmitt trigger to improve its noise immunity. Refer to Section 5. Resets.
NON-DISCLOSURE
1.5.4 Port A (PA0-PA7) Port A is comprised of eight I/O pins (PA0-PA7). The state of any pin is software programmable and all port A lines are configured as inputs during power-on or reset. Eight mask options can be chosen to enable pullups and interrupts (active low) on port A pins (see 1.4 Mask Options). Refer to Section 7. Input/Output (I/O) Ports and Section 4. Interrupts.
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MC68HC05P18A
Freescale Semiconductor, Inc.
General Description Functional Pin Description
1.5.5 Port B (PB5/SDO, PB6/SDI, and PB7/SCK) Port B is comprised of three I/O pins which are shared with the SIOP communications subsystem. The state of any pin is software programmable and all port B lines are configured as inputs during power-on or reset. Refer to Section 7. Input/Output (I/O) Ports and Section 9. Serial Input/Output Ports (SIOP).
1.5.6 Port C (PC0-PC2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/VREFH)
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Port C is comprised of eight I/O pins which are shared with the A/D converter subsystem. The state of any pin is software programmable and all port C lines are configured as inputs during power-on or reset. Port pins PC0 and PC1 are capable of sourcing and sinking high currents. Refer to Section 7. Input/Output (I/O) Ports.
1.5.7 Port D (PD5/CKOUT and PD7/TCAP) Port D is comprised of two I/O pins and one of them is shared with the 16-bit timer subsystem. The state of PD5/CKOUT is software programmable and is configured as an input during power-on or reset. PD7 is always an input; it may be read at any time, regardless of the mode of operation the 16-bit timer may be in. Refer to Section 7. Input/Output (I/O) Ports and Section 8. 16-Bit Timer.
NOTE:
A mask option turns the PD5/CKOUT pin into a clock output which is a buffered OSC2 signal with a CMOS output driver. The clock output or the port D function must be chosen with the mask option and is not alterable in software.
1.5.8 Timer Output Compare (TCMP) TCMP is the output from the 16-bit timer's output compare function. It is low after reset. Refer to Section 8. 16-Bit Timer.
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Technical Data
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. General Description REQUIRED
1.5.9 Maskable Interrupt Request (IRQ) This input pin drives the asynchronous interrupt function of the MCU. The MCU completes the current instruction being executed before it responds to the IRQ interrupt request. When IRQ is driven low, the event is latched internally to signify an interrupt has been requested. When the MCU completes its current instruction, the interrupt latch is tested. If the interrupt latch is set, and the interrupt mask bit (I bit) in the condition code register (CCR) is clear, the MCU begins the interrupt sequence. Depending on the mask option selected, the IRQ pin triggers this interrupt on either a negative going edge at the IRQ pin and/or while the IRQ pin is held in the low state. In either case, the IRQ pin must be held low for at least one tILIH time period. If the edge- and level-sensitive mask option is selected, the IRQ input requires an external resistor connected to VDD for a wired-OR operation. If the IRQ pin is not used, it must be tied to the VDD supply. The IRQ pin contains an internal Schmitt trigger as part of its input circuitry to improve noise immunity. Refer to Section 4. Interrupts.
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AGREEMENT
1.5.10 CPU Core
NON-DISCLOSURE
The MC68HC05P18A uses a standard M68HC05 series CPU core. A description of the instruction set is in Section 12. Instruction Set.
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MC68HC05P18A
Freescale Semiconductor, Inc.
Technical Data -- MC68HC05P18A
Section 2. Memory Map
2.1 Contents
2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 I/O and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
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2.3 2.4 2.5 2.6
2.2 Introduction
The MC68HC05P18A utilizes 14 address lines to access an internal memory space covering 16 Kbytes. This memory space is divided into: * * * * Input/output (I/O)
Electrically erasable programmable read-only memory (EEPROM) Read-only memory (ROM)
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Technical Data
NON-DISCLOSURE
Random-access memory (RAM)
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Memory Map REQUIRED 2.3 User Mode Memory Map
When the MC68HC05P18A is in user mode, these are active: * * * * * * 32 bytes of I/O 192 bytes of RAM 128 bytes of EEPROM 8000 bytes of user ROM 48 bytes of user page zero ROM 16 bytes of user vector ROM
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AGREEMENT
See Figure 2-1.
2.4 I/O and Control Registers
Figure 2-2 and Figure 2-3 briefly describe the I/O and control registers at locations $0000-$001F.
NOTE:
Reading unimplemented bits returns unknown states, and writing unimplemented bits is ignored.
NON-DISCLOSURE
Technical Data Memory Map For More Information On This Product, Go to: www.freescale.com
MC68HC05P18A
Freescale Semiconductor, Inc.
Memory Map I/O and Control Registers
$0000 $001F $0020 $004F $0050 $00BF $00C0 $00FF $0100 $010F $0140
I/O 32 BYTES USER ROM 48 BYTES INTERNAL RAM 192 BYTES STACK 64 BYTES
0000 0031 0032 0079 0080 0191 0192 0255 0256 0271 0272 0399 0400
$0000
I/O REGISTERS SEE FIGURE 2-2
$001F
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$01BF $01C0
UNUSED 7728 BYTES $1FBF $1FC0 USER ROM 8000 BYTES $3EFF $3F00 16127 16128 8127 8128
COP CONTROL REGISTER UNIMPLEMENTED UNIMPLEMENTED UNIMPLEMENTED UNIMPLEMENTED UNIMPLEMENTED UNIMPLEMENTED
$3FF0 $3FF1 $3FF2 $3FF3 $3FF4 $3FF5 $3FF6 $3FF7 $3FF8 $3FF9 $3FFA $3FFB $3FFC $3FFD $3FFE $3FFF
$3FEF $3FF0 $3FFF
RESERVED FOR TEST 240 BYTES USER VECTORS ROM 16 BYTES
16367 16368 16383
UNIMPLEMENTED TIMER VECTOR (HIGH BYTE) TIMER VECTOR (LOW BYTE) IRQ VECTOR (HIGH BYTE) IRQ VECTOR (LOW BYTE) SWI VECTOR (HIGH BYTE) SWI VECTOR (LOW BYTE) RESET VECTOR (HIGH BYTE) RESET VECTOR (LOW BYTE)
Figure 2-1. MC68HC05P18A User Mode Memory Map
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Technical Data
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AGREEMENT
EEPROM 128 BYTES
REQUIRED
Freescale Semiconductor, Inc. Memory Map REQUIRED
PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER PORT D DATA REGISTER PORT A DATA DIRECTION REGISTER PORT B DATA DIRECTION REGISTER PORT C DATA DIRECTION REGISTER PORT D DATA DIRECTION REGISTER UNIMPLEMENTED UNIMPLEMENTED SIOP CONTROL REGISTER
$0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F
AGREEMENT
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SIOP STATUS REGISTER SIOP DATA REGISTER UNIMPLEMENTED UNIMPLEMENTED UNIMPLEMENTED UNIMPLEMENTED UNIMPLEMENTED TIMER CONTROL REGISTER TIMER STATUS REGISTER INPUT CAPTURE MSB INPUT CAPTURE LSB OUTPUT COMPARE MSB OUTPUT COMPARE LSB TIMER MSB TIMER LSB ALTERNATE COUNTER MSB ALTERNATE COUNTER LSB EEPROM PROGRAMMING REGISTER A/D CONVERTER DATA REGISTER A/D CONVERTER CONTROL & STATUS REGISTER RESERVED FOR TEST
NON-DISCLOSURE
Figure 2-2. MC68HC05P18A I/O and Control Registers Memory Map
Technical Data Memory Map For More Information On This Product, Go to: www.freescale.com
MC68HC05P18A
Freescale Semiconductor, Inc.
Memory Map I/O and Control Registers
Addr.
Register Name Read: Port A Data Register (PORTA) Write: See page 56. Reset: Read: Port B Data Register (PORTB) Write: See page 57. Reset: Read: Port C Data Register (PORTC) Write: See page 58. Reset: Read: Port D Data Register (PORTD) Write: See page 59. Reset:
Bit 7 PA7
6 PA6
5 PA5
4 PA4
3 PA3
2 PA2
1 PA1
Bit 0 PA0
$0000
Unaffected by reset 0 PB7 PB6 PB5 Unaffected by reset PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0 0 0 0
$0001
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$0002
Unaffected by reset PD7 0 PD5 Unaffected by reset DDRA6 0 DDRB6 0 DDRC6 0 0 DDRD5 0 0 0 0 0 0 0 0 DDRA5 0 DDRB5 0 DDRC5 0 0 DDRC4 0 0 0 DDRC3 0 0 0 DDRC2 0 0 0 DDRC1 0 0 0 DDRC0 0 0 DDRA4 0 1 DDRA3 0 1 DDRA2 0 1 DDRA1 0 1 DDRA0 0 1 1 0 0 0 0
$0003
$0004
Read: Port A Data Direction DDRA7 (DDRA) Write: See page 56. Reset: 0 Read: Port B Data Direction DDRB7 (DDRB) Write: See page 57. Reset: 0 Read: Port C Data Direction DDRC7 (DDRC) Write: See page 58. Reset: 0 Read: Port D Data Direction (DDRD) Write: See page 59. Reset: Unimplemented 0
$0006
$0007
$0008
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-3. I/O and Control Registers (Sheet 1 of 4)
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Technical Data
NON-DISCLOSURE
$0005
AGREEMENT
REQUIRED
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Addr. $0009
Register Name Unimplemented Read: SIOP Control Register (SCR) Write: See page 80. Reset: Read: SIOP Status Register (SSR) Write: See page 82. Reset: Read: SIOP Data Register (SDR) Write: See page 83. Reset: Reserved Unimplemented Unimplemented Read: Timer Control Register (TCR) Write: See page 72. Reset: Read: Timer Status Register (TSR) Write: See page 73. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
0 SPE 0 SPIF 0 DCOL
0 MSTR 0 0 0 0
0
0
0
0
$000A
0 0
0 0
0 0
0 0
$000B
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0 SDR7
0 SDR6
0 SDR5
0 SDR4
0 SDR3
0 SDR2
0 SDR1
0 SDR0
$000C
Unaffected by reset R R R R R R R R
$000D $000E $0011
NON-DISCLOSURE
0 ICIE 0 ICF OCIE 0 OCF TOIE 0 TOF 0 0
0
0 IEDG OLVL 0 0
$0012
0 0
0 0
U 0
$0013
U
U ICRH6
U ICRH5
0 ICRH4
0 ICRH3
0 ICRH2
0 ICRH1
0 ICRH0
$0014
Input Capture Register Read: ICRH7 (ICRH) Write: See page 70. Reset:
Unaffected by reset = Unimplemented R = Reserved U = Unaffected
Figure 2-3. I/O and Control Registers (Sheet 2 of 4)
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Freescale Semiconductor, Inc.
Memory Map I/O and Control Registers
Addr.
Register Name
Bit 7
6 ICRL6
5 ICRL5
4 ICRL4
3 ICRL3
2 ICRL2
1 ICRL1
Bit 0 ICRL0
$0015
Read: ICRL7 Input Capture Register (ICRL) Write: See page 70. Reset: Read: Output Compare Register OCRH7 (OCRH) Write: See page 68. Reset: Read: Output Compare Register OCRL7 (OCRL) Write: See page 68. Reset: Read: Timer Counter Register TMRH7 (TMRH) Write: See page 66. Reset: 1 Read: Timer Counter Register TMRL7 (TMRL) Write: See page 66. Reset: 1 Read: ACRH7 Alternate Counter Register (ACRH) Write: See page 66. Reset: 1 Read: ACRL7 Alternate Counter Register (ACRL) Write: See page 66. Reset: 1 Read: EEPROM Programming Register (EEPROG) Write: See page 86. Reset: Read: A/D Conversion Value Data Register (ADC) Write: See page 96. Reset: 0
Unaffected by reset OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0
$0016
Unaffected by reset OCRL6 OCRL5 OCRL4 OCRL3 OCRL2 OCRL1 OCRL0
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$0017
Unaffected by reset TMRH6 1 TMRL6 1 ACRH6 TMRH5 1 TMRL5 1 ACRH5 TMRH4 1 TMRL4 1 ACRH4 TMRH3 1 TMRL3 1 ACRH3 TMRH2 1 TMRL2 1 ACRH2 TMRH1 1 TMRL1 1 ACRH1 TMRH0 1 TMRL0 1 ACRH0
$0018
$0019
1 ACRL6
1 ACRL5
1 ACRL4
1 ACRL3
1 ACRL2
1 ACRL1
1 ACRL0
$001B
1 CPEN
1 0
1 ER1
1 ER0 0 AD3
1 LATCH 0 AD2
1 EERC 0 AD1
1 EEPGM 0 AD0
$001C
0 AD7
0 AD6
0 AD5
0 AD4
$001D
Unaffected by reset = Unimplemented R = Reserved U = Unaffected
Figure 2-3. I/O and Control Registers (Sheet 3 of 4)
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NON-DISCLOSURE
$001A
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Memory Map REQUIRED
Addr.
Register Name Read: A/D Converter Status and Control Register (ADSCR) Write: See page 94. Reset: Reserved
Bit 7 CC
6 R
5 ADON 0 R
4 0
3 0
2 CH2
1 CH1 0 R
Bit 0 CH0 0 R
$001E
0 R
0 R
0 R R
0 R = Reserved
0 R
$001F
= Unimplemented
U = Unaffected
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AGREEMENT
Figure 2-3. I/O and Control Registers (Sheet 4 of 4)
2.5 RAM
The user RAM consists of 192 bytes (including the stack) at locations $0050-$010F. The stack begins at address $00FF. The stack pointer can access 64 bytes of RAM from $00FF to $00C0.
NOTE:
Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call.
NON-DISCLOSURE
2.6 ROM
There are 8064 bytes of user ROM available, consisting of: * * * 8000 bytes at locations $1FC0-$3EFF 48 bytes in page zero locations $0020-$004F 16 additional bytes for user vectors at locations $3FF0-$3FFF
NOTE:
Address space $3F00-$3FEF is reserved for test code. Unlike other M68HC05 devices, the MC68HC05P18A does not contain self-check code.
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Technical Data -- MC68HC05P18A
Section 3. Central Processor Unit (CPU)
3.1 Contents
3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
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3.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.4 Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.2 Introduction
This section describes the central processor unit (CPU) registers.
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Figure 3-1 shows the five CPU registers. CPU registers are not part of the memory map.
A
ACCUMULATOR (A)
7 X
0 INDEX REGISTER (X)
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AGREEMENT
15 0 0 0 0 0 0 0 0 1
6 1
5 SP
0 STACK POINTER (SP)
15 0 0
10 PCH
8
7 PCL
0 PROGRAM COUNTER (PC)
7 1 1
5 1
4 H I N Z
0 C CONDITION CODE REGISTER (CCR)
HALF-CARRY FLAG INTERRUPT MASK NEGATIVE FLAG ZERO FLAG CARRY/BORROW FLAG
NON-DISCLOSURE
Figure 3-1. Programming Model
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Central Processor Unit (CPU) CPU Registers
3.3.1 Accumulator The accumulator (A) is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and results of arithmetic and nonarithmetic operations.
Bit 7 Read: Write: 6 5 4 3 2 1 Bit 0
Freescale Semiconductor, Inc...
Reset:
Unaffected by reset
Figure 3-2. Accumulator (A)
3.3.2 Index Register In the indexed addressing modes, the CPU uses the byte in the index register (X) to determine the conditional address of the operand. The 8-bit index register can also serve as a temporary data storage location.
Bit 7 Read: Write: Reset: Unaffected by reset 6 5 4 3 2 1 Bit 0
Figure 3-3. Index Register (X)
3.3.3 Stack Pointer The stack pointer (SP) is a 16-bit register that contains the address of the next location on the stack. During a reset or after the reset stack pointer (RSP) instruction, the stack pointer is preset to $00FF. The address in the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
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The 10 most significant bits of the stack pointer are permanently fixed at 000000011, so the stack pointer produces addresses from $00C0 to $00FF. If subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00FF and begins writing over the previously stored data. A subroutine uses two stack locations. An interrupt uses five locations.
Bit 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
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AGREEMENT
Figure 3-4. Stack Pointer (SP)
3.3.4 Program Counter The program counter (PC) is a 16-bit register that contains the address of the next instruction or operand to be fetched. The two most significant bits of the program counter are ignored internally and appear as 00. Normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.
Bit 15 Read: 0 Write: Reset: 0 0 Loaded with vectors from $3FF3 and $3FFF 0 5 Bit 0
NON-DISCLOSURE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 3-5. Program Counter (PC)
Technical Data Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com
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Central Processor Unit (CPU) CPU Registers
3.3.5 Condition Code Register The condition code register (CCR) is an 8-bit register whose three most significant bits are permanently fixed at 111. The condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed. The following paragraphs describe the functions of the condition code register.
Bit 7 6 1 5 1 H Write: Reset: 1 1 1 U 1 U = Unaffected U U U I N Z C 4 3 2 1 Bit 0
Freescale Semiconductor, Inc...
= Unimplemented
Figure 3-6. Condition Code Register (CCR) Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an ADD or ADC operation. The halfcarry flag is required for binary coded decimal (BCD) arithmetic operations. Interrupt Mask Setting the interrupt mask disables interrupts. If an interrupt request occurs while the interrupt mask is logic 0, the CPU saves the CPU registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. If an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the CPU processes the latched interrupt as soon as the interrupt mask is cleared again. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its cleared state. After any reset, the interrupt mask is set and can be cleared only by a software instruction. Negative Flag The CPU sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result.
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NON-DISCLOSURE
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Read:
1
REQUIRED
Freescale Semiconductor, Inc. Central Processor Unit (CPU) REQUIRED
Zero Flag The CPU sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a result of $00. Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some logical operations and data manipulation instructions also clear or set the carry/borrow flag.
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AGREEMENT
3.4 Arithmetic/Logic Unit
The arithmetic/logic unit (ALU) performs the arithmetic and logical operations defined by the instruction set. The binary arithmetic circuits decode instructions and set up the ALU for the selected operation. Most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. Multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the ALU. The multiply instruction (MUL) requires 11 internal clock cycles to complete this chain of operations.
NON-DISCLOSURE
Technical Data Central Processor Unit (CPU) For More Information On This Product, Go to: www.freescale.com
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Technical Data -- MC68HC05P18A
Section 4. Interrupts
4.1 Contents
4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
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4.3
4.4 Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.4.1 Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.4.2 Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.4.3 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.4.3.1 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.4.3.2 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.4.3.3 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . .44 4.4.3.4 Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .44
4.2 Introduction
The MCU can be interrupted six different ways: 1. Non-maskable software interrupt instruction (SWI) 2. External asynchronous interrupt (IRQ) 3. Input capture interrupt (TIMER) 4. Output compare interrupt (TIMER) 5. Timer overflow interrupt (TIMER) 6. Port A interrupt, if selected as a mask option
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REQUIRED
Freescale Semiconductor, Inc. Interrupts REQUIRED 4.3 CPU Interrupt Processing
Interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is completed. When the current instruction is completed, the processor checks all pending hardware interrupts. If interrupts are not masked (I bit in the condition code register is clear), and the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing. Otherwise, the next instruction is fetched and executed. The SWI is executed the same as any other instruction, regardless of the I-bit state. When an interrupt is to be processed, the CPU puts the register contents on the stack, sets the I bit in the CCR, and fetches the address of the corresponding interrupt service routine from the vector table at locations $3FF0-$3FFF. If more than one interrupt is pending when the interrupt vector is fetched, the interrupt with the highest vector location, shown in Table 4-1, is serviced first. Table 4-1. Vector Address for Interrupts and Reset
Register N/A N/A N/A TSR TSR TSR N/A N/A N/A N/A Flag Name N/A N/A N/A ICF OCF TOF N/A N/A N/A N/A Reset Software External interrupt Timer input capture Timer output compare Timer overflow Unimplemented Unimplemented Unimplemented Unimplemented Interrupts CPU Interrupt RESET SWI IRQ TIMER TIMER TIMER N/A N/A N/A N/A Vector Address $3FFE-$3FFF $3FFC-$3FFD $3FFA-$3FFB $3FF8-$3FF9 $3FF8-$3FF9 $3FF8-$3FF9 $3FF6-$3FF7 $3FF4-$3FF5 $3FF2-$3FF3 $3FF0-$3FF1
NON-DISCLOSURE
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A return-from-interrupt (RTI) instruction is used to signify when the interrupt software service routine is completed. The RTI instruction
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Interrupts CPU Interrupt Processing
causes the CPU state to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. Figure 4-1 shows the sequence of events that occur during interrupt processing.
FROM RESET
Y
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N IRQ INTERRUPT? N TIMER INTERRUPT? N Y Y CLEAR IRQ REQUEST LATCH
STACK PC, X, A, CC
SET I BIT IN CCR
FETCH NEXT INSTRUCTION
SWI INSTRUCTION? N RTI INSTRUCTION? N EXECUTE INSTRUCTION
Y
Y
RESTORE REGISTERS FROM STACK CC, A, X, PC
Figure 4-1. Interrupt Processing Flowchart
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Technical Data
NON-DISCLOSURE
LOAD PC FROM SWI: $3FFC AND $3FFD IRQ: $3FFA-$3FFB TIMER: $3FF8-$3FF9
AGREEMENT
IS I BIT SET?
REQUIRED
Freescale Semiconductor, Inc. Interrupts REQUIRED 4.4 Interrupt Types
The interrupts fall into these three categories which are discussed here: * * * Reset interrupt sequence Software interrupt (SWI) Hardware interrupts
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AGREEMENT
4.4.1 Reset Interrupt Sequence The reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in Figure 4-1. A low-level input on the RESET pin or internally generated RST signal causes: * * * The program to vector to its starting address, which is specified by the contents of memory locations $3FFE and $3FFF The I bit in the condition code register (CCR) to be set The MCU to be configured to a known state as described in Section 5. Resets.
NON-DISCLOSURE
4.4.2 Software Interrupt (SWI) The SWI is an executable instruction. It is also a non-maskable interrupt since it is executed regardless of the state of the I bit in the CCR. As with any instruction, interrupts pending during the previous instruction are serviced before the SWI opcode is fetched. The interrupt service routine address for the SWI instruction is specified by the contents of memory locations $3FFC and $3FFD.
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Interrupts Interrupt Types
4.4.3 Hardware Interrupts All hardware interrupts are maskable by the I bit in the CCR. If the I bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I bit enables the hardware interrupts. The four hardware interrupts are explained here: * * External interrupt (IRQ) Input capture interrupt Output compare interrupt Timer overflow interrupt
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*
4.4.3.1 External Interrupt (IRQ) The IRQ pin drives an asynchronous interrupt to the CPU. An edge detector flip-flop is latched on the falling edge of IRQ. If either the output from the internal edge detector flip-flop or the level on the IRQ pin is low, a request is synchronized to the CPU to generate the IRQ interrupt. If the edge-sensitive only mask option is selected, the output of the internal edge detector flip-flop is sampled and the input level on the IRQ pin is ignored. If port A interrupts are selected as a mask option, a port A interrupt uses the same vector. The interrupt service routine address is specified by the contents of memory locations $3FFA and $3FFB.
NOTE:
The internal interrupt latch is cleared 9 PH2 clock cycles after the interrupt is recognized (after location $3FFA is read). Therefore, another external interrupt pulse could be latched during the IRQ service routine. When the edge- and level-sensitive mask option is selected, the voltage applied to the IRQ pin must return to the high state before the returnfrom-interrupt (RTI) instruction in the interrupt service routine is executed.
4.4.3.2 Input Capture Interrupt The input capture interrupt is generated by the 16-bit timer as described in Section 8. 16-Bit Timer. The input capture interrupt flag is located in
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*
REQUIRED
Freescale Semiconductor, Inc. Interrupts REQUIRED
the timer status register (TSR) and its corresponding enable bit can be found in the timer control register (TCR). The I bit in the CCR must be clear in order for the input capture interrupt to be enabled. The interrupt service routine address is specified by the contents of memory locations $3FF8 and $3FF9. 4.4.3.3 Output Compare Interrupt The output compare interrupt is generated by the 16-bit timer as described in Section 8. 16-Bit Timer. The output compare interrupt flag is located in register TSR and its corresponding enable bit can be found in register TCR. The I bit in the CCR must be clear in order for the output compare interrupt to be enabled. The interrupt service routine address is specified by the contents of memory locations $3FF8 and $3FF9. 4.4.3.4 Timer Overflow Interrupt The timer overflow interrupt is generated by the 16-bit timer as described in Section 8. 16-Bit Timer. The timer overflow interrupt flag is located in register TSR and its corresponding enable bit can be found in register TCR. The I bit in the CCR must be clear in order for the timer overflow interrupt to be enabled. This internal interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $3FF8 and $3FF9.
NON-DISCLOSURE
Technical Data
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Technical Data -- MC68HC05P18A
Section 5. Resets
5.1 Contents
5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Freescale Semiconductor, Inc...
5.3
5.4 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.4.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.4.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . .47 5.4.3 Low-Voltage Reset (LVR). . . . . . . . . . . . . . . . . . . . . . . . . . .48
5.2 Introduction
The MCU can be reset from four sources: * * One external input Three internal reset conditions
The RESET pin is an input with a Schmitt trigger as shown in Figure 5-1. The CPU and all peripheral modules are reset by the internal reset signal (RST), which is the logical OR of internal reset functions and is clocked by PH2.
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IRQ
TO IRQ LOGIC
RESET
PULSE WIDTH = 4 X E-CLK PH2
CLOCKED ONE-SHOT
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AGREEMENT
OSC DATA ADDRESS VDD VDD
COP WATCHDOG (COPR) LOW-VOLTAGE RESET (LVR) POWER-ON RESET (POR) PH2 CPU S D LATCH RST TO OTHER PERIPHERALS
Figure 5-1. Reset Block Diagram
5.3 External Reset (RESET)
The RESET input is the only external reset and is connected to an internal Schmitt trigger. The external reset occurs whenever the RESET input is driven below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. The upper and lower thresholds are given in Section 13. Electrical Specifications.
NON-DISCLOSURE
5.4 Internal Resets
The three internally generated resets are: * * * Initial power-on reset (POR) Computer operating properly (COP) watchdog timer Low-voltage reset (LVR)
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Resets Internal Resets
5.4.1 Power-On Reset (POR) The internal POR is generated at power-up to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and should not be used to detect a drop in the power supply voltage. There is a 4064 PH2 clock cycle oscillator stabilization delay after the oscillator becomes active. The POR generates the RST signal and resets the MCU. At the same time, the POR pulls the RESET pin low allowing external devices to be reset with the MCU. If any other reset function is active at the end of this 4064 PH2 clock cycle delay, the RST signal remains active until the other reset condition(s) end.
Freescale Semiconductor, Inc...
5.4.2 Computer Operating Properly (COP) Reset When the COP watchdog timer is enabled by mask option, the internal COP reset is generated automatically by a timeout of the COP watchdog timer. This timer is implemented with an 18-stage ripple counter that provides a timeout period of 65.5 ms when a 4-MHz oscillator is used. The COP watchdog counter is cleared by writing a logical 0 to bit 0 at location $3FF0. The COP register is shared with the most-significant bit (MSB) of an unimplemented user interrupt vector, as shown in Figure 5-2. Reading this location returns the MSB of the unimplemented user interrupt vector. Writing to this location clears the COP watchdog timer.
Address: $3FF0 Bit 7 Read: Write: Reset: R = Reserved 0 R Unaffected by reset = Unimplemented 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0 COPR
Figure 5-2. COP Register (COPR)
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REQUIRED
Freescale Semiconductor, Inc. Resets REQUIRED
5.4.3 Low-Voltage Reset (LVR) The internal LVR reset is generated when the supply voltage to the VDD pin falls below a nominal 3.80 Vdc. The LVR threshold is not intended to be an accurate and stable trip point, but is intended to assure that the CPU is held in reset when the VDD supply voltage is below reasonable operating limits. If the LVR is tripped for a short time, the LVR reset signal will last at least two cycles of the CPU bus clock, PH2. A mask option is provided to disable the LVR. The LVR generates the RST signal, which resets the CPU and other peripherals. If any other reset function is active at the end of the LVR reset signal, the RST signal remains in the reset condition until the other reset condition(s) end.
NON-DISCLOSURE
Technical Data Resets For More Information On This Product, Go to: www.freescale.com
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MC68HC05P18A
Freescale Semiconductor, Inc.
Technical Data -- MC68HC05P18A
Section 6. Operating Modes
6.1 Contents
6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Freescale Semiconductor, Inc...
6.3
6.4 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 6.4.1 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 6.4.1.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 6.4.1.2 Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.4.2 WAIT Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.5 COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . .54
6.2 Introduction
The MC68HC05P18A has one user mode of operation and several lowpower modes which are described in this section.
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Freescale Semiconductor, Inc. Operating Modes REQUIRED 6.3 User Mode
The user mode allows the MCU to function as a self-contained microcontroller, with maximum use of the pins for on-chip peripheral functions. All address and data activity occurs within the MCU and is not available externally. User mode is entered on the rising edge of RESET if the IRQ pin is within the normal operating voltage range. In the user mode, there is: * * * * An 8-bit input/output (I/O) port A second 8-bit I/O port shared with the analog-to-digital (A/D) subsystem One 3-bit I/O port shared with the serial input/output port (SIOP) One 2-bit I/O port shared with the 16-bit timer subsystem
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6.4 Low-Power Modes
The MC68HC05P18A is capable of running in a low-power mode in each of its configurations. The WAIT and STOP instructions provide three modes that reduce the power required for the MCU by stopping various internal clocks and/or the on-chip oscillator. The STOP and WAIT instructions are not normally used if the computer operating properly (COP) watchdog timer is enabled. The stop conversion mask option is used to modify the behavior of the STOP instruction from stop mode to halt mode. The flow of the stop, halt, and wait modes is shown in Figure 6-1.
NON-DISCLOSURE
Technical Data
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Freescale Semiconductor, Inc.
Operating Modes Low-Power Modes
STOP
HALT
WAIT
STOP TO HALT MASK OPTION? N
Y
EXTERNAL OSCILLATOR ACTIVE AND INTERNAL TIMER CLOCK ACTIVE
STOP EXTERNAL OSCILLATOR STOP INTERNAL TIMER CLOCK RESET STARTUP DELAY
STOP RC OSCILLATOR STOP INTERNAL PROCESSOR CLOCK CLEAR I BIT IN CCR
EXTERNAL OSCILLATOR ACTIVE AND INTERNAL TIMER CLOCK ACTIVE
Freescale Semiconductor, Inc...
STOP RC OSCILLATOR STOP INTERNAL PROCESSOR CLOCK CLEAR I BIT IN CCR
Y
LVR OR EXTERNAL RESET? N
LVR OR EXTERNAL RESET? N IRQ EXTERNAL INTERRUPT? N
Y
Y
IRQ EXTERNAL INTERRUPT? N
Y
LVR OR EXTERNAL RESET? N
Y RESTART EXTERNAL OSCILLATOR START STABILIZATION DELAY
Y
TIMER INTERNAL INTERRUPT? N
Y
IRQ EXTERNAL INTERRUPT? N
Y
END OF STABILIZATION DELAY? N
Y
N Y
N COP INTERNAL RESET? N
RESTART INTERNAL PROCESSOR CLOCK
1. 2.
FETCH RESET VECTOR OR SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE
Figure 6-1. Stop, Halt, and Wait Modes Flowchart
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Technical Data
NON-DISCLOSURE
COP INTERNAL RESET?
Y
TIMER INTERNAL INTERRUPT?
AGREEMENT
STOP INTERNAL PROCESSOR CLOCK CLEAR I BIT IN CCR
REQUIRED
Freescale Semiconductor, Inc. Operating Modes REQUIRED
6.4.1 STOP Instruction The STOP instruction can result in one of two modes of operation, depending on the mask option. 1. If the stop conversion to halt mask option is not chosen, the STOP instruction behaves like a normal STOP instruction in the M68HC05 Family and places the MCU in stop mode. 2. If the stop conversion to halt mask option is chosen, the STOP instruction behaves like a WAIT instruction (with the exception of a brief delay at startup) and places the MCU in halt mode. 6.4.1.1 Stop Mode Execution of the STOP instruction without conversion to halt places the MCU in its lowest power consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing, including the COP watchdog timer. The RC oscillator that feeds the electrically erasable programmable read-only memory (EEPROM) and the A/D converter is also stopped. Execution of the STOP instruction automatically clears the I bit in the condition code register so that the IRQ external interrupt is enabled. All other registers and memory remain unaltered. All input/output lines remain unchanged. The MCU can be brought out of the stop mode only by: * * * An IRQ external interrupt Port A external interrupt, if selected as a mask option An externally generated reset
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When exiting stop mode, the internal oscillator resumes after a 4064 PH2 clock cycle oscillator stabilization delay.
NOTE:
Execution of the STOP instruction without conversion to halt (via mask option) causes the oscillator to stop, and therefore disable the COP watchdog timer. If the COP watchdog timer is to be used, stop mode should be changed to halt mode by selecting the appropriate mask option.
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Freescale Semiconductor, Inc.
Operating Modes Low-Power Modes
6.4.1.2 Halt Mode Execution of the STOP instruction with the conversion to halt places the MCU in this low-power mode. Halt mode consumes the same amount of power as wait mode.
NOTE:
Both halt and wait modes consume more power than stop mode. In halt mode the PH2 clock is halted, suspending all processor and internal bus activity. Internal timer clocks remain active, permitting interrupts to be generated from the 16-bit timer or a reset to be generated from the COP watchdog timer. Execution of the STOP instruction automatically clears the I bit in the condition code register, enabling the IRQ external interrupt. All other registers, memory, and input/output lines remain in their previous states. If the 16-bit timer interrupt is enabled, it causes the processor to exit halt mode and resume normal operation. Halt mode also can be exited when an IRQ external interrupt or external RESET occurs. When exiting halt mode, the PH2 clock resumes after a delay of one to 4064 PH2 clock cycles. This varied delay time is the result of the halt mode exit circuitry testing the oscillator stabilization delay timer (a feature of stop mode) which has been free-running (a feature of wait mode).
Freescale Semiconductor, Inc...
NOTE:
Halt mode is not intended for normal use. This feature is provided to keep the COP watchdog timer active in the event a STOP instruction is inadvertently executed.
6.4.2 WAIT Instruction The WAIT instruction places the MCU in a low-power mode, which consumes more power than stop mode. In wait mode, the PH2 clock is halted, suspending all processor and internal bus activity. Internal timer clocks remain active, permitting interrupts to be generated from the 16bit timer and reset to be generated from the COP watchdog timer. Execution of the WAIT instruction automatically clears the I bit in the condition code register, enabling the IRQ external interrupt. All other registers, memory, and input/output lines remain in their previous state.
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Freescale Semiconductor, Inc. Operating Modes REQUIRED
If the 16-bit timer interrupt is enabled, it causes the processor to exit wait mode and resume normal operation. The 16-bit timer may be used to generate a periodic exit from wait mode. Wait mode may also be exited when an IRQ or RESET occurs.
NOTE:
If port A interrupts are selected as a mask option, the processor also will exit wait mode.
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AGREEMENT
6.5 COP Watchdog Timer Considerations
The COP watchdog timer is active in the user mode of operation when selected by mask option. Executing the STOP instruction without conversion to halt via mask option causes the COP to be disabled. Therefore, it is recommended that the STOP instruction be modified to produce halt mode via mask option if the COP watchdog timer is enabled. Furthermore, it is recommended that the COP watchdog timer be disabled for applications that use the halt or wait mode for time periods that exceed the COP timeout period. COP watchdog timer interactions are summarized in Table 6-1. Table 6-1. COP Watchdog Timer Recommendations
IF These Conditions Exist: STOP Instruction Halt mode selected via mask option Halt mode selected via mask option Stop mode selected via mask option WAIT Time WAIT time less than COP timeout WAIT time MORE than COP timeout Any length WAIT time THEN the COP Watchdog Timer Should: Enable or disable COP via mask option Disable COP via mask option Disable COP via mask option
NON-DISCLOSURE
Technical Data
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Technical Data -- MC68HC05P18A
Section 7. Input/Output (I/O) Ports
7.1 Contents
7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
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7.3 7.4 7.5 7.6 7.7
7.2 Introduction
In user mode, 20 bidirectional input/output (I/O) lines are arranged as: * * * Two 8-bit I/O ports, port A and port C One 3-bit I/O port, port B One 1-bit I/O port, port D
These ports are programmable as either inputs or outputs under software control of the data direction registers (DDRs). There is also an input-only pin associated with port D.
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REQUIRED
Freescale Semiconductor, Inc. Input/Output (I/O) Ports REQUIRED 7.3 Port A
Port A is an 8-bit bidirectional port which can share its pins with the IRQ interrupt system, as shown in Figure 7-1. Each port A pin is controlled by the corresponding bits in a data direction register and a data register. The port a data register is located at address $0000. The port A data direction register (DDRA) is located at address $0004. Reset clears the DDRA thereby initializing port A as an input port. The port A data register is unaffected by reset.
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AGREEMENT
READ $0004 WRITE $0004
DATA DIRECTION REGISTER BIT DATA REGISTER BIT OUTPUT I/O PIN
WRITE $0000
READ $0000
100 A PULLUP INTERNAL HC05 DATA BUS RESET (RST) MASK OPTION (PULLUP INHIBIT) VDD
NON-DISCLOSURE
TO IRQ INTERRUPT SYSTEM
Figure 7-1. Port A I/O Circuitry
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Input/Output (I/O) Ports Port B
7.4 Port B
Port B is a 3-bit bidirectional port that can share pins PB5-PB7 with the serial input/output port (SIOP) communications subsystem. The port B data register is located at address $0001 and its data direction register (DDR) is located at address $0005. Reset does not affect the data registers, but clears the DDRs, thereby setting all of the port pins to input mode. Writing a 1 to a DDR bit sets the corresponding port pin to output mode (see Figure 7-2).
Freescale Semiconductor, Inc...
READ $0005 WRITE $0005 RESET (RST) WRITE $0001
DATA DIRECTION REGISTER BIT DATA REGISTER BIT OUTPUT I/O PIN
READ $0001 INTERNAL HC05 DATA BUS
Figure 7-2. Port B I/O Circuitry
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Port B may be used for general I/O applications when the SIOP subsystem is disabled. The SPE bit in register SIOP control register (SPCR) is used to enable/disable the SIOP subsystem. When the SIOP subsystem is enabled, port B registers are still accessible to software. Writing to either of the port B registers while a data transfer is under way could corrupt the data. See Section 9. Serial Input/Output Ports (SIOP) for a discussion of the SIOP subsystem.
REQUIRED
Freescale Semiconductor, Inc. Input/Output (I/O) Ports REQUIRED 7.5 Port C
Port C is an 8-bit bidirectional port that can share pins PC3-PC7 with the analog-to-digital (A/D) converter subsystem. The port C data register is located at address $0002 and its data direction register (DDR) is located at address $0006. Reset does not affect the data registers, but clears the DDRs, thereby setting all of the port pins to input mode. Writing a 1 to a DDR bit sets the corresponding port pin to output mode (see Figure 7-3). Two port C pins, PC0 and PC1, can source and sink a higher current than a typical I/O pin. See Section 13. Electrical Specifications regarding current specifications. Port C may be used for general I/O applications when the A/D subsystem is disabled. The ADON bit in the A/D status and control register (ADSC) is used to enable/disable the A/D subsystem.
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AGREEMENT
CAUTION:
Care must be exercised when using pins PC0-PC2 while the A/D subsystem is enabled. Accidental changes to bits that affect pins PC3-PC7 in the data or DDR registers will produce unpredictable results in the A/D subsystem. See Section 11. Analog-to-Digital (A/D) Converter.
NON-DISCLOSURE
READ $0006 WRITE $0006 RESET (RST) WRITE $0002 HIGH CURRENT CAPABILITY, PC0 AND PC1 ONLY I/O PIN
DATA DIRECTION REGISTER BIT DATA REGISTER BIT OUTPUT
READ $0002 INTERNAL HC05 DATA BUS
Figure 7-3. Port C I/O Circuitry
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Input/Output (I/O) Ports Port D
7.6 Port D
Port D is a 2-bit port with: * * One bidirectional pin, PD5/CKOUT One input-only pin, PD7
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Port D may be used for general I/O applications regardless of the state of the 16-bit timer. Since PD7 is an input-only line, its state can be read from the port D data register at any time.
READ $0007 WRITE $0007 RESET (RST) WRITE $0003
DATA REGISTER BIT
OUTPUT
I/O PIN
READ $0003 INTERNAL HC05 DATA BUS
Figure 7-4. Port D I/O Circuitry
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DATA DIRECTION REGISTER BIT
AGREEMENT
Pin PD7 is shared with the 16-bit timer. There is a mask option to have PD5 replaced with the clock output. The port D data register is located at address $0003 and its data direction register (DDR) is located at address $0007. Reset does not affect the data registers, but clears the DDRs, thereby setting PD5/CKOUT to input mode. Writing a 1 to DDR bit 5 sets PD5/CKOUT to output mode (see Figure 7-4).
REQUIRED
Freescale Semiconductor, Inc. Input/Output (I/O) Ports REQUIRED 7.7 I/O Port Programming
Each pin on ports A through port D, with the exception of pin 7 of port D, may be programmed as an input or an output under software control as shown in Table 7-1, Table 7-2, Table 7-3, and Table 7-4. The direction of a pin is determined by the state of its corresponding bit in the associated port data direction register (DDR). A pin is configured as an output if its corresponding DDR bit is set to a logic 1. A pin is configured as an input if its corresponding DDR bit is cleared to a logic 0. Table 7-1. Port A I/O Pin Functions
DDRA I/O Pin Mode Access to DDRA @ $0004 Read/Write 0 1 In, Hi-Z Out DDRA0-DDRA7 DDRA0-DDRA7 Access to Data Register @ $0000 Read I/O pin PA0-PA7 Write See note PA0-PA7
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AGREEMENT
Note: Does not affect input, but stored to data register
Table 7-2. Port B I/O Pin Functions
DDRB I/O Pin Mode Access to DDRB @ $0005 Read/Write 0 1 In, Hi-Z Out DDRB5-DDRB7 DDRB5-DDRB7 Access to Data Register @ $0001 Read I/O pin PB5-PB7 Write See note PB5-PB7
NON-DISCLOSURE
Note: Does not affect input, but stored to data register
Table 7-3. Port C I/O Pin Functions
DDRC I/O Pin Mode Access to DDRC @ $0006 Read/Write 0 1 In, Hi-Z Out DDRC0-DDRC7 DDRC0-DDRC7 Access to Data Register @ $0002 Read I/O pin PC0-PC7 Write See note PC0-PC7
Note: Does not affect input, but stored to data register
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Input/Output (I/O) Ports I/O Port Programming
Table 7-4. Port D I/O Pin Functions
DDRD I/O Pin Mode Access to DDRD @ $0007 Read/Write 0 1 In, Hi-Z Out DDRD5 DDRD5 Access to Data Register @ $0003 Read I/O pin PD5/CKOUT Write See note PD5/CKOUT
Note: Does not affect input, but stored to data register PD7 is input only.
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NOTE:
To avoid generating a glitch on an I/O port pin, data should be written to the I/O port data register before writing a logical 1 to the corresponding data direction register.
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Freescale Semiconductor, Inc. Input/Output (I/O) Ports REQUIRED NON-DISCLOSURE
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Technical Data -- MC68HC05P18A
Section 8. 16-Bit Timer
8.1 Contents
8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Timer Operation during Wait Mode and Halt Mode . . . . . . . . .74 Timer Operating during Stop Mode . . . . . . . . . . . . . . . . . . . . .74
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8.3 8.4 8.5 8.6 8.7 8.8 8.9
8.2 Introduction
The MC68HC05P18A MCU contains a single 16-bit programmable timer with an input capture function and an output compare function. The 16bit timer is driven by the output of a fixed divide-by-four prescaler operating from the PH2 clock. The 16-bit timer may be used for many applications, including input waveform measurement while simultaneously generating an output waveform. Pulse widths can vary from microseconds to seconds depending on the oscillator frequency selected. The 16-bit timer is also capable of generating periodic interrupts. See Figure 8-1.
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Freescale Semiconductor, Inc. 16-Bit Timer REQUIRED
INTERNAL HC05 BUS
OUTPUT COMPARE
BUFFER FREERUNNING COUNTER
PH2 CLOCK
INPUT CAPTURE
OCRH
OCRL
ICRH
ICRL
TMRH/ACRH TMRL/ACRL
/4
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AGREEMENT
COMPARE DETECTOR
OVERFLOW DETECTOR
EDGE DETECTOR
TCAP
D > R TIMER STATUS REGISTER OCF TOF ICF
Q
TCMP
RESET
NON-DISCLOSURE
INTERRUPT GENERATOR
TIMER INTERRUPT
OCIE
TOIE
ICIE
IEDG
OLVL
TIMER CONTROL REGISTER
Figure 8-1. 16-Bit Timer Block Diagram
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16-Bit Timer Timer
Because the timer has a 16-bit architecture, each function is represented by two registers. Each register pair contains the high and low byte of that function. Generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed.
NOTE:
The I bit in the condition code register (CCR) should be set while manipulating both the high and low byte registers of a specific timer function. This prevents interrupts from occurring between the time that the high and low bytes are accessed.
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8.3 Timer
The key element of the programmable timer is a 16-bit free-running counter, or timer registers, preceded by a prescaler, which divides the PH2 clock by four. The prescaler gives the timer a resolution of 2.0 ms when a 4-MHz crystal is used. The counter is incremented to increasing values during the low portion of the PH2 clock cycle. The double byte free-running counter can be read from either of two locations: * * The timer registers, TMRH and TMRL The alternate counter registers, ACRH and ACRL
Both locations will contain identical values. A read sequence containing only a read of the least-significant bit (LSB) of the counter (TMRL/ACRL) returns the count value at the time of the read. If a read of the counter accesses the most-significant bit (MSB) first (TMRH/ACRH), it causes the LSB (TMRL/ACRL) to be transferred to a buffer. This buffer value remains fixed after the first MSB byte read even if the MSB is read several times. The buffer is accessed when reading the counter LSB (TMRL/ACRL), and thus completes a read sequence of the total counter value. When reading either the timer or alternate counter registers, if the MSB is read, the LSB must also be read to complete the read sequence. See Figure 8-2 and Figure 8-3.
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Freescale Semiconductor, Inc. 16-Bit Timer REQUIRED
Address:
$0018 Bit 7 6 TMRH6 5 TMRH5 4 TMRH4 3 TMRH3 2 TMRH2 1 TMRH1 Bit 0 TMRH0
Read: Write: Reset: Address:
TMRH7
1 $0019 Bit 7
1
1
1
1
1
1
1
6 TMRL6
5 TMRL5
4 TMRL4
3 TMRL3
2 TMRL2
1 TMRL1
Bit 0 TMRL0
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AGREEMENT
Read: Write: Reset:
TMRL7
1
1
1
1
1
1
1
1
= Unimplemented
Figure 8-2. Timer Counter Registers (TMRH/TMRL)
Address: $001A Bit 7 Read: Write: Reset: Address: 1 $001B Bit 7 Read: Write: Reset: 1 1 1 1 1 1 1 1 ACRL7 6 ACRL6 5 ACRL5 4 ACRL4 3 ACRL3 2 ACRL2 1 ACRL1 Bit 0 ACRL0 1 1 1 1 1 1 1 ACRH7 6 ACRH6 5 ACRH5 4 ACRH4 3 ACRH3 2 ACRH2 1 ACRH1 Bit 0 ACRH0
NON-DISCLOSURE
= Unimplemented
Figure 8-3. Alternate Counter Registers (ACRH/ACRL) The timer registers and alternate counter registers can be read at any time without affecting their values. However, the alternate counter registers differ from the timer registers in one respect: A read of the timer register MSB can clear the timer overflow flag (TOF). Therefore, the alternate counter registers can be read at any time without the possibility
Technical Data 16-Bit Timer For More Information On This Product, Go to: www.freescale.com MC68HC05P18A
Freescale Semiconductor, Inc.
16-Bit Timer Timer
of missing timer overflow interrupts due to clearing of the TOF. See Figure 8-4. The free-running counter is initialized to $FFFC during reset and is a read-only register. During power-on reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator startup delay. Since the counter is 16 bits preceded by a fixed divide-by-four prescaler, the value in the counter repeats every 262,144 PH2 clock cycles (524,288 oscillator cycles). When the free-running counter rolls over from $FFFF to $0000, the timer overflow flag bit (TOF) in the timer status register (TSR) is set. An interrupt can also be enabled when counter rollover occurs by setting the timer overflow interrupt enable bit (TOIE) in the timer control register (TCR). See Figure 8-5.
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PH2 CLOCK
16-BIT FREE-RUNNING COUNTER TIMER OVERFLOW FLAG (TOF)
$FFFE
$FFFF
$0000
$0001
$0002
Figure 8-4. State Timing Diagram for Timer Overflow
PH2 CLOCK
INTERNAL RESET
16-BIT FREE-RUNNING COUNTER RESET (EXTERNAL OR OTHER)
$FFFC
$FFFD
$FFFE
$FFFF
Note: The counter and control registers are the only 16-bit timer registers affected by reset.
Figure 8-5. State Timing Diagram for Timer Reset
MC68HC05P18A 16-Bit Timer For More Information On This Product, Go to: www.freescale.com Technical Data
NON-DISCLOSURE
Note: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by reading the timer status register (TSR) during the high portion of the PH2 clock followed by reading the LSB of the counter register pair (TCRL).
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. 16-Bit Timer REQUIRED 8.4 Output Compare
The output compare function may be used to generate an output waveform and/or as an elapsed time indicator. All of the bits in the output compare register pair, OCRH/OCRL, are readable and writable and are not altered by the 16-bit timer's control logic. Reset does not affect the contents of these registers. If the output compare function is not utilized, its registers may be used for data storage. See Figure 8-6.
Address: $0016 Bit 7 Read: OCRH7 Write: Reset: Address: $0017 Bit 7 Read: OCRL7 Write: Reset: Unaffected by reset OCRL6 OCRL5 OCRL4 OCRL3 OCRL2 OCRL1 OCRL0 6 5 4 3 2 1 Bit 0 Unaffected by reset OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0 6 5 4 3 2 1 Bit 0
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Figure 8-6. Output Compare Registers (OCRH/OCRL) The contents of the output compare registers are compared with the contents of the free-running counter once every four PH2 clock cycles. If a match is found, the output compare flag bit (OCF) is set and the output level bit (OLVL) is clocked to the output latch. The values in the output compare registers and output level bit should be changed after each successful comparison to control an output waveform or to establish a new elapsed timeout. An interrupt can also accompany a successful output compare if the output compare interrupt enable bit (OCIE) is set. After a CPU write cycle to the MSB of the output compare register pair (OCRH), the output compare function is inhibited until the LSB (OCRL) is written. Both bytes must be written if the MSB is written. A write made only to the LSB will not inhibit the compare function. The free-running
Technical Data 16-Bit Timer For More Information On This Product, Go to: www.freescale.com MC68HC05P18A
Freescale Semiconductor, Inc.
16-Bit Timer Output Compare
counter increments every four PH2 clock cycles. The minimum time required to update the output compare registers is a function of software rather than hardware. The output compare output level bit (OLVL) will be clocked to its output latch regardless of the state of the output compare flag bit (OCF). A valid output compare must occur before the OLVL bit is clocked to its output latch (TCMP). Since neither the output compare flag (OCF) nor the output compare registers are affected by reset, care must be exercised when initializing the output compare function. This procedure is recommended: 1. Block interrupts by setting the I bit in the condition code register (CCR). 2. Write the MSB of the output compare register pair (OCRH) to inhibit further compares until the LSB is written. 3. Read the timer status register (TSR) to arm the output compare flag (OCF). 4. Write the LSB of the output compare register pair (OCRL) to enable the output compare function and to clear its flag and interrupt. 5. Unblock interrupts by clearing the I bit in the CCR. This procedure prevents the output compare flag bit (OCF) from being set between the time it is read and the time the output compare registers are updated. A software example is shown in Figure 8-7.
9B * * B6 BE B7 B6 BF * SEI * * LDA LDX STA LDA STX * BLOCK INTERRUPTS * * HI BYTE FOR COMPARE LOW BYTE FOR COMPARE INHIBIT OUTPUT COMPARE ARM OCF BIT TO CLEAR READY FOR NEXT COMPARE *
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* * XX XX 16 13 17 *
* * DATAH DATAL OCRH TSR OCRL *
Figure 8-7. Output Compare Software Initialization Example
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Freescale Semiconductor, Inc. 16-Bit Timer REQUIRED 8.5 Input Capture
Two 8-bit read-only registers (ICRH and ICRL) make up the 16-bit input capture. They are used to latch the value of the free-running counter after a defined transition is sensed by the input capture edge detector.
NOTE:
The input capture edge detector contains a Schmitt trigger to improve noise immunity. The edge that triggers the counter transfer is defined by the input edge bit (IEDG) in TCR. Reset does not affect the contents of the input capture registers. See Figure 8-8.
Address: $0014 Bit 7 Read: Write: Reset: Address: $0015 Bit 7 Read: Write: Reset: Unaffected by reset ICRL7 6 ICRL6 5 ICRL5 4 ICRL4 3 ICRL3 2 ICRL2 1 ICRL1 Bit 0 ICRL0 Unaffected by reset ICRH7 6 ICRH6 5 ICRH5 4 ICRH4 3 ICRH3 2 ICRH2 1 ICRH1 Bit 0 ICRH0
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Figure 8-8. Input Capture Registers (ICRH/ICRL) The result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the PH2 clock preceding the external transition (see Figure 8-9). This delay is required for internal synchronization. Resolution is affected by the prescaler, allowing the free-running counter to increment once every four PH2 clock cycles. The contents of the free-running counter are transferred to the input capture registers on each proper signal transition regardless of the state of the input capture flag bit (ICF) in register TSR. The input capture registers always contain the free-running counter value which corresponds to the most recent input capture.
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16-Bit Timer Input Capture
After a read of the MSB of the input capture register pair (ICRH), counter transfers are inhibited until the LSB of the register pair (ICRL) is also read. This characteristic forces the minimum pulse period attainable to be determined by the time required to execute an input capture software routine in an application. Reading the LSB of the input capture register pair (ICRL) does not inhibit transfer of the free-running counter. Again, minimum pulse periods are ones which allow software to read the LSB of the register pair (ICRL) and perform needed operations. There is no conflict between reading the LSB (ICRL) and the free-running counter transfer since they occur on opposite edges of the PH2 clock.
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PH2 CLOCK
16-BIT FREE-RUNNING COUNTER
$FFEB
$FFEC
$FFED
$FFEE
$FFEF
TCAP PIN
INPUT CAPTURE LATCH INPUT CAPTURE REGISTER
(SEE NOTE)
$FFED
INPUT CAPTURE FLAG
Note: If the input edge occurs in the shaded area from one T10 timer state to the other T10 timer state, the input capture flag is set during the next T11 timer state.
Figure 8-9. State Timing Diagram for Input Capture
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The timer control (TCR) shown in Figure 8-10 and free-running counter (TMRH, TMRL, ACRH, ACRL) registers are the only registers of the 16bit timer affected by reset. The output compare port (TCMP) is forced low after reset and remains low until OLVL is set and a valid output compare occurs.
Address: $0012 Bit 7 Read: ICIE Write: Reset: 0 0 0 0 0 U = Unaffected 0 U 0 OCIE TOIE 6 5 4 0 3 0 2 0 IEDG OLVL 1 Bit 0
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Figure 8-10. Timer Control Register (TCR) ICIE -- Input Capture Interrupt Enable Bit Bit 7, when set, enables input capture interrupts to the CPU. The interrupt will occur at the same time bit 7 (ICF) in the TSR register is set. OCIE -- Output Comapre Interrupt Enable Bit Bit 6, when set, enables output compare interrupts to the CPU. The interrupt will occur at the same time bit 6 (OCF) in the TSR register is set. TOIE -- Timer Overflow Interrupt Enable Bit Bit 5, when set, enables timer overflow (rollover) interrupts to the CPU. The interrupt will occur at the same time bit 5 (TOF) in the TSR register is set. IEDG -- Input Capture Edge Select Bit Bit 1 selects which edge of the input capture signal will trigger a transfer of the contents of the free-running counter registers to the input capture registers. Clearing this bit will select the falling edge, setting it selects the rising edge.
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16-Bit Timer Timer Status Register
OLVL -- Output Compare Output Level Select Bit Bit 0 selects the output level (high or low) that is clocked into the output compare output latch at the next successful output compare.
8.7 Timer Status Register
Reading the timer status register (TSR) satisfies the first condition required to clear status flags and interrupts (see Figure 8-11). The only remaining step is to read (or write) the register associated with the active status flag (and/or interrupt). This method does not present any problems for input capture or output compare functions. However, a problem can occur when using a timer interrupt function and reading the free-running counter at random times to, for example, measure an elapsed time. If the proper precautions are not designed into the application software, a timer interrupt flag (TOF) could unintentionally be cleared if: 1. The TSR is read when bit 5 (TOF) is set. 2. The LSB of the free-running counter is read, but not for the purpose of servicing the flag or interrupt. The alternate counter registers (ACRH and ACRL) contain the same values as the timer registers (TMRH and TMRL). Registers ACRH and ACRL can be read at any time without affecting the timer overflow flag (TOF) or interrupt.
Address: $0013 Bit 7 Read: Write: Reset: U U U 0 0 U = Unaffected 0 0 0 ICF 6 OCF 5 TOF 4 0 3 0 2 0 1 0 Bit 0 0
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= Unimplemented
Figure 8-11. Timer Status Register (TSR)
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ICF -- Input Capture Flag Bit 7 is set when the edge specified by IEDG in register TCR has been sensed by the input capture edge detector fed by pin TCAP. This flag, and the input capture interrupt, can be cleared by reading register TSR followed by reading the LSB of the input capture register pair (ICRL). OCF -- Output Compare Bit Bit 6 is set when the contents of the output compare registers match the contents of the free-running counter. This flag, and the output compare interrupt, can be cleared by reading register TSR followed by writing the LSB of the output compare register pair (OCRL). TOF -- Timer Overflow Flag Bit 5 is set by a rollover of the free-running counter from $FFFF to $0000. This flag, and the timer overflow interrupt, can be cleared by reading register TSR followed by reading the LSB of the timer register pair (TMRL).
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8.8 Timer Operation during Wait Mode and Halt Mode
During wait mode and halt mode the 16-bit timer continues to operate normally and may generate an interrupt to trigger the MCU out of the wait mode and halt mode.
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8.9 Timer Operating during Stop Mode
When the MCU enters the stop mode, the free-running counter stops counting. (The PH2 clock is stopped.) It remains at that particular count value until the stop mode is exited by applying a low signal to the IRQ pin, at which time the counter resumes from its stopped value as if nothing had happened. If stop mode is exited via an external RESET (logic low applied to the RESET pin), the counter is forced to $FFFC. If a valid input capture edge occurs at the TCAP pin during stop mode, the input capture detect circuitry is armed. This action does not set any flags or wake up the MCU, but when the MCU does wake up there will
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16-Bit Timer Timer Operating during Stop Mode
be an active input capture flag (and data) from the first valid edge. If the stop mode is exited by an external RESET, no input capture flag or data will be present even if a valid input capture edge was detected during stop mode.
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Technical Data -- MC68HC05P18A
Section 9. Serial Input/Output Ports (SIOP)
9.1 Contents
9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
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9.3 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 9.3.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 9.3.2 Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.3.3 Serial Data Output (SDO). . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.4 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 9.4.1 SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 9.4.2 SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 9.4.3 SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
9.2 Introduction
The simple synchronous serial input/output (I/O) port (SIOP) subsystem is designed to provide efficient serial communications between peripheral devices or other MCUs. The SIOP is implemented as a 3-wire master/slave system with: * * * Serial clock (SCK) Serial data input (SDI) Serial data output (SDO)
A block diagram of the SIOP is shown in Figure 9-1. The SIOP subsystem shares its input/output pins with port B. When the SIOP is enabled, SPE bit set in the SIOP control register (SCR), port B data direction register (DDR), and data register are modified by the SIOP. Although port B DDR and data registers can be altered by
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Freescale Semiconductor, Inc. Serial Input/Output Ports (SIOP) REQUIRED
application software, these actions could affect the transmitted or received data.
HCO5 INTERNAL BUS
SPE
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76543210
76543210
76543210
BAUD CONTROL REGISTER $0A GENERATOR STATUS RATE REGISTER $0B
8-BIT SHIFT REGISTER $0C
SDO SDI
I/O CONTROL LOGIC
SDO/PB5
SDI/PB6
SCK PH2 CLOCK
SCK/PB7
Figure 9-1. SIOP Block Diagram
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9.3 SIOP Signal Format
The SIOP subsystem is software configurable for master or slave operation. There are no external mode selection inputs available (for example, slave select pin).
9.3.1 Serial Clock (SCK) The state of the SCK output normally remains a logic 1 during idle periods between data transfers. The first falling edge of SCK signals the beginning of a data transfer. At this time the first bit of received data is accepted at the SDI pin and the first bit of transmitted data is presented at the SDO pin (see Figure 9-2). Data is captured at the SDI pin on the rising edge of SCK, and the first bit of transmitted data is presented at the SDO pin. The transfer is terminated upon the eighth rising edge of SCK.
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Serial Input/Output Ports (SIOP) SIOP Signal Format
BIT 0 SDO
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
SCK 100 ns SDI BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 100 ns
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The master and slave modes of operation differ only by the sourcing of SCK. In master mode, SCK is driven from an internal source within the MCU. In slave mode, SCK is driven from a source external to the MCU. The SCK frequency is mask option selectable. Available rates are OSC divided by 2, 4, 8, or 16.
NOTE:
OSC divided by 2 is four times faster than the standard rate available on the 68HC05P6. Refer to 1.4 Mask Options for a description of available mask options.
9.3.2 Serial Data Input (SDI) The SDI pin becomes an input as soon as the SIOP subsystem is enabled. New data is presented to the SDI pin on the falling edge of SCK. Valid data must be present at least 100 ns before the rising edge of SCK and remain valid for 100 ns after the rising edge of SCK. See Figure 9-2.
9.3.3 Serial Data Output (SDO) The SDO pin becomes an output as soon as the SIOP subsystem is enabled. Prior to enabling the SIOP, PB5 can be initialized to determine the beginning state. While the SIOP is enabled, PB5 cannot be used as a standard output since that pin is connected to the last stage of the SIOP serial shift register. A mask option is included to allow the data to
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Figure 9-2. SIOP Timing Diagram
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Freescale Semiconductor, Inc. Serial Input/Output Ports (SIOP) REQUIRED
be transmitted in either most-significant bit (MSB) first format or the least-significant bit (LSB) format. On the first falling edge of SCK, the first data bit will be shifted out to the SDO pin. The remaining data bits will be shifted out to the SDI pin on subsequent falling edges of SCK. The SDO pin will present valid data at least 100 ns before the rising edge of the SCK and remain valid for 100 ns after the rising edge of SCK. See Figure 9-2.
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9.4 SIOP Registers
The SIOP is programmed and controlled by these registers: * * * SIOP control register (SCR) located at address $000A SIOP status register (SSR) located at address $000B SIOP data register (SDR) located at address $000C
9.4.1 SIOP Control Register This register is located at address $000A and contains two bits. Figure 9-3 shows the position of each bit in the register and indicates the value of each bit after reset.
Address: $000A Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 SPE 6 5 0 MSTR 4 3 0 2 0 1 0 Bit 0 0
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= Unimplemented
Figure 9-3. SIOP Control Register (SCR)
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Serial Input/Output Ports (SIOP) SIOP Registers
SPE -- Serial Peripheral Enable Bit When set, the SPE bit enables the SIOP subsystem such that SDO/PB5 is the serial data output, SDI/PB6 is the serial data input, and SCK/PB7 is a serial clock input in the slave mode or a serial clock output in the master mode. The port B DDR and data registers can be manipulated as usual (except for PB5); however, these actions could affect the transmitted or received data. The SPE bit is readable and writable at any time. Clearing the SPE bit while a transmission is in progress will:
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1. Abort the transmission 2. Reset the serial bit counter 3. Convert the port B/SIOP port to a general-purpose I/O port Reset clears the SPE bit. MSTR -- Master Mode Select Bit When set, the MSTR bit configures the serial I/O port for master mode. A transfer is initiated by writing to the SDR. Also, the SCK pin becomes an output providing a synchronous data clock dependent upon the oscillator frequency. When the device is in slave mode, the SDO and SDI pins do not change function. These pins behave exactly the same in both the master and slave modes. The MSTR bit is readable and writable at any time regardless of the state of the SPE bit. Clearing the MSTR bit will abort any transfers that may have been in progress. Reset clears the MSTR bit, placing the SIOP subsystem in slave mode.
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9.4.2 SIOP Status Register This register is located at address $000B and contains two bits. Figure 9-4 shows the position of each bit in the register and indicates the value of each bit after reset.
Address: $000B Bit 7 Read: SPIF 6 DCOL 5 0 4 0 3 0 2 0 1 0 Bit 0 0
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Write: Reset: 0 0 0 0 0 0 0 0
= Unimplemented
Figure 9-4. SIOP Status Register (SSR) SPIF -- Serial Port Interface Flag SPIF is a read-only status bit that is set on the last rising edge of SCK and indicates that a data transfer has been completed. It has no effect on any future data transfers and can be ignored. The SPIF bit is cleared by reading the SSR followed by a read or write of the SDR. If the SPIF is cleared before the last rising edge of SCK it will be set again on the last rising edge of SCK. Reset clears the SPIF bit. DCOL -- Data Collision Bit DCOL is a read-only status bit, which indicates that an illegal access of the SDR has occurred. The DCOL bit will be set when reading or writing the SDR after the first falling edge of SCK and before SPIF is set. Reading or writing the SDR during this time will result in invalid data being transmitted or received. The DCOL bit is cleared by reading the SSR (when the SPIF bit is set) followed by a read or write of the SDR. If the last part of the clearing sequence is done after another transfer has started, the DCOL bit will be set again. Reset clears the DCOL bit.
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Serial Input/Output Ports (SIOP) SIOP Registers
9.4.3 SIOP Data Register This register is located at address $000C and serves as both the transmit and receive data register. Writing to this register will initiate a message transmission if the SIOP is in master mode. The SIOP subsystem is not double buffered and any write to this register will destroy the previous contents. The SDR can be read at any time; however, if a transfer is in progress, the results may be ambiguous and the DCOL bit will be set. Writing to the SDR while a transfer is in progress can cause invalid data to be transmitted and/or received. Figure 9-5 shows the position of each bit in the register. This register is not affected by reset.
Address: $000C Bit 7 Read: SD7 Write: Reset: Unaffected by reset SD6 SD5 SD4 SD3 SD2 SD1 SD0 6 5 4 3 2 1 Bit 0
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Figure 9-5. SIOP Data Register (SDR)
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MC68HC05P18A
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Technical Data -- MC68HC05P18A
Section 10. EEPROM
10.1 Contents
10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 EEPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . .86 Programming/Erasing Procedures . . . . . . . . . . . . . . . . . . . . . .88
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10.3 10.4
10.2 Introduction
The electrically erasable programmable read-only memory (EEPROM) is located at address $0140 and consists of 128 bytes. Programming the EEPROM can be done by the user on a single byte basis by manipulating the programming register, located at address $001C.
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Freescale Semiconductor, Inc. EEPROM REQUIRED 10.3 EEPROM Programming Register
The contents and use of the programming register (EEPROG) are discussed here.
Address: $001C Bit 7 Read: Write: 0 CPEN 6 5 0 ER1 0 0 ER0 0 LATCH 0 EERC 0 EEPGM 0 4 3 2 1 Bit 0
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Reset:
0
0
= Unimplemented
Figure 10-1. EEPROM Programming Register (EEPROG) CPEN -- Charge Pump Enable Bit When set, CPEN enables the charge pump that produces the internal EEPROM programming voltage. This bit should be set concurrently with the LATCH bit. The programming voltage will not be available until EEPGM is set. The charge pump should be disabled when not in use. CPEN is readable and writable and is cleared by reset. ER1 and ER0 -- Erase Select Bits ER1 and ER0 form a 2-bit field that is used to select one of three erase modes: byte, block, or bulk. Table 10-1 shows the modes selected for each bit configuration. These bits are readable and writable and are cleared by reset. Table 10-1. Erase Mode Select
ER1 0 0 1 1 ER0 0 1 0 1 Mode Program, no erase Byte erase Block erase Bulk erase
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EEPROM EEPROM Programming Register
In byte erase mode, only the selected byte is erased. In block mode, a 32-byte block of EEPROM is erased. The EEPROM memory space is divided into four 32-byte blocks ($140-$15F, $160-$17F, $180-$19F, $1A0-$1BF), and doing a block erase to any address within a block erases the entire block. In bulk erase mode, the entire 128-byte EEPROM section is erased. LATCH -- EEPROM Programming Latch Bit When set, LATCH configures the EEPROM address and data bus for programming. When LATCH is set, writes to the EEPROM array cause the data bus and the address bus to be latched. This bit is readable and writable, but reads from the array are inhibited if the LATCH bit is set and a write to the EEPROM space has taken place. When clear, address and data buses are configured for normal operation. Reset clears this bit. EERC -- EEPROM RC Oscillator Control Bit When this bit is set, the EEPROM section uses the internal RC oscillator instead of the CPU clock. The RC oscillator is shared with the analog-to-digital (A/D) converter, so this bit should be set by the user when the internal bus frequency is below 1.5 MHz to guarantee reliable operation of the EEPROM or A/D converter. After setting the EERC bit, delay a time, tRCON, to allow the RC oscillator to stabilize. This bit is readable and writable. The EERC bit is cleared by reset. The RC oscillator is disabled while the MCU is in stop mode. EEPGM -- EEPROM Programming Power Enable Bit EEPGM must be written to enable (or disable) the EEPGM function. When set, EEPGM turns on the charge pump and enables the programming (or erasing) power to the EEPROM array. When clear, this power is switched off. This enables pulsing of the programming voltage to be controlled internally. This bit can be read at any time, but can only be written to if LATCH = 1. If LATCH is not set, EEPGM cannot be set. LATCH and EEPGM cannot both be set with one write if LATCH is cleared. EEPGM is cleared automatically when LATCH is cleared. Reset clears this bit.
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Freescale Semiconductor, Inc. EEPROM REQUIRED 10.4 Programming/Erasing Procedures
To program a byte of EEPROM: 1. Set EELAT = CPEN = 1. 2. Set ER1 = ER0 = 0. 3. Write data to the desired address. 4. Set EEPGM for a time, tEEPGM. Any bit should be erased before it is programmed. However, if write/erase cycling is a concern, a procedure can be followed to minimize the cycling of each bit in each EEPROM byte. Here is the procedure: * * If PB * EB = 0 -- Program the new data over the existing data without erasing it first. If PB * EB 0 -- Erase byte before programming.
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Where: PB = Byte data to be programmed EB = Existing EEPROM byte data To erase a byte of EEPROM: 1. Set LATCH = 1, CPEN = 1, ER1 = 0, and ER0 = 1. 2. Write to the address to be erased. 3. Set EEPGM for a time, tEBYT. To erase a block of EEPROM: 1. Set LATCH = 1, CPEN = 1, ER1 = 1, and ER0 = 0. 2. Write to any address in the block. 3. Set EEPGM for a time, tEBLOCK.
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EEPROM Programming/Erasing Procedures
For a bulk erase: 1. Set LATCH = 1, CPEN = 1, ER1 = 1, and ER0 = 1. 2. Write to any address in the array. 3. Set EEPGM for a time, tEBULK. To terminate the programming or erase sequence, clear EEPGM, delay for a time, tFPV, to allow the programming voltage to fall, and then clear LATCH and CPEN to free up the buses. Following each erase or programming sequence, clear all programming control bits.
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Section 11. Analog-to-Digital (A/D) Converter
11.1 Contents
11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
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11.3 Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.3.1 Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.3.2 Reference Supply Voltage (VREFH) . . . . . . . . . . . . . . . . . . .92 11.3.3 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.4 Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
11.5 Digital Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.5.1 Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.5.2 Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . .93 11.5.3 Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .94 11.6 11.7 11.8 11.9 A/D Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . .94
A/D Subsystem Operation during Wait Mode and Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 A/D Subsystem Operation during Stop Mode. . . . . . . . . . . . . .96
11.2 Introduction
The MC68HC05P18A includes a 4-channel, multiplexed input, 8-bit, successive approximation analog-to-digital (A/D) converter. The A/D subsystem shares its inputs with port C pins PC3-PC7.
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A/D Conversion Data Register . . . . . . . . . . . . . . . . . . . . . . . . .96
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The following paragraphs describe the operation and performance of analog modules within the analog subsystem.
11.3.1 Ratiometric Conversion The A/D converter is ratiometric, with pin VREFH supplying the high reference voltage. Applying an input voltage equal to VREFH produces a conversion result of $FF (full scale). Applying an input voltage equal to VSS produces a conversion result of $00. An input voltage greater than VREFH converts to $FF with no overflow indication. For ratiometric conversions, VREFH should be at the same potential as the supply voltage being used by the analog signal being measured and be referenced to VSS.
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11.3.2 Reference Supply Voltage (VREFH) The reference supply for the A/D converter shares pin PC7 with port C. The low reference is tied to the VSS pin internally. VREFH can be any voltage between VSS and VDD; however, the accuracy of conversions is tested and guaranteed only for VREFH = VDD.
NON-DISCLOSURE
11.3.3 Accuracy and Precision The 8-bit conversion result is accurate to within 1 1/2 LSB (least significant bit), including quantization; however, the accuracy of conversions is tested and guaranteed only with external oscillator operation.
11.4 Conversion Process
The A/D reference inputs are applied to a precision digital-to-analog (D/A) converter. Control logic drives the D/A and the analog output is successively compared to the selected analog input that was sampled at
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Analog-to-Digital (A/D) Converter Digital Section
the beginning of the conversion cycle. The conversion process is monotonic and has no missing codes.
11.5 Digital Section
The following paragraphs describe the operation and performance of digital modules within the analog subsystem.
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Each input conversion requires 32 PH2 clock cycles, which must be at a frequency equal to or greater than 1 MHz.
11.5.2 Internal versus External Oscillator If the MCU PH2 clock frequency is less than 1 MHz (2 MHz external oscillator), the internal RC oscillator (approximately 1.5 MHz) must be used for the A/D converter clock. The internal RC clock is selected by setting the EERC bit in the EEPROM program register (EEPROG).
NOTE:
When the internal RC oscillator is being used, these limitations apply: 1. Since the internal RC oscillator is running asynchronously with respect to the PH2 clock, the conversion complete (CC) bit in the A/D status and control register (ADSC) must be used to determine when a conversion sequence has been completed. 2. Electrical noise slightly degrades the accuracy of the A/D converter. The A/D converter is synchronized to read voltages during the quiet period of the clock driving it. Since the internal and external clocks are not synchronized, the A/D converter occasionally measures an input when the external clock is making a transition. 3. If the PH2 clock is 1 MHz or greater (for example, external oscillator 2 MHz or greater), the internal RC oscillator should be turned off and the external oscillator used as the conversion clock.
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The RC oscillator is shared with the EEPROM module. The RC oscillator is disabled while the MCU is in stop mode.
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11.5.1 Conversion Times
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11.5.3 Multi-Channel Operation An input multiplexer allows the A/D converter to select from one of four external analog signals. Port C pins PC3-PC6 are shared with the inputs to the multiplexer.
11.6 A/D Status and Control Register
The A/D status and control register (ADSCR) reports the completion of A/D conversion and provides control over: * * * Oscillator selection Analog subsystem power Input channel selection
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See Figure 11-1.
Address: $001E Bit 7 Read: Write: Reset: 0 CC 6 R 0 5 ADON 0 4 0 3 0 2 CH2 0 1 CH1 0 Bit 0 CH0 0
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0 R
0 = Reserved
= Unimplemented
Figure 11-1. A/D Status and Control Register (ADSCR) CC -- Conversion Complete Bit This read-only status bit is set when a conversion sequence has completed and data is ready to be read from the ADC register. CC is cleared when a channel is selected for conversion, when data is read from the ADC register, or when the A/D subsystem is turned off. Once a conversion is started, conversions of the selected channel continue every 32 PH2 clock cycles until the ADSC register is written to again. During continuous conversion operation, the ADC register is updated with new data, and the CC bit is set, every 32 PH2 clock cycles. Also, data from the previous conversion is overwritten regardless of the state of the CC bit.
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Analog-to-Digital (A/D) Converter A/D Status and Control Register
R -- Reserved Bit This bit is not currently used. It can be read or written, but does not control anything. ADON -- A/D Subsystem On Bit When the A/D subsystem is turned on (ADON = 1), it requires a time tADON to stabilize before accurate conversion results can be attained. CH2-CH0 -- Channel Select Bits
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Table 11-1. A/D Multiplexer Input Channel Assignments
Channel 0 1 2 3 4 5 6 7 Signal AD0 port C bit 6 AD1 port C bit 5
AD3 port C bit 3 VREFH port C bit 7 (VREFH + VSS)/2 VSS Reserved
If the ADON bit is set, and an input from channels 0-4 is selected, the corresponding port C pin's DDR bit is cleared (making that port C pin an input). If the port C data register is read while the A/D is on, and one of the shared input channels is selected using bit CH0-CH2, the corresponding port C pin reads as a logic 0. The remaining port C pins read normally. To digitally read a port C pin, the A/D subsystem must be disabled (ADON = 0) or input channel 5-7 must be selected.
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AD2 port C bit 4
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CH2, CH1, and CH0 form a 3-bit field that is used to select an input to the A/D converter. Channels 0-3 correspond to port C input pins PC6-PC3. Channels 4-6 are used for reference measurements. In user mode, channel 7 is reserved. If a conversion is attempted with channel 7 selected, the result is $00. Table 11-1 lists the inputs selected by bits CH0-CH3.
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This register contains the output of the A/D converter. See Figure 11-2.
Address: $001D Bit 7 Read: Write: Reset: = Unimplemented Unaffected by reset R = Reserved AD7 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 Bit 0 AD0
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Figure 11-2. A/D Conversion Value Data Register (ADC)
11.8 A/D Subsystem Operation during Wait Mode and Halt Mode
The A/D subsystem continues normal operation during wait mode and halt mode. To decrease power consumption during wait or halt, the ADON bit in the ADSC register and the EERC bit in the EEPROG register should be cleared if the A/D subsystem is not being used.
NON-DISCLOSURE
11.9 A/D Subsystem Operation during Stop Mode
When stop mode is enabled, execution of the STOP instruction terminates all A/D subsystem functions. Any pending conversion is aborted. When the oscillator resumes operation upon leaving the stop mode, a finite amount of time passes before the A/D subsystem stabilizes sufficiently to provide conversions at its rated accuracy. The delays built into the MC68HC05P18A when coming out of stop mode are sufficient for this purpose. No explicit delays need to be added to the application software.
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Section 12. Instruction Set
12.1 Contents
12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
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12.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 12.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 12.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 12.3.7 Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 12.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 12.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 12.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .102 12.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .103 12.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .104 12.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .106 12.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 12.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
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The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator.
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12.3 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: * * * * * * * * Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative
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12.3.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.
12.3.2 Immediate
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Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte.
12.3.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address.
12.3.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction.
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12.3.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000-$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location.
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12.3.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000-$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.
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12.3.7 Indexed,16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing.
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Instruction Set Instruction Types
12.3.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two's complement byte that gives a branching range of -128 to +127 bytes from the address of the next location after the branch instruction.
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12.4 Instruction Types
The MCU instructions fall into five categories: * * * * * Register/memory instructions Read-modify-write instructions Jump/branch instructions Bit manipulation instructions Control instructions
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When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch.
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12.4.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 12-1. Register/Memory Instructions
Instruction Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB
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Add memory byte and carry bit to accumulator Add memory byte to accumulator AND memory byte with accumulator Bit test accumulator Compare accumulator Compare index register with memory byte Exclusive OR accumulator with memory byte Load accumulator with memory byte Load Index register with memory byte Multiply OR accumulator with memory byte Subtract memory byte and carry bit from accumulator Store accumulator in memory Store index register in memory Subtract memory byte from accumulator
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Instruction Set Instruction Types
12.4.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register.
NOTE:
Do not use read-modify-write operations on write-only registers. Table 12-2. Read-Modify-Write Instructions
Instruction Mnemonic ASL ASR BCLR(1) BSET(1) CLR COM DEC INC LSL
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Arithmetic shift left (same as LSL) Arithmetic shift right Bit clear Bit set Clear register Complement (one's complement) Decrement Increment Logical shift left (same as ASL) Logical shift right Negate (two's complement) Rotate left through carry bit Rotate right through carry bit Test for negative or zero
NEG ROL ROR TST(2)
1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value.
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LSR
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12.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from -128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register.
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Instruction Set Instruction Types
Table 12-3. Jump and Branch Instructions
Instruction Branch if carry bit clear Branch if carry bit set Branch if equal Branch if half-carry bit clear Branch if half-carry bit set Branch if higher Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL
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Branch if higher or same Branch if IRQ pin high Branch if IRQ pin low Branch if lower Branch if lower or same Branch if interrupt mask clear Branch if minus Branch if interrupt mask set Branch if not equal Branch if plus Branch always Branch if bit clear Branch never Branch if bit set Branch to subroutine Unconditional jump Jump to subroutine
BRCLR BRN BRSET BSR JMP JSR
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BRA
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12.4.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 12-4. Bit Manipulation Instructions
Instruction Mnemonic BCLR BRCLR BRSET BSET
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Bit clear Branch if bit clear Branch if bit set Bit set
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Instruction Set Instruction Types
12.4.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. Table 12-5. Control Instructions
Instruction Clear carry bit Clear interrupt mask Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA
WAIT
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No operation Reset stack pointer Return from interrupt Return from subroutine Set carry bit Set interrupt mask Stop oscillator and enable IRQ pin Software interrupt Transfer accumulator to index register Transfer index register to accumulator Stop CPU clock and enable interrupts
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Table 12-6. Instruction Set Summary (Sheet 1 of 6)
Address Mode Opcode Source Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel
Operation
Description
H I NZC
Add with Carry
A (A) + (M) + (C)
--
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AGREEMENT
IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL
A9 ii 2 B9 dd 3 C9 hh ll 4 D9 ee ff 5 E9 ff 4 F9 3 AB ii 2 BB dd 3 CB hh ll 4 DB ee ff 5 EB ff 4 FB 3 A4 ii 2 B4 dd 3 C4 hh ll 4 D4 ee ff 5 E4 ff 4 F4 3 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 28 29 22 24 dd 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 3 3 3 3
Add without Carry
A (A) + (M)
--
Logical AND
A (A) (M)
----
--
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
----
NON-DISCLOSURE
ff dd
Arithmetic Shift Right
b7 b0
C
----
ff rr dd dd dd dd dd dd dd dd rr rr rr rr rr rr
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? C = 0
----------
BCLR n opr
Clear Bit n
Mn 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- ---------- ---------- ---------- REL REL REL REL REL REL
BCS rel BEQ rel BHCC rel BHCS rel BHI rel BHS rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? Z = 1 PC (PC) + 2 + rel ? H = 0 PC (PC) + 2 + rel ? H = 1 PC (PC) + 2 + rel ? C = 0
PC (PC) + 2 + rel ? C Z = 0 -- -- -- -- -- ----------
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Cycles
Effect on CCR
Operand
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Instruction Set Instruction Set Summary
Table 12-6. Instruction Set Summary (Sheet 2 of 6)
Address Mode Opcode Source Form
BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
Operation
Branch if IRQ Pin High Branch if IRQ Pin Low
Description
PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0
H I NZC
---------- ----------
REL REL IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL
2F 2E
rr rr
Bit Test Accumulator with Memory Byte
(A) (M)
----
--
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A5 ii 2 B5 dd 3 C5 hh ll 4 D5 ee ff 5 E5 ff 4 F5 3 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
Cycles
3 3 6 2 2
Effect on CCR
Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? I = 0 PC (PC) + 2 + rel ? N = 1 PC (PC) + 2 + rel ? I = 1 PC (PC) + 2 + rel ? Z = 0 PC (PC) + 2 + rel ? N = 0 PC (PC) + 2 + rel ? 1 = 1
----------
PC (PC) + 2 + rel ? C Z = 1 -- -- -- -- -- ---------- ---------- ---------- ---------- ---------- ----------
BRCLR n opr rel Branch if Bit n Clear
PC (PC) + 2 + rel ? Mn = 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) -------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- REL
BRN rel
Branch Never
PC (PC) + 2 + rel ? 1 = 0
BRSET n opr rel Branch if Bit n Set
PC (PC) + 2 + rel ? Mn = 1
DIR (b0) DIR (b1) DIR (b2) DIR (b3) -------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BSET n opr
Set Bit n
Mn 1
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel C0 I0
----------
REL
AD
rr
CLC CLI
Clear Carry Bit Clear Interrupt Mask
-------- 0 -- 0 ------
INH INH
98 9A
MC68HC05P18A Instruction Set For More Information On This Product, Go to: www.freescale.com
Technical Data
NON-DISCLOSURE
AGREEMENT
REQUIRED
Operand
Freescale Semiconductor, Inc. Instruction Set REQUIRED
Table 12-6. Instruction Set Summary (Sheet 3 of 6)
Address Mode Opcode Source Form
CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X
Operation
Description
M $00 A $00 X $00 M $00 M $00
H I NZC
Clear Byte
---- 0 1 --
DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR EXT IX2 IX1 IX
3F 4F 5F 6F 7F
dd
ff
Freescale Semiconductor, Inc...
AGREEMENT
Compare Accumulator with Memory Byte
(A) - (M)
----
A1 ii 2 B1 dd 3 C1 hh ll 4 D1 ee ff 5 E1 ff 4 F1 3 33 43 53 63 73 dd 5 3 3 6 5
Complement Byte (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (A) X (X) = $FF - (X) M (M) = $FF - (M) M (M) = $FF - (M)
----
1
ff
Compare Index Register with Memory Byte
(X) - (M)
----
A3 ii 2 B3 dd 3 C3 hh ll 4 D3 ee ff 5 E3 ff 4 F3 3 3A 4A 5A 6A 7A dd 5 3 3 6 5
NON-DISCLOSURE
Decrement Byte
M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1
----
--
ff
EXCLUSIVE OR Accumulator with Memory Byte
A (A) (M)
----
--
A8 ii 2 B8 dd 3 C8 hh ll 4 D8 ee ff 5 E8 ff 4 F8 3 3C 4C 5C 6C 7C dd 5 3 3 6 5
Increment Byte
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1
----
--
ff
Unconditional Jump
PC Jump Address
----------
BC dd 2 CC hh ll 3 DC ee ff 4 EC ff 3 FC 2
Technical Data Instruction Set For More Information On This Product, Go to: www.freescale.com
MC68HC05P18A
Cycles
5 3 3 6 5
Effect on CCR
Operand
Freescale Semiconductor, Inc.
Instruction Set Instruction Set Summary
Table 12-6. Instruction Set Summary (Sheet 4 of 6)
Address Mode Opcode Source Form
JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X
Operation
Description
H I NZC
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Effective Address
Jump to Subroutine
----------
DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX
BD dd 5 CD hh ll 6 DD ee ff 7 ED ff 6 FD 5 A6 ii 2 B6 dd 3 C6 hh ll 4 D6 ee ff 5 E6 ff 4 F6 3 AE ii 2 BE dd 3 CE hh ll 4 DE ee ff 5 EE ff 4 FE 3 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D dd dd 5 3 3 6 5 5 3 3 6 5 1 1 5 3 3 6 5 2
Freescale Semiconductor, Inc...
Load Index Register with Memory Byte
X (M)
----
--
Logical Shift Left (Same as ASL)
C b7 b0
0
----
ff dd
Logical Shift Right
0 b7 b0
C
---- 0
Unsigned Multiply
X : A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M)
0 ------ 0
Negate Byte (Two's Complement)
----
ff
No Operation
----------
Logical OR Accumulator with Memory
A (A) (M)
----
--
AA ii 2 BA dd 3 CA hh ll 4 DA ee ff 5 EA ff 4 FA 3 39 49 59 69 79 dd 5 3 3 6 5
Rotate Byte Left through Carry Bit
C b7 b0
----
ff
MC68HC05P18A Instruction Set For More Information On This Product, Go to: www.freescale.com
Technical Data
NON-DISCLOSURE
ff
AGREEMENT
Load Accumulator with Memory Byte
A (M)
----
--
Cycles
Effect on CCR
REQUIRED
Operand
Freescale Semiconductor, Inc. Instruction Set REQUIRED
Table 12-6. Instruction Set Summary (Sheet 5 of 6)
Address Mode Opcode Source Form
ROR opr RORA RORX ROR opr,X ROR ,X RSP
Operation
Description
H I NZC
Rotate Byte Right through Carry Bit
b7 b0
C
----
DIR INH INH IX1 IX INH
36 46 56 66 76 9C
dd
ff
Reset Stack Pointer
SP $00FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL)
----------
Freescale Semiconductor, Inc...
AGREEMENT
RTI
Return from Interrupt

INH
80
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X
Return from Subroutine
----------
INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX
81
Subtract Memory Byte and Carry Bit from Accumulator
A (A) - (M) - (C)
----
A2 ii 2 B2 dd 3 C2 hh ll 4 D2 ee ff 5 E2 ff 4 F2 3 99 9B 2 2
Set Carry Bit Set Interrupt Mask
C1 I1
-------- 1 -- 1 ------
NON-DISCLOSURE
Store Accumulator in Memory
M (A)
----
--
B7 dd 4 C7 hh ll 5 D7 ee ff 6 E7 ff 5 F7 4 8E 2
Stop Oscillator and Enable IRQ Pin
-- 0 ------
Store Index Register In Memory
M (X)
----
--
BF dd 4 CF hh ll 5 DF ee ff 6 EF ff 5 FF 4 A0 ii 2 B0 dd 3 C0 hh ll 4 D0 ee ff 5 E0 ff 4 F0 3
Subtract Memory Byte from Accumulator
A (A) - (M)
----
SWI
Software Interrupt
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) -- 1 ------ SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte X (A) ----------
INH
83
TAX
Transfer Accumulator to Index Register
INH
97
Technical Data Instruction Set For More Information On This Product, Go to: www.freescale.com
MC68HC05P18A
Cycles
5 3 3 6 5 2 9 6 1 0 2
Effect on CCR
Operand
Freescale Semiconductor, Inc.
Instruction Set Instruction Set Summary
Table 12-6. Instruction Set Summary (Sheet 6 of 6)
Address Mode Opcode Source Form
TST opr TSTA TSTX TST opr,X TST ,X TXA WAIT
Operation
Description
H I NZC
Test Memory Byte for Negative or Zero
(M) - $00
----
--
DIR INH INH IX1 IX INH INH
3D 4D 5D 6D 7D 9F 8F
dd
ff
Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit
A (X)
---------- -- 0 ------ opr PC PCH PCL REL rel rr SP X Z # () -( ) ? : --
Freescale Semiconductor, Inc...
Cycles
4 3 3 5 4 2 2
Effect on CCR
MC68HC05P18A Instruction Set For More Information On This Product, Go to: www.freescale.com
Technical Data
NON-DISCLOSURE
A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n
Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Loaded with If Concatenated with Set or cleared Not affected
AGREEMENT
REQUIRED
Operand
NON-DISCLOSURE REQUIRED
Freescale Semiconductor, IN T A G R E E M E nc...
Table 12-7. Opcode Map
Branch Register/Memory IMM A B C D E F
3 SUB IX 3 CMP IX 3 SBC IX 3 CPX IX 3 AND IX 3 BIT IX 3 LDA IX 4 STA 2 IX 3 EOR IX 3 ADC 1 1 1 1 1 IX 3 ORA IX 3 ADD IX 2 JMP 2 IX 5 JSR IX 3 LDX IX 4 STX 2 MSB LSB IX
Bit Manipulation Control IX INH INH IX1 9 IX2 8 EXT 7 DIR IX REL DIR INH INH 5 6 4 3 2 IX1
Read-Modify-Write
Instruction Set
Technical Data
MSB LSB
DIR
DIR
MSB LSB 2 2 2 10 SWI INH 2 2 2 2 1 1
0
1
0
0 1 2 3 4 5 6 7 8 9 A B C D E F
1
9 RTI INH 6 RTS INH
2
3
4
5
6
2 SUB IMM 2 2 CMP IMM 2 2 SBC IMM 2 2 CPX IMM 2 2 AND IMM 2 2 BIT IMM 2 2 LDA IMM 2
7
8
9
A
Freescale Semiconductor, Inc.
Instruction Set For More Information On This Product, Go to: www.freescale.com
2 EOR IMM 2 2 ADC IMM 2 2 ORA IMM 2 2 ADD IMM 2 2 TAX INH 2 CLC INH 2 2 SEC INH 2 2 CLI INH 2 2 SEI INH 2 2 RSP INH 2 NOP INH 2 6 BSR REL 2 2 LDX 2 IMM 2 2 STOP INH 2 2 TXA WAIT INH 1 INH
B
C
D
E
F
5 5 3 5 3 3 6 5 BRSET0 BRA BSET0 NEG NEGA NEGX NEG NEG 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 BRCLR0 BRN BCLR0 3 1 DIR 2 DIR 2 REL 5 11 5 3 BRSET1 MUL BHI BSET1 3 1 DIR 2 INH DIR 2 REL 5 5 3 5 3 3 6 5 BRCLR1 BLS BCLR1 COM COMA COMX COM COM 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 5 3 3 6 5 BRSET2 BCC BSET2 LSR LSRA LSRX LSR LSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR2 BCLR2 BCS/BLO 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET3 BNE BSET3 ROR RORA RORX ROR ROR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR3 BEQ BCLR3 ASR ASRA ASRX ASR ASR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET4 BHCC BSET4 ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR4 BHCS BCLR4 ROL ROLA ROLX ROL ROL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET5 BPL BSET5 DEC DECA DECX DEC DEC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR5 BMI BCLR5 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET6 BMC BSET6 INC INCA INCX INC INC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 4 3 3 5 4 BRCLR6 BMS BCLR6 TST TSTA TSTX TST TST 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRSET7 BIL BSET7 3 1 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRCLR7 BIH BCLR7 CLR CLRA CLRX CLR CLR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 3 SUB DIR 3 3 CMP DIR 3 3 SBC DIR 3 3 CPX DIR 3 3 AND DIR 3 3 BIT DIR 3 3 LDA DIR 3 4 STA DIR 3 3 EOR DIR 3 3 ADC DIR 3 3 ORA DIR 3 3 ADD DIR 3 2 JMP DIR 3 5 JSR DIR 3 3 LDX DIR 3 4 STX DIR 3 4 SUB EXT 3 4 CMP EXT 3 4 SBC EXT 3 4 CPX EXT 3 4 AND EXT 3 4 BIT EXT 3 4 LDA EXT 3 5 STA EXT 3 4 EOR EXT 3 4 ADC EXT 3 4 ORA EXT 3 4 ADD EXT 3 3 JMP EXT 3 6 JSR EXT 3 4 LDX EXT 3 5 STX EXT 3 5 SUB IX2 2 5 CMP IX2 2 5 SBC IX2 2 5 CPX IX2 2 5 AND IX2 2 5 BIT IX2 2 5 LDA IX2 2 6 STA IX2 2 5 EOR IX2 2 5 ADC IX2 2 5 ORA IX2 2 5 ADD IX2 2 4 JMP IX2 2 7 JSR IX2 2 5 LDX IX2 2 6 STX IX2 2
4 SUB IX1 1 4 CMP IX1 1 4 SBC IX1 1 4 CPX IX1 1 4 AND IX1 1 4 BIT IX1 1 4 LDA IX1 1 5 STA IX1 1 4 EOR IX1 1 4 ADC IX1 1 4 ORA IX1 1 4 ADD IX1 1 3 JMP IX1 1 6 JSR IX1 1 4 LDX IX1 1 5 STX IX1 1
0
LSB of Opcode in Hexadecimal
MSB of Opcode in Hexadecimal
MC68HC05P18A
INH = Inherent IMM = Immediate DIR = Direct EXT = Extended
REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset
0
5 Number of Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes/Addressing Mode
Freescale Semiconductor, Inc.
Technical Data -- MC68HC05P18A
Section 13. Electrical Specifications
13.1 Contents
13.2 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .116 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .118 Active Reset Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .119 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . .120 SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Freescale Semiconductor, Inc...
13.3 13.4 13.5 13.6 13.7 13.8 13.9
13.10 PD5 Clock Out Timing (PD5 Clock Out Option Enabled) . . . .122
MC68HC05P18A Electrical Specifications For More Information On This Product, Go to: www.freescale.com
Technical Data
NON-DISCLOSURE
13.11 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Electrical Specifications REQUIRED 13.2 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table here. Keep VIn and VOut within the range VSS (VIn or VOut) VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD.
Rating Supply voltage Input voltage Current drain per pin excluding VDD and VSS Storage temperature range Symbol VDD VIn I TSTG Value -0.3 to +7.0 VSS -0.3 to VDD +0.3 25 -65 to +150 Unit V V mA C
Freescale Semiconductor, Inc...
AGREEMENT
NOTE:
This device is not guaranteed to operate properly at the maximum ratings. Refer to 13.6 DC Electrical Characteristics for guaranteed operating conditions.
NON-DISCLOSURE
13.3 Operating Temperature Range
Characteristic Operating temperature range Standard Extended Automotive Maximum junction temperature Symbol Value TL to TH 0 to +70 -40 to +85 -40 to +125 150 Unit C C
TA TJ
13.4 Thermal Characteristics
Characteristic Thermal resistance PDIP (28 pin) SOIC (28 pin) Symbol JA Value 60 60 Unit C/W
Technical Data Electrical Specifications For More Information On This Product, Go to: www.freescale.com
MC68HC05P18A
Freescale Semiconductor, Inc.
Electrical Specifications Power Considerations
13.5 Power Considerations
The average chip junction temperature, TJ, in C can be obtained from: TJ = TA + (PD x JA) (1)
Freescale Semiconductor, Inc...
For most applications, PI/O
PINT and can be neglected.
Ignoring PI/O, the relationship between PD and TJ is approximately: K PD = (2) TJ + 273C Solving equations (1) and (2) for K gives: = PD x (TA + 273C) + JA x (PD)2 (3)
MC68HC05P18A Electrical Specifications For More Information On This Product, Go to: www.freescale.com
Technical Data
NON-DISCLOSURE
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.
AGREEMENT
Where: TA = ambient temperature in C JA = package thermal resistance, junction to ambient in C/W PD = PINT + PI/O PINT = ICC x VCC = chip internal power dissipation PI/O = power dissipation on input and output pins (user-determined)
REQUIRED
Freescale Semiconductor, Inc. Electrical Specifications REQUIRED 13.6 DC Electrical Characteristics
Characteristic(1) Output voltage ILoad = 10.0 A Output high voltage (ILoad -0.8 mA) PA0-PA7, PB5-PB7, PC0-PC7, PD5/CKOUT (ILoad -5 mA) PC0, PC1 Output low voltage (ILoad = 1.6 mA) PA0-PA7, PB5-PB7, PC0-PC7, PD5/CKOUT (ILoad = 10 mA) PC0, PC1 Input high voltage PA0-PA7, PB5-PB7, PC0-PC7, PD5/CKOUT, TCAP/PD7, IRQ, RESET, OSC1 Input low voltage PA0-PA7, PB5-PB7, PC0-PC7, PD5, TCAP/PD7, IRQ, RESET, OSC1 Supply current(2) (3) (4) Low frequency (2-MHz bus) Run Wait (A2D on) Wait (A2D off) High frequency (4-MHz bus) Run Wait (A2D on) Wait (A2D off) Stop (-40C to +132C) LVR disabled LVR enabled I/O ports hi-z leakage current PA0-PA7, PB5-PB7, PC0-PC7, PD5/CKOUT, TCAP/PD7 I/O ports switch resistance (pullup enabled PA0-PA7) A/D ports hi-z leakage current PC3-PC7 Input current RESET, IRQ, OSC1 Capacitance Ports (as input or output) RESET, IRQ Symbol VOL VOH VOH Min -- VDD -0.1 VDD -0.8 Max 0.1 -- Unit V
--
V
AGREEMENT
Freescale Semiconductor, Inc...
VOL
--
0.4
V
VIH
0.7 x VDD
VDD
V
VIL
VSS
0.3 x VDD
V
-- -- -- IDD -- -- -- -- -- IIL RPTA IIn IIn -- 7 -- --
4 3.5 2.5 6 4.5 4.6 50 200 10 30 1 1
mA mA mA mA mA mA A A A k A A
NON-DISCLOSURE
COut CIn
-- --
12 8
pF Continued
Technical Data Electrical Specifications For More Information On This Product, Go to: www.freescale.com
MC68HC05P18A
Freescale Semiconductor, Inc.
Electrical Specifications Active Reset Characteristics
Characteristic(1) EEPROM program/erase time Byte Block Bulk Low-voltage reset inhibit
Symbol
Min -- -- -- 3.5
Max 5 30 100 4.3
Unit
--
ms
VLVRI
V
Freescale Semiconductor, Inc...
13.7 Active Reset Characteristics
Rise Time 0.5 s 1.0 s 2.5 s Fall Time 13 ns 20 ns 42 ns Pulse Width 2.4 s 2.7 s 3.7 s CLoad 59 pF 100 pF 250 pF Pullup 10 K 10 K 10 K
Note: VDD = 4.5 Vdc, VSS = 0 Vdc, TA = 125C
MC68HC05P18A Electrical Specifications For More Information On This Product, Go to: www.freescale.com
Technical Data
NON-DISCLOSURE
AGREEMENT
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = -40C to +125C, unless otherwise noted. All values shown reflect average measurements. 2. Run (Operating) IDD, wait IDD: Measured using external square wave clock source to OSC1 (fOSC = 4.2 MHz), all inputs 0.2 Vdc from rail; no DC loads, less than 50 pF on all outputs, CL = 20 pF on OSC2 3. Wait IDD: Only timer system active Wait IDD is affected linearly by the OSC2 capacitance. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD -0.2 Vdc Stop IDD measured with OSC1 = VSS 4. Run and wait IDD limit values are with no load on PD5 clockout, when PD5 is enabled. Run and wait IDD values are for both PD5 enabled and disabled and LVR enabled and disabled.
REQUIRED
Freescale Semiconductor, Inc. Electrical Specifications REQUIRED 13.8 A/D Converter Characteristics
Characteristic(1) Resolution Absolute accuracy VDD VREFH > 4.5 Conversion range VREFH Input leakage AD0, AD1, AD2, AD3 VREFH Conversion time(2) (Includes sampling time) Monotonicity Zero input reading External Internal Full-scale reading Sample time Input capacitance Analog input voltage 00 00 FE 12 -- VSS 01 03 FF 12 12 VREFH Min 8 -- VSS VSS Max 8 +1 1/2 VREFH VDD Unit Bits LSB Including quantization A/D accuracy may decrease proportionately as VREFH is reduced below 4.5 V. Comments
V
Freescale Semiconductor, Inc...
AGREEMENT
-- -- 32
+1 +1 32
A tAD (Note 2) Inherent (within total error) Hex Hex tAD (Note 3) pF V VIn = 0 V VIn = VREFH
NON-DISCLOSURE
1. VDD = 5.0 10% Vdc 10%, VSS = 0 Vdc, TA = -40C to +125C, unless otherwise noted 2. tAD = tCYC if clock source equals MCU
Technical Data Electrical Specifications For More Information On This Product, Go to: www.freescale.com
MC68HC05P18A
Freescale Semiconductor, Inc.
Electrical Specifications SIOP Timing
13.9 SIOP Timing
t1 SCK t2
t5
t6
SDI
Freescale Semiconductor, Inc...
BIT 0 t3 t4
BIT 1 ... 6
BIT 7
SDO
BIT 0
BIT 1 ... 6
BIT 7
Figure 13-1. SIOP Timing Diagram
No. Operating frequency(2) Master Slave 1 2 3 4 5 6 Cycle time Master Slave SCK low time SDO data valid time SDO hold time SDI setup time SDI hold time
Characteristic(1)
Symbol fOP(M) fOP(S) tCYC(m) tCYC(s) tCYC tV tHO tS tH
Min 1 dc 4.0 -- 238 -- 0 100 100
Max 1 1 4.0 4.0 -- 200 -- -- --
Unit fOP
tCYC ns ns ns ns ns
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = -40C to +125C, unless otherwise noted 2. fOP = fOSC / 2; tCYC = 1 / fOP
MC68HC05P18A Electrical Specifications For More Information On This Product, Go to: www.freescale.com
Technical Data
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Electrical Specifications REQUIRED 13.10 PD5 Clock Out Timing (PD5 Clock Out Option Enabled)
(1) (2) (3)
D5 CLK OUT
Freescale Semiconductor, Inc...
AGREEMENT
(4)
(5)
Figure 13-2. PD5 Clock Out Timing
Characteristic Cycle time Rise time Fall time Pulse width
Symbol
1
Min tCYC 3.5 7.5 tOH, tOL
Max
Unit ns
4 5 2, 3
12 27.5 --
ns ns ns
NON-DISCLOSURE
NOTE:
All timing is shown with respect to 20% and 70% VDD. Maximum rise and fall times assume 44% duty cycle. Minimum rise and fall times assume 55% duty cycle.
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MC68HC05P18A
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Electrical Specifications Control Timing
13.11 Control Timing
Characteristic(1) Frequency of operation Crystal option External clock source Internal operating frequency Crystal (fOSC /2) External clock (fOSC /2) Symbol fOSC Min -- dc -- dc 476 238 -- -- 1.5 125 Note 2 200 100 -- -- Max 4.2 4.2 2.1 2.1 -- 100 100 -- -- -- -- 100 5.0 Unit MHz
fOP
MHz
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Crystal oscillator startup time Stop recovery startup time (crystal oscillator) RESET pulse width Interrupt pulse width low (edge-triggered) Interrupt pulse period(2) OSC1 pulse width Low speed High speed A/D on current stabilization time RC oscillator stabilization time
tOXON tILCH tRL tILIH tILIL tOH, tOL tADON tRCON
ms ms tCYC ns tCYC ns s
1. VDD = 5.0 Vdc, VSS = 0 Vdc, TA = -40C to +125C, unless otherwise noted 2. The minimum period, tILIL, should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tCYC.
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Technical Data
NON-DISCLOSURE
s
AGREEMENT
Cycle time Low speed High speed
tCYC
ns
REQUIRED
NON-DISCLOSURE REQUIRED
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Electrical Specifications
Technical Data
t VDDR 4064 tCYC tCYC 3FFE 3FFF NEW PC NEW PC 3FFE 3FFE 3FFE 3FFE 3FFF NEW PC NEW PC NEW PCH NEW PCL tRL NOTE 3 OP CODE PCH PCL OP CODE
V
DD
V THRESHOLD (1-2 V TYPICAL) DD
OSC1(2)
INTERNAL PROCESSOR CLOCK(1)
INTERNAL ADDRESS BUS(1)
INTERNAL DATA BUS(1)
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RESET
Notes: 1. Internal timing signal and bus information are not available externally. 2. OSC1 line is not meant to represent frequency. It is used only to represent time. 3. The next rising edge of the PH2 clock following the rising edge of RESET initiates the reset sequence.
MC68HC05P18A
Figure 13-3. Power-On Reset and External Reset Timing Diagram
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Technical Data -- MC68HC05P18A
Section 14. Mechanical Specifications
14.1 Contents
14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 28-Pin Plastic Dual In-Line Package (Case #710) . . . . . . . . .126 28-Pin Small Outline Package (Case #751F) . . . . . . . . . . . . .126
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14.3 14.4
14.2 Introduction
This section provides package dimension drawings for the 28-pin plastic dual in-line (PDIP) or 28-pin small outline (SOIC) packages. To make sure that you have the latest case outline specifications, contact: * * Local Motorola Sales Office Motorola Mfax - Phone 602-244-6609 - EMAIL rmfax0@email.sps.mot.com * Worldwide Web (wwweb) at http://design-net.com
Follow Mfax or wwweb on-line instructions to retrieve the current mechanical specifications.
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Technical Data
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Mechanical Specifications REQUIRED 14.3 28-Pin Plastic Dual In-Line Package (Case #710)
28
15
B
1 14
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25mm (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 36.45 37.21 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0 15 0.51 1.02 INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040
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AGREEMENT
A N
C
L
H
G F D
K
SEATING PLANE
M
J
14.4 28-Pin Small Outline Package (Case #751F)
-A28 15 14X
NON-DISCLOSURE
-B1 14
P 0.010 (0.25)
M
B
M
28X D
0.010 (0.25)
M
T
A
S
B
S
M R X 45
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 17.80 18.05 7.60 7.40 2.65 2.35 0.49 0.35 0.90 0.41 1.27 BSC 0.32 0.23 0.29 0.13 8 0 10.05 10.55 0.75 0.25 INCHES MIN MAX 0.701 0.711 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 8 0 0.395 0.415 0.010 0.029
-T26X
C G K -TSEATING PLANE
F J
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MC68HC05P18A
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Technical Data -- MC68HC05P18A
Section 15. Ordering Information
15.1 Contents
15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
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15.3
15.2 Introduction
This section contains instructions for ordering the MC68HC05P18A.
15.3 MC Order Numbers
Table 15-1 shows the MC order numbers for the available package types. Table 15-1. MC Order Numbers
MC Order Number(1)
MC68HC05P18AP (standard) MC68HC05P18ADW (standard) MC68HC05P18ACP (extended) MC68HC05P18ACDW (extended) MC68HC05P18AMP (automotive) MC68HC05P18AMDW (automotive) 1. P = Plastic dual in-line package DW = Small outline (wide body) package
Operating Temperature Range
0C to 70C 0C to 70C -40C to +85C -40C to +85C -40C to +125C -40C to +125C
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Technical Data
NON-DISCLOSURE
AGREEMENT
REQUIRED
Freescale Semiconductor, Inc. Ordering Information REQUIRED NON-DISCLOSURE
Technical Data Ordering Information For More Information On This Product, Go to: www.freescale.com
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AGREEMENT
MC68HC05P18A
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For More Information On This Product, Go to: www.freescale.com
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