View ML9226GA_1280533.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

OKI Semiconductor ML9226
GENERAL DESCRIPTION
FEDL9226-01
Issue Date: Dec. 11, 2002
32-Bit Duplex/Triplex VFD Controller/Driver with Digital Dimming, ADC and Keyscan
The ML9226 is a full CMOS controller/driver for Duplex or Triplex vacuum fluorescent display tube. It conststs of 32-segment driver outputs and 3-grid pre-driver outputs, so that it can drive directly up to 96-segment VFD. ML9226 features a digital dimming function, a 8-ch ADC, a 5 x 5 keyscan circuit and an encoder type switch interface. ML9226 provides an interface with a microcontroller only by four signal lines: DATA I/O, CLOCK, CS.
FEATURES
* Supply voltage (VDISP) * Duplex/Triplex selectable * Applicable VFD tube * * * * * * * * * : 8 to 18.5V (Built-in 5V regulator for logic)
: 2 Grids x 32 Anodes VFD tube : 3 Grids x 32 Anodes VFD tube 32-segment driver outputs : IOH = -5 mA at VOH = VDISP - 0.8 V (SEG1 to 22) IOH = -10 mA at VOH = VDISP - 0.8 V (SEG23 to 32) IOL = 500 uA at VOL = 2.0 V (SEG1 to 32) 3-grid pre-driver outputs : IOH = - 5.0 mA at VOH = VDISP - 0.8V IOL = 10 mA at VOL = 2.0V Built-in digital dimming circuit (10-bit resolution) Built-in 8-ch A/D converter Built-in 5 x 5 keyscan circuit 3 interface circuits for an encoder type rotary switch Built-in oscillation circuit (external R and C) Built-in Power-On-Reset circuit Package: 80-pin plastic QFP (QFP80-P-1420-0.80-BK) ( ML9226GA)
1/26
FEDL9226-01
OKI Semiconductor
ML9226
BLOCK DIAGRAM
SEG1 SEG32 GRID1 GRID2 GRID3
D-GND VDISP VCC(5 V) VREG(5 V) L-GND 5V Regulator & Power On Reset 0H 7H
32 Segment Driver
3 Grid pre Driver
POR in1-32 Out1-32 96 to 32 Segment Control in1-32 in1-32
POR
Mode Select in1-3
1H 0H POR
Out1-32 Segment Latch 1 in1-32
2H 0H POR
Out1-32 Segment Latch 2 in1-32
3H 0H POR
Out1-32 Segment Latch 3 in1-32
CS CLOCK DATA I/O Control
Out1-3 3bit Shift Register POR
Out1-32 32bit Shift Register POR POR
4H POR
in1-10 Dimming Latch Out1-10
OSC0
OSC
10bit Digital Dimming
DIM OUT SYNC OUT1 DUP/TRI Timing Generator SYNC OUT2
8ch, 8bit A/D Converter
7H 5H 6H
5 x 5 Key Scan and Encoder Switch Interface
INT
CH1
CH8
COL1
COL5
ROW1
ROW5
A1 B1 A2 B2 A3 B3
2/26
FEDL9226-01
OKI Semiconductor
ML9226
PIN CONFIGURATION (TOP VIEW)
SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 67 SEG16 66 SEG15 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 29 30 31 32 33 34 35 36 37 38 39 25 26 27 28 40
80
79
78
77
NC
76
75
74
73
72
NC
71
70
69
VDISP SEG28 SEG29 SEG30 SEG31 SEG32 GRID1 GRID2 GRID3 ROW1 ROW2 ROW3 ROW4 ROW5 COL1 COL2 COL3 COL4 COL5 A3 B3 A2 B2
1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24
68
NC
VDISP SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Vreg
D-GND 10
L-GND DATA I/O
CLOCK
CS
NC
SYNC OUT2
SYNC OUT1
NC: No connection (OPEN) 80-pin Plastic QFP
DIM OUT
A1
B1
INT
DUP/TRI
VCC
NC
OSC0 NC
3/26
FEDL9226-01
OKI Semiconductor
ML9226
PIN DESCRIPTIONS
Pin 1, 64 10 33 30 41 50 to 63, 65 to 67, 69 to 71, 73, 74 75, 76, 78 to 80, 2 to 6 7, 8, 9 36 GRID1 to 3 CS O I SEG23 to 32 O Symbol VDISP D-GND L-GND VCC VREG Type -- -- -- O O Power supply pins. Pin1 and pin64 should be connected externally. D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the logic circuit. Pins 10 and 33 should be connected externally. 5 V output pin for internal logic portion and external logic circuit. Reference voltage (5 V) output pin for A/D converter. Segment (anode) signal output pins for a VFD tube. SEG1 to 22 O These pins can be directly connected to the VFD tube. External circuit is not required. IOH -5 mA Segment (anode) signal output pins for a VFD tube. These pins can be directly connected to the VFD tube. External circuit is not required. IOH -10 mA Inverted Grid signal output pins. For pre-driver, the external circuit is requiend. IOL 10 mA Chip Select input pin. Data input/output operation is valid when this pin is set at a High level. Serial clock input pin. 35 CLOCK I Data is input and/or output through the DATA I/O pin at the rising edge of the serial clock. Serial data input/output pin. 34 DATA I/O I/O Data is input to/comes out from the shift register at the rising edge of the serial clock. Interrupt signal output to microcontroller. When any key of key matrix is pressed or released, key scanning is started. After the completion of the one cycle, this pin goes to high level and keeps the high level until keyscan stop mode is selected. Duplex/Triplex operation select input pin. 29 42 to 49 21 to 26 DUP/TRI CH1 to 8 A1 to A3 B1 to B3 COL1 to 5 I I I Duplex (1/2 duty) operation is selected when this pin is set at a VCC level. Triplex (1/3 duty) operation is selected when this pin is set at a GND level. Analog voltage input pin for the 8-bit A/D converter. Input pin for the encoder type rotary switch. The phase of an An/Bn input is detected. Return inputs from the key matrix. 16 to 20 I These pins are active low. When key matrix are in the inactive sate, these pins are at high level through the internal pull-up resistors. All the inputs do not have the cahttering absorption function for the keyscans. Key switch scanning outputs. 11 to 15 ROW1 to 5 O Normally low level is output through these pin. When any switch of key matrix is depressed or released, key scanning is started and is continued until keyscan stop mode is selected. When keyscan stop mode is selected, all outputs of ROW1 to 5 go back to low level. Description
27
INT
O
4/26
FEDL9226-01
OKI Semiconductor
ML9226
Pin 40 38, 39
Symbol DIM OUT SYNC OUT 1, 2
Type O O Dimming pulse output.
Description Connect this pin to the slave side DIM IN pin. Synchronous signal input. Connect these pins to the SYNC IN1 and SYNC IN2 pins of a slave side. RC oscillator connecting pins. Oscillation frequency depends on display tubes to be used. For details refer to ELECTRICAL CHARACTERISTICS.
VCC OSC0
R Co
31
OSC0
I/O
28,32, 37,68, 72,77
NC
-
OPEN pins.
5/26
FEDL9226-01
OKI Semiconductor
ML9226
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDISP VIN PD TSTG IO1 Output Current IO2 IO3 IO4 Ta = 85C Condition -- -- QFP80-P-1420-0.80-BK -- SEG1 to 22 SEG23 to 32 GRID1 to 3 DIM OUT, SYNC OUT1, SYNC OUT2 Rating -0.3 to +20 -0.3 to +6.0 263 -55 to +150 -10.0 to +2.0 -20.0 to +2.0 -10.0 to +20.0 -2.0 to +2.0 Unit V V mW C mA mA mA mA
RECOMMENDED OPERATING CONDITIONS
Parameter Driver Supply Voltage High Level Input Voltage Low Level Input Voltage Clock Frequency Oscillation Frequency Frame Frequency Operating Temperature Symbol VDISP VIH VIL fC fOSC fFR TOP Condition -- All inputs except OSC0 All inputs except OSC0 -- R = 10 k 5%, Co = 27 pF 5% R = 10 k 5% Co = 27 pF 5% -- 1/3 Duty 1/2 Duty Min. 8.0 3.8 -- -- 2.2 179 268 -40 Typ. 13.0 -- -- -- 3.3 269 403 -- Max. 18.5 -- 0.8 2.0 4.4 358 538 +85 Unit V V V MHz MHz Hz Hz C
6/26
FEDL9226-01
OKI Semiconductor
ML9226
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta = -40 to +85C, VDISP = 8.0 to 18.5 V) Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Symbol VIH VIL IIH1 IIH2 IIL1 IIL2 VOH1 High Level Output Voltage VOH2 VOH3 VOH4 VOL1 Low Level Output Voltage VOL2 VOL3 VOL4 Supply Current Supply Voltage for Logic IDISP VL Applied pin *1) *1) *2) *3) *2) *3) SEG1 to 22 SEG23 to 32 GRID1 to 3 *4) SEG1 to 22 SEG23 to 32 GRID1 to 3 *5) VDISP VCC VDISP = 9.5 V VDISP = 9.5 V Condition -- -- VIH = 3.8 V VIH = 3.8 V VIL = 0.0 V VIL = 0.0 V IOH1 = -5 mA IOH2 = -10 mA IOH3 = -5 mA IOH4 = -200 A Output Open IOL1 = 500 A IOL2 = 500 A IOL3 = 10 mA IOL4 = 300 A R = 10 k 5%, Co = 27 pF 5% no load C = 0.01 F 10%, IO = 0 to -10 mA Min. 3.8 -- -5.0 -70 -5.0 -160 VDISP - 0.8 VDISP - 0.8 VDISP - 0.8 4.0 4.5 -- -- -- -- -- 4.5 Max. -- 0.8 +5.0 -5.0 +5.0 -10 Unit V V A A A A V V V V V V V V V mA V
-- -- -- -- --
2.0 2.0 2.0 0.4 10 5.5
*1) CS, CLOCK, DATA I/O DUP/TRI, A1 to A3, B1 to B3, COL1 to 5 *2) CS, CLOCK, DATA I/O DUP/TRI, A1 to A3, B1 to B3 *3) COL1 to 5 *4) DATA I/O, INT, DIM OUT, SYNC OUT1, SYNC OUT2 *5) DATA I/O, INT, DIM OUT, SYNC OUT1, SYNC OUT2, ROW1 to 5
7/26
FEDL9226-01
OKI Semiconductor
ML9226
AC Characteristics
(Ta = -40 to +85C, VDISP = 8.0 to 18.5 V) Parameter Clock Frequency Clock Pulse Width Data Setup Time Data Hold Time CS Off Time CS Setup Time (CS-Clock) CS Hold Time (Clock-CS) DATA Output Delay Time (Clock-DATA I/O) Output Slew Rate Time VDISP Rise Time VDISP Off Time CS Wait Time Symbol fC tCW tDS tDH tCSL tCSS tCSH tPD tR tF tPRZ tPOF tRSOFF CL= 100 pF Condition -- -- -- -- R = 10 k 5%, Co = 27 pF 5% -- -- -- tR = 20% to 80% tF = 80% to 20% Min. -- 200 200 200 20 200 200 -- -- -- -- 5.0 400 Max. 2.0 -- -- -- -- -- -- 1.0 2.0 2.0 100 -- -- Unit MHz ns ns ns s ns ns s s s s ms s
Mounted in a unit Mounted in a unit, VDISP = 0.0 V --
8/26
FEDL9226-01
OKI Semiconductor
ML9226
TIMING DIAGRAM
Data Input Timing
tCSS 1/fC tCW CLOCK tDS DATA I/O (INPUT) VALID VALID tDH -3.8 V VALID VALID -0.8 V tCW tCSH tCSL -3.8 V -0.8 V -3.8 V -0.8 V
CS
Data Output Timing
tCSS tCSH CLOCK tPD DATA I/O (OUTPUT) -3.8 V -0.8 V -3.8 V -0.8 V -3.8 V -0.8 V
CS
Reset Timing
tPRZ tRSOFF -3.8 V CS -0.0 V tPOF -0.8VDISP -0.0 V
VDISP
Driver Output Timing
tR tF -0.8VDISP -0.2VDISP
SEG1-32, GRID1-3
9/26
FEDL9226-01
OKI Semiconductor
ML9226
A/D Converter Characteristics
(Ta = -40 to +85C, VDISP = 8.0 to 18.5 V) Parameter Reference Voltage (VREG) Output Current Input Voltage Range Conversion Time/Channel Resolution Linearity error Differentiation linearity error Zero scale error Full-scale error Condition -- -- -- R = 10 k 5%, C2 = 27 pF 5% Min. 4.5 -- GND 256 -- -- -- -- -- Typ. 5.0 -- -- 310 -- -- -- -- -- Max. 5.5 -10 VREG 394 8 2.0 2.0 +2.0 -2.0 Unit V mA V s bit LSB LSB LSB LSB
Terminological definition Resolution Linearity error
The minimum input analog value which can be recognized. It can decompose into 28= 256,(VRH-VRL)/256,in 8 bits. The deviation between the ideal conversion characteristic as a 8-bit A/D converter and the actual conversion characteristic is said. (Therefore, a quantization error is not included.) The ideal conversion characteristic means the step which divided the voltage between VRH to VRL into 256 division into equal parts. The smoothness of the conversion characteristic is shown, and ideally, the width of the analog input voltage corresponding to change for 1 bit of digital outputs is 1LSB= (VRH-VRL)/256, and says the deviation of this ideal bit size and the bit size in the arbitrary points of the conversion range. Digital output "000H" to "001H" changes, and the deviation of the ideal conversion characteristic of a point and the actual conversion characteristic is said. Digital output "0FEH" to "0FFH" changes, and the deviation of the ideal conversion characteristic of a point and the actual conversion characteristic is said.
Differentiation linearity error
Zero scale error
Full scale error
10/26
FEDL9226-01
OKI Semiconductor
ML9226
Keyscan Characteristics
(Ta = -40 to +85C, VDISP = 8.0 to 18.5 V) Parameter Keyscan Cycle Time Keyscan Pulse Width Condition R = 10 k 5%, Co = 27 pF 5% R = 10 k 5%, Co = 27 pF 5% Min. 160 32 Typ. 194 39 Max. 246 49 Unit s s
Rotary switch characteristic
(Ta = -40 to +85C, VDISP = 8.0 to 18.5 V) Parameter Phase input time Phase input fixed time Sign tABW tABH Condition R = 10 k 5%, CO = 27 pF 5% Min. 950 Typ. -- Max. -- Unit s
Rotary switch input timing
A
B tABW tABH tABW tABH tABW tABW
Keyscan Timing
Keyscan Cycle Time ROW1 Keyscan Pulse Width ROW2
ROW3
ROW4
ROW5
11/26
FEDL9226-01
OKI Semiconductor
ML9226
Output Timing (Duplex Operation) *1 bit time = 4/fOSC
Solid line : The dimming data is 1016/1024 Dotted line : The dimming data is 64/1024 2048 bit times(1 display cycle) GRID1 1016 bit times 8 bit times GRID2 1016 bit times 1016 bit times 8 bit times 8 bit times VDISP D-GND VDISP D-GND VDISP 64 bit times SEG1-32 64 bit times 64 bit times D-GND VDISP D-GND 5V DIM OUT L-GND 5V SYNC OUT1 L-GND 5V SYNC OUT2 L-GND
GRID3
Output Timing (Triplex Operation) *1 bit time = 4/fOSC Solid line : The dimming data is 1016/1024 Dotted line : The dimming data is 64/1024
3072 bit times(1 display cycle) GRID1 1016 bit times 8 bit times GRID2 1016 bit times 8 bit times 8 bit times VDISP D-GND VDISP D-GND 1016 bit times 64 bit times SEG1-32 64 bit times 64 bit times VDISP D-GND VDISP D-GND 5V DIM OUT L-GND 5V SYNC OUT1 L-GND 5V SYNC OUT2 L-GND
GRID3
12/26
FEDL9226-01
OKI Semiconductor
ML9226
FUNCTIONAL DESCRIPTION
Power-on Reset When power is turned on, ML9226 is initialized by the internal power-on reset circuit. The status of the internal circuit after initialization is as follows: * The contents of the shift registers and latches are set to "0". * The digital dimming duty cycle is set to "0". * All segment outputs are set to Low level. * GRID1 outputs are set to Low level. * GRID2 to 3 outputs are set to High level. * All the ROW outputs are set to Low level. * INT output is set to Low level.
Mode Data ML9226 has the seven function modes. The function mode is selected by the mode data (M0 to M2). The relation between function mode and mode data (M0 to M2) is as follows:
FUNCTION MODE 0 1 2 3 4 5 6 7
OPERATING MODE Segment Data for GRID1-3 Input Segment Data for GRID1 Input Segment Data for GRID2 Input Segment Data for GRID3 Input Digital Dimming Data Input Keyscan Stop Switch Data Output A/D Data Output
FUNCTION DATA M0 0 1 0 1 0 1 0 1 M1 0 0 1 1 0 0 1 1 M2 0 0 0 0 1 1 1 1
Data Input and Output Data input and output through the DATA I/O pin is valid only when the CS pin is set at a High level. The input data to DATA I/O pin is shifted into the shift register at the rising edge of the serial clock. The data is automatically loaded to the latches when the CS pin is set at a Low level. 10-bit dimming data (D1 to D10) and 32-bit segment data (S1 to S32) are used for inputting of dimming data and display data. To transfer these two data, the mode data (M0 to M2) must be sent after each of these data succeddingly. The output data from the DATA I/O pin is output from the shift register at the rising edge of the serial clock. ML9226 outputs 64-bit (8 ch x 8 bits) A/D data (A11 to A88) and 37-bit key data (S11 to S55, R1, Q11 to Q13, R2, Q21 to Q23, R3 and Q31 to Q33). To receive these data, the mode data (M0 to M2) mast be sent first and then CS must be set once to Low level and set again to High level. Then inputting serial clocks, these data are output from the DATA I/O pin. When the CS pin is set at a Low level, the DATA I/O pin returns to an input pin. To stop the keyscan, the only mode data (M0 to M2) must be sent. After the mode data transfer, the key scanning is stopped immediately.
13/26
FEDL9226-01
OKI Semiconductor
ML9226
Segment Data Input [Function Mode: 0 to 3] * ML9226 receives the segment data when function mode 0 to 3 are selected. * The same segment data is transferred to the 3 segment data latch correspond to GRID1 to 3 at the same time when the function mode 0 is selected. * The segment data is transferred to only one segment data latch that is selected by mode data, when the function mode is 1, 2 or 3 is selected. * Segment output (SEG1 to 32) becomes High level when the segment data (S1 to 32) is High level. [Data Format] Input Data Segment Data Mode Data
Bit Input Data 1 S1 LSB 2 S2
: 35 bits : 32 bits : 3 bits
3 S3 4 S4 29 30 31 32 33 34 35
S29 S30 S31 S32 M0 M1 M2 MSB Mode Data Segment Data (32 bits) (3 bits)
[Bit correspondence between segment output and segment data]
SEG n Segment data SEG n Segment data
1 S1 17 S17
2 S2 18 S18
3 S3 19 S19
4 S4 20 S20
5 S5 21 S21
6 S6 22 S22
7 S7 23 S23
8 S8 24 S24
9 S9 25 S25
10 S10 26 S26
11 S11 27 S27
12 S12 28 S28
13 S13 29 S29
14 S14 30 S30
15 S15 31 S31
16 S16 32 S32
14/26
FEDL9226-01
OKI Semiconductor
ML9226
Digital Dimming Data Input [Function Mode: 4] * ML9226 receives the digital dimming data when function mode 4 is selected. * The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. * The 10-bit digital dimming data is input from LSB. [Data Format] Input Data : 13 bits Digital Dimming Data : 10 bits Mode Data : 3 bits
Bit Input Data 1 2 3 D3 4 D4 5 D5 6 D6 7 D7 8 D8 9 10 11 12 13
D1 D2 LSB
D9 D10 M0 M1 M2 MSB Mode Data Digital Dimming Data (10 bits) (3 bits)
(LSB) D1 0 1 1 0 1 1 D2 0 0 1 0 0 1 D3 0 0 1 0 0 1 D4 0 0 0 1 1 1
Dimming Data D5 0 0 ... 1 1 1 ... 1 D6 0 0 1 1 1 1 D7 0 0 1 1 1 1 D8 0 0 1 1 1 1 D9 0 0 1 1 1 1
(MSB) D10 0 0 1 1 1 1
Duty Cycle 0/1024 1/1024 1015/1024 1016/1024 1016/1024 1016/1024 ... ...
Keyscan Stop [Function Mode: 5] * ML9226 stops a key scanning when function mode 5 are selected. * To select this mode, the only mode data (M0 to M2) is needed. * The actual time lag range between receipt of the keyscan stop command and the ceasing of scanning is 2.4 s to 3.6 s [Input Data Format] Input Data Mode Data
Bit Input Data 28 M0
: 3 bits : 3 bits
29 M1 Mode Data (3 bits) 30 M2
15/26
FEDL9226-01
OKI Semiconductor
ML9226
Switch Data Output [Function Mode: 6] * * * * * * * * ML9226 output the switch data when function mode 6 is selected. To select this mode, the only mode data (M0 to M2) is needed. When ML9226 recieves this mode, the DATA I/O pin is changed to an output pin. 37-bit switch data come out from the DATA I/O pin synchronizing with the rise edge of the clock. When the CS pin is set at the low level, the DATA I/O pin returns to an input pin. R1, R2, R3 = 0, implies Right rotation of the knob (Clockwise) R1, R2, R3 = 1, implies Left rotation of the knob (Counter Clockwise) Contact Count bits are Q11 (LSB) to Q13 (MSB), Q21 (LSB) to Q23 (MSB) and Q31 (LSB) to Q33 (MSB)
[Input Data Format] Input Data Mode Data
Bit Input Data 28 M0
: 3 bits : 3 bits
29 M1 Mode Data (3 bits) 30 M2
[Output Data Format] Output Data : 37 bits 5 x 5 push swithc Data : 25 bits Encoder switch Data : 12 bits
Bit 1 2 3 4 5 6 7 8 9 10 11 Output S11 S12 S13 S14 S15 S21 S22 S23 S24 S25 S31 Data Bit 26 27 28 29 30 31 32 33 34 35 36 Output R1 Q11 Q12 Q13 R2 Q21 Q22 Q23 R3 Q31 Q32 Data 12 37 Q33 13 14 15 16 17 18 19 20 21 22 23 24 25
S32 S33 S34 S35 S41 S42 S43 S44 S45 S51 S52 S53 S54 S55
Sij: i = ROW1 to 5, j = COL1 to 5 Sij = 1: Switch ON Sij = 0: Switch OFF
[5x5 Push switch]
ROW1 ROW2 COL1 COL2 COL3 COL4 COL5 = ROW3 ROW4 ROW5
16/26
FEDL9226-01
OKI Semiconductor
ML9226
Keyscan Keyscanning is started only when depression or release of any key is detected in order to minimize noise caused by scanning signal. Then, keyscanning is continued until the keyscan stop mode is sent from a microcomputer. The INT pin goes to the high level at the completion of 1-cycle scanning after the keyscan start, so the (high level) signal sent from the INT pin can be used as an interrupt signal. [Keyscan Timing]
ROW 1
ROW 2 ROW 3
ROW 4
ROW 5 1 Cycle INT
Depress/Release
Keyscan stop mode is selected.
Note:
Keyscanning cannot be stopped by selecting the keyscan stop mode only once if: - keyscanning is started after depression or release of any key is detected, and then - a key is depressed or released again before the keyscan stop mode is selected. To stop keyscanning, it is required to select the keyscan stop mode once again.
Depress
Depress
Release
INT
Keyscan
Keyscan
CS
MODE5 MODE5 : Keyscan stop
MODE5
MODE5
17/26
FEDL9226-01
OKI Semiconductor
ML9226
A/D Data Output [Function Mode: 7] * * * * * ML9226 output the A/D data when function mode 7 is selected. To select this mode, the only mode data (M0 to M2) is needed. When ML9226 recieves this mode, the DATA I/O pin is changed to an output pin. 64-bit A/D data come out from the DATA I/O pin synchronizeing with the rise edge of the clock. When the CS pin is set at the low level, the DATA I/O pin returns to an input pin.
[Input Data Format] Input Data Mode Data
Bit Input Data 28 M0
: 3 bits : 3 bits
29 M1 Mode Data (3 bits) 30 M2
[Output Data Format] Output Data A/D Data
Bit Output Data A/D Bit Output Data A/D Bit Output Data A/D Bit Output Data A/D 1 A11 (LSB) 17 A31 (LSB) 33 A51 (LSB) 49 A71 (LSB) 2 A12 3 A13
: 64 bits : 64 bits
4 A14 5 A15 6 A16 7 A17 8 9 A18 A21 (MSB) (LSB) 24 25 A38 A41 (MSB) (LSB) 40 41 A58 A61 (MSB) (LSB) 56 57 A78 A81 (MSB) (LSB) 10 A22 11 A23 12 A24 13 A25 14 A26 15 A27 16 A28 (MSB) 32 A48 (MSB) 48 A68 (MSB) 64 A88 (MSB)
18 A32
19 A33
CH1 20 21 A34 A35 CH3 36 37 A54 A55 CH5 52 53 A74 A75 CH7
22 A36
23 A37
26 A42
27 A43
CH2 28 29 A44 A45 CH4 44 45 A64 A65 CH6 60 61 A84 A85 CH8
30 A46
31 A47
34 A52
35 A53
38 A56
39 A57
42 A62
43 A63
46 A66
47 A67
50 A72
51 A73
54 A76
55 A77
58 A82
59 A83
62 A86
63 A87
18/26
FEDL9226-01
OKI Semiconductor
ML9226
The rotary encoder switch function. As figure 1 shows, the rotary encoder switch circuit is consisted of Phase detection, Interrupt generation, Up/down counter, Direction latch and Parallel-in serial-out shift register.
A
B
Phase Detection UP DOWN Interrupt Generation for INT
UP/DOWN Counter Q3 Q2 Q1
Direction Latch R1
P-in/S-out Shift Registor
Output data
Fig.1 The Rotary Encoder Switch Circuit
1) Phase detection 1-1) Clockwise When signal A and B input as fig. 2, the phase detection circuit outputs UP signal after the chattering absorption period. At this time, the output INT also goes to high level, so this signal can be used as an interrupt. The INT stays High level until the key scan stop mode is selected.
A
B chattering absorption time UP (internal)
INT
Fig.2 The Input and Output Timing in Case of Clockwise.
19/26
FEDL9226-01
OKI Semiconductor
ML9226
1-2) counter clockwise When signal A and B input as fig. 3, the phase detection circuit outputs Down signal after the chattering absorption period. At this time, the output INT also goes to High level. The INT stays High level until the key scan stop mode is selected.
A
B chattering absorption time DOWN (internal)
INT
Fig.3 The Input and Output Timing in Case of Counter Clockwise.
2) UP/DOWN COUNTER When the UP/DOWN COUNTER is input UP, it counts up and when it is input DOWN, it counts down. But if overcounte of "111" occurs the UP/DOWN COUNTER stays "111".
A
B
Q1, Q2, Q3
100
010
110
001
101
011
111
111
Fig.4 3) Direction latch When the Direction latch is input DOWN the output R goes "1". But if the UP pulse is input and the counts value change to plus value, the output R goes to "0".
A
B
R1
Q1, Q2, Q3
100
010
100
000
100
010
Fig.5
20/26
FEDL9226-01
OKI Semiconductor
ML9226
4) P-in/S-out shift resistor When the key scan stop mode is selected and SC goes L, INT signal goes "L".
CS Data I/O
C1 C2 C3 C4 C5 C1 C2 C3 C4 C5 C1 C2 C3 C4 C5 R1 Q11 Q12 Q13
R2 Q21 Q22 Q23 R3 Q31 Q32 Q33
ROW1 CLOCK
ROW2
ROW5
Rotary
INT
INT signal goes "L".
Fig.6
21/26
OKI Semiconductor
VDISP SEG1 ML9226 VDISP ML9213 SEG1
VCC
VDD
(MASTER) (SLAVE) SEG56
DUP/TRI M/S GND
S1S2 S3 S62 S63 S64
APPLICATION CIRCUITS
VDISP GRID1 GRID2 GRID3 G1 Duplex VFD Tube G2 Ef
DUP/TRI
VREG
SEG32 GRID1 GRID2 GRID3
CH1 to 8
GND 5x5 Key matrix
ROW1 to 5 COL1 to 5
1. Circuit for the duplex VFD tube with 128 segments (2 Grid x 64 Anode)
Microcontroller
OSC 0
GND
CS DATA I/O CLOCK VCC OSC0
SYNC OUT 2 SYNC OUT 1 DIM OUT
SYNC IN 2 SYNC OUT 2 SYNC IN 1 SYNC OUT 1 DIM IN DIM OUT CS DATA IN CLOCK OSC 1
L-GND GND
L-GND
FEDL9226-01
GND
ML9226
22/26
OKI Semiconductor
VCC
SEG1
VDISP
VDD
VDISP
SEG1
VDISP
GRID1 GRID2 GRID3
ML9226 (MASTER) SEG32
DUP/TRI M/S GND
G1 G2 G3 S1 S2 S3 GRID1 GRID2 GRID3
ML9213 (SLAVE) SEG56
VREG
CH1 to 8
S62 S63 S64
GND
5x5 Key matrix
ROW1 to 5
Triplex VFD Tube
COL1 to 5
Ef
2. Circuit for the triplex VFD tube with 192 segments (3 Grid x 64 Anode)
Microcontroller
OSC 0
GND
DUP/TRI SYNC OUT 2 SYNC OUT 1 DIM OUT CS DATA I/O CLOCK VCC OSC0 L-GND L-GND GND
SYNC IN 2 SYNC OUT 2 SYNC IN 1 SYNC OUT 1 DIM IN DIM OUT CS DATA IN CLOCK OSC 1
FEDL9226-01
GND
ML9226
23/26
FEDL9226-01
OKI Semiconductor
ML9226
PACKAGE DIMENSIONS
(Unit: mm)
QFP80-P-1420-0.80-BK
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 1.27 TYP. 4/Nov. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
24/26
FEDL9226-01
OKI Semiconductor
ML9226
REVISION HISTORY
Page Previous Current Edition Edition
- -
Document No.
FEDL9226-01
Date
Dec. 11, 2002
Description
Preliminary edition 1
25/26
FEDL9226-01
OKI Semiconductor
ML9226
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd.
3.
4.
5.
6.
7.
8.
26/26

▲Up To Search▲

Price & Availability of ML9226GA

	To Download ML9226GA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .