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Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
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Low Voltage Zero Delay Buffer
The MPC961 is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay buffer. With output frequencies of up to 200MHz, output skews of 150ps the device meets the needs of the most demanding clock tree applications.
MPC961C
Freescale Semiconductor, Inc...
* * * * * * * *
Fully Integrated PLL Up to 200MHz I/O Frequency LVCMOS Outputs Outputs Disable in High Impedance LVCMOS Reference Clock Options LQFP Packaging 50ps Cycle-Cycle Jitter 150ps Output Skews
LOW VOLTAGE ZERO DELAY BUFFER
The MPC961 is offered with two different input configurations. The MPC961C offers an LVCMOS reference clock while the MPC961P offers an LVPECL reference clock. When pulled high the OE pin will force all of the outputs (except QFB) into a high impedance state. Because the OE pin does not affect the QFB output, down stream clocks can be disabled without the internal PLL losing lock. The MPC961 is fully 2.5V or 3.3V compatible and requires no external loop filter components. All control inputs accept LVCMOS compatible levels and the outputs provide low impedance LVCMOS outputs capable of driving terminated 50W transmission lines. For series terminated lines the MPC961 can drive two lines per output giving the device an effective fanout of 1:36. The device is packaged in a 32 lead LQFP.
FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-02
Q0 Ref PLL 100 - 200 MHz 50 - 100 MHz FB_IN 50k Q14 F_RANGE 50k Q15 Q16 OE 50k QFB FB Q1 O 1 Q2 Q3
CCLK 50k
The MPC961C requires an external RC filter for the analog power supply pin VCCA. Please see applications section for details.
Figure 1. MPC961C Logic Diagram
03/01
(c) Motorola, Inc. 2001
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GND VCC Q10 18 Q11 17 16 15 14 13 VCC Q12 Q13 Q14 GND Q15 Q16 QFB 12 11 10 9 1 2 3 4 5 6 7 8 VCC Function PLL reference clock signal PLL feedback signal input, connect to a QFB output PLL frequency range select Output enable/disable Clock outputs PLL feedback signal output, connect to a FB_IN Negative power supply PLL positive power supply (analog power supply). The MPC961C requires an external RC filter for the analog power supply pin VCCA. Please see applications section for details. Positive power supply for I/O and core Not connected
Q6
Q7
Q8
24 Q5 Q4 Q3 GND Q2 Q1 25 26 27 28
23
22
21
20
MPC961C
29 30 31 32
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Q0 VCC
CCLK
F_RANGE
VCCA
GND
NC
Q9 19 OE
Figure 2. 32-Lead Pinout (Top View)
Table 1: PIN CONFIGURATIONS
Pin CCLK FB_IN F_RANGE OE Q0 - Q16 QFB GND VCCA I/O Input Input Input Input Output Output Supply Supply Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC
VCC NC
Supply
VCC
Table 2: FUNCTION TABLE
Control F_RANGE OE Default 0 0 0 PLL high frequency range. MPC961C input reference and output clock frequency range is 100 - 200 MHz Outputs enabled 1 PLL low frequency range. MPC961C input reference and output clock frequency range is 50 - 100 MHz Outputs disabled (high-impedance state)
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FB_IN
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Table 3: ABSOLUTE MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Range -40 Parameter Min -0.3 -0.3 -0.3 Max 3.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.
Table 4: DC CHARACTERISTICS (VCC = 3.3V 5%, TA = -40 to 85C)
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Symbol VIH VIL VOH VOL ZOUT IIN CIN CPD ICCA ICC VTT
Characteristic Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Output Impedance Input Current Input Capacitance Power Dissipation Capacitance Maximum PLL Supply Current Maximum Quiescent Supply Current Output Termination Voltage
Min 2.0 -0.3 2.4
Typ
Max VCC + 0.3 0.8
Unit V V V
Condition LVCMOS LVCMOS IOH = -20mAa IOL = 20mAa
0.55 14 20 120 4.0 8.0 2.0 10 5.0
V
W
A pF pF mA mA V
Per Output VCCA Pin All VCC Pins
VCC
B2
a. The MPC961C is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up two 50 series terminated transmission lines.
Table 5: AC CHARACTERISTICS (VCC = 3.3V 5%, TA = -40 to 85C)a
Symbol fref fmax frefDC tr, tf t() tsk(O) DCO tr, tf tPLZ,HZ tPZL,LZ tJIT(CC) tJIT(PER) tJIT() tlock Input Frequency Maximum Output Frequency Reference Input Duty Cycle TCLK Input Rise/Fall Time Propagation Delay (static phase offset) Output-to-Output Skewb Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time RMS (1 F_RANGE = 0 F_RANGE = 1 42 45 0.1 CCLK to FB_IN -80 90 50 50 Characteristic F_RANGE = 0 F_RANGE = 1 F_RANGE = 0 F_RANGE = 1 Min 100 50 100 50 25 Typ Max 200 100 200 100 75 3.0 120 150 55 55 1.0 10 10 Unit MHz MHz % ns ps ps % ns ns ns ps ps ns ms 0.55 to 2.4V 0.8 to 2.0V PLL locked Condition
s)c RMS (1 s) RMS (1 s) s
15 7.0 10 15 10
a. AC characteristics apply for parallel output termination of 50W to VTT b. See applications section for part-to-part skew calculation c. See applications section for calculation for other confidence factors than 1
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Table 6: DC CHARACTERISTICS (VCC = 2.5V 5%, TA = -40 to 85C)
Symbol VIH VIL VOH VOL ZOUT IIN CIN CPD ICCA ICC Characteristic Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Output Impedance Input Current Input Capacitance Power Dissipation Capacitance Maximum PLL Supply Current Maximum Quiescent Supply Current 4.0 8.0 2.0 10 5.0 18 Min 1.7 -0.3 1.8 0.6 26 120 Typ Max VCC + 0.3 0.7 Unit V V V V Condition LVCMOS LVCMOS IOH = -15mAa IOL = 15mAa
W
A pF pF mA mA
Per Output VCCA Pin All VCC Pins
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VTT Output Termination Voltage VCC 2 V a. The MPC961C is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up two 50 series terminated transmission lines.
B
Table 7: AC CHARACTERISTICS (VCC = 2.5V 5%, TA = -40 to 85C)a
Symbol fref fmax frefDC tr, tf t() tsk(O) DCO tr, tf tPLZ,HZ tPZL,LZ tJIT(CC) tJIT(PER) tJIT() Input Frequency Maximum Output Frequency Reference Input Duty Cycle TCLK Input Rise/Fall Time Propagation Delay (static phase offset) Output-to-Output Skewb Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter RMS (1 F_RANGE = 0 F_RANGE = 1 40 45 0.1 CCLK to FB_IN -80 90 50 50 Characteristic F_RANGE = 0 F_RANGE = 1 F_RANGE = 0 F_RANGE = 1 Min 100 50 100 50 25 Typ Max 200 100 200 100 75 3.0 120 150 60 55 1.0 10 10 Unit MHz MHz % ns ps ps % ns ns ns ps ps ns ms 0.6 to 1.8V 0.7 to 1.7V PLL locked Condition
s)c RMS (1 s) RMS (1 s) s
15 7.0 10 15 10
tlock Maximum PLL Lock Time a. AC characteristics apply for parallel output termination of 50W to VTT b. See applications section for part-to-part skew calculation c. See applications section for calculation for other confidence factors than 1
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Power Supply Filtering The MPC961C is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC961C provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC961C. Figure 3. illustrates a typical power supply filter scheme. The MPC961C is most susceptible to noise with spectral content in the 10kHz to 10MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC961C. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 2mA (5mA maximum), assuming that a minimum of 2.375V (VCC = 3.3V or VCC = 2.5V) must be maintained on the VCCA pin. The resistor RF shown in Figure 3. must have a resistance of 270 (VCC = 3.3V) or 5 to 15 (VCC = 2.5V) to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20kHz. As the noise frequency crosses the series resonant point of an individual capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. adequate to eliminate power supply noise related problems in most designs. Driving Transmission Lines The MPC961C clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 15 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC961C clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4. illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC961C clock driver is effectively doubled due to its capability to drive multiple lines.
MPC961 OUTPUT BUFFER IN
14
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RS = 36
ZO = 50 OutA
MPC961 OUTPUT BUFFER IN
14
RS = 36
ZO = 50 OutB0
RF = 270 for VCC = 3.3V RF = 5-15 for VCC = 2.5V RF VCC 22 F 10 nF
RS = 36 VCCA MPC961C
ZO = 50 OutB1
Figure 4. Single versus Dual Transmission Lines
VCC 33...100 nF
Figure 3. Power Supply Filter Although the MPC961C has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be
The waveform plots of Figure 5. show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC961C output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC961C. The output waveform in Figure 5. shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel
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combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Zo / (Rs + Ro +Zo)) Zo = 50 || 50 Rs = 36 || 36 Ro = 14 VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.62V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). SPICE level and IBIS output buffer models are available for engineers who want to simulate their specific interconnect schemes. Using the MPC961C in zero-delay applications Nested clock trees are typical applications for the MPC961C. Designs using the MPC961C as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC961C clock driver allows for its use as a zero delay buffer. By using the QFB output as a feedback to the PLL the propagation delay through the device is virtually eliminated. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device. The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of part-to-part skew The MPC961C zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC961C are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is:
2 4 6 8 TIME (nS) 10 12 14
3.0
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2.5
OutA tD = 3.8956
OutB tD = 3.9386
VOLTAGE (V)
2.0 In 1.5
1.0
0.5
0
Figure 5. Single versus Dual Waveforms
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter:
Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 6. should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
CCLKCommon
-t()
tPD,LINE(FB)
QFBDevice 1
tJIT()
Any QDevice 1
+tSK(O) +t()
MPC961 OUTPUT BUFFER
14
RS = 22
ZO = 50
QFBDevice2
tJIT()
RS = 22
ZO = 50
Any QDevice 2 Max. skew
+tSK(O) tSK(PP)
14 + 22 k 22 = 50 k 50 25 = 25 Figure 6. Optimized Dual Line Termination
Figure 7. MPC961C max. device-to-device skew Due to the statistical nature of I/O jitter a rms value (1 s) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8.
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Table 8: Confidence Facter CF
CF 1s 2s 3s 4s 5s 6s Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999
convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the MPC961C die junction temperature and the associated device reliability. For a complete analysis of power consumption as a function of operating conditions and associated long term device reliability please refer to the application note AN1545. According the AN1545, the long-term device reliability is a function of the die junction temperature: Table 9: Die junction temperature and MTBF
Junction temperature (C) 100 110 120 130 MTBF (Years) 20.4 9.1 4.2 2.0
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The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3s) is assumed, resulting in a worst case timing uncertainty from input to any output of -275 ps to 315 ps relative to CCLK:
tSK(PP) = tSK(PP) =
[-80ps...120ps] + [-150ps...150ps] + [(15ps -3)...(15ps 3)] + tPD, LINE(FB)
@
@
[-275ps...315ps] + tPD, LINE(FB)
Due to the frequency dependence of the I/O jitter, Figure 8. "Max. I/O Jitter versus frequency" can be used for a more precise timing performance analysis.
Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the MPC961C needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the MPC961C is represented in equation 1. Where ICCQ is the static current consumption of the MPC961C, CPD is the power dissipation capacitance per output, ()CL represents the external capacitive output load, N is the number of active outputs (N is always 27 in case of the MPC961C). The MPC961C supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, CL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation.
Figure 8. Max. I/O Jitter versus frequency Power Consumption of the MPC961C and Thermal Management The MPC961C AC specification is guaranteed for the entire operating frequency range up to 200 MHz. The MPC961C power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical P TOT
In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cyle. If transmission lines are used CL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. CL
M
+
I CCQ
)V @f
CC
CLOCK
@ N@C )
PD
@V
OH
CC
Equation 1
P TOT
+V @
CC
I CCQ
)V @f
CC
CLOCK
@ N@C )
PD
CL
M
)
thja
DC Q
P
@ I @ V * V ) 1 * DC @ I @ V
CC OH Q OL
OL
Equation 2
TJ
+T )P @R
A TOT 2 CC
Equation 3
f CLOCK,MAX
1 +C @N@V @
PD
T J,MAX T A R thja
* * I @V
CCQ
CC
Equation 4
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Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 9, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the MPC961C in a series terminated transmission line system. Table 10: Thermal package impedance of the 32ld LQFP
Convection, LFPM Still air 100 lfpm 200 lfpm Rthja (1P2S board), K/W 80 70 61 57 56 55
TJ,MAX should be selected according to the MTBF system requirements and Table 9. Rthja can be derived from Table 10. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below. If the calculated maximum frequency is below 200 MHz, it becomes the upper clock speed limit for the given application conditions. The following two derating charts describe the safe frequency operation range for the MPC961C. The charts were calculated for a maximum tolerable die junction temperature of 110C, corresponding to an estimated MTBF of 9.1 years, a supply voltage of 3.3V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. There are no operating frequency limitations if a 2.5V power supply or the system specifications allow for a MTBF of 4 years (corresponding to a max. junction temperature of 120C.
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300 lfpm 400 lfpm 500 lfpm
200 OPERATING FREQUENCY (MHz) 180 160 140 120 100 80 60 40 20 0 500 400
fMAX (AC) TA = 85C OPERATING FREQUENCY (MHz)
200 180 160 140 120 100 80 60 40 20 0
fMAX (AC) TA = 75C TA = 85C
Safe operation
300 200 IFPM, CONVECTION 100 0
Safe operation
500 400 300 200 IFPM, CONVECTION 100 0
Figure 9. Maximum MPC961C frequency, VCC = 3.3V, MTBF 9.1 years, driving series terminated transmission lines
Figure 10. Maximum MPC961C frequency, VCC = 3.3V, MTBF 9.1 years, 4 pF load per line
MPC961C DUT Pulse Generator Z = 50W ZO = 50 ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 11. TCLK MPC961C AC test reference for Vcc = 3.3V and Vcc = 2.5V
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VCC VCC
B2 B2
GND VOH VCC
CCLK
VCC VCC VCC VCC
B2 B2
GND FB_IN
GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device
GND t()
Figure 12. Output-to-output Skew tSK(O)
VCC VCC tP T0 DC = tP /T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
Figure 13. Propagation delay (tPD, static phase offset) test reference
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B2
CCLK
GND FB_IN
TJIT ) = |T0 -T1 mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles
Figure 14. Output Duty Cycle (DC)
Figure 15. I/O Jitter
TN
TN+1
TJIT(CC) = |TN -TN+1 |
T0
TJIT(PER) = |TN -1/f0 |
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles
Figure 16. Cycle-to-cycle Jitter
Figure 17. Period Jitter
VCC=3.3V 2.4 0.55 tF tR
VCC=2.5V 1.8V 0.6V
Figure 18. Output Transition Time Test Reference
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OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A
A A1
32 25 4X
0.20 (0.008) AB T-U Z
1
-T- B
-U- V P AE
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B1
8
DETAIL Y
17
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
F
8X
M_ R
CE
SECTION AE-AE
X DETAIL AD
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GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
EE EE EE EE
N
D
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
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NOTES
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TIMING SOLUTIONS MPC961C/D DL207 -- Rev 0

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