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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order number: MPC962308 Rev 3, 08/2004
3.3 V Zero Delay Buffer
The MPC962308 is a 3.3 V Zero Delay Buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications. The MPC962308 uses an internal PLL and an external feedback path to lock its low-skew clock output phase to the reference clock phase, providing virtually zero propagation delay. The input-to-output skew is guaranteed to be less than 250 ps and output-to-output skew is guaranteed to be less than 200 ps. Features * * 1:8 outputs LVCMOS zero-delay buffer Zero input-output propagation delay, adjustable by the capacitive load on FBK input Multiple Configurations, see Table 2. Available MPC962308 Configurations Multiple low-skew outputs 200 ps max output-output skew 700 ps max device-device skew Two banks of four outputs, output tristate control by two select inputs Supports a clock I/O frequency range of 10 MHz to 133 MHz Low jitter, 200 ps max cycle-cycle (-1, -1H, -4, -5H) 250 ps static phase offset (SPO) 16-pin SOIC package or 16-pin TSSOP package Single 3.3 V supply Ambient temperature range: -40C to +85C Compatible with the CY2308 and CY23S08 Spread spectrum compatible
MPC962308
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D SUFFIX 16-LEAD SOIC PACKAGE CASE 751B-05
* * * * * * * * * * * * *
DT SUFFIX 16-LEAD TSSOP PACKAGE CASE 948F-01
Functional Description The MPC962308 has two banks of four outputs each which can be controlled by the select inputs as shown in Table 1. Select Input Decoding. Bank B can be tristated if all of the outputs are not required. The select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. The MPC962308 PLL enters a power down state when there are no rising edges on the REF input. During this state, all of the outputs are in tristate and there is less than 50 A of current draw. The PLL shuts down in two additional cases explained in Table 1. Select Input Decoding. Multiple MPC962308 devices can accept and distribute the same input clock throughout the system. In this situation, the difference between the output skews of two devices will be less than 700 ps. The MPC962308 is available in five different configurations as shown in Table 2. Available MPC962308 Configurations. In the MPC962308-1, the reference frequency is reproduced by the PLL and provided at the outputs. A high drive version of this configuration, the MPC962308-1H, is available to provide faster rise and fall times of the device. The MPC962308-2 provides 2X and 1X the reference frequency at the output banks. In addition, the MPC962308-3 provides 4X and 2X the reference frequency at the output banks. The output banks driving the feedback will determine the different configurations of the above devices. The MPC962308-4 provides outputs 2X the reference frequency.The MPC962308-5H is a high drive version with outputs of REF/2. The MPC962308 is fully 3.3 V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines on the incident edge. Depending on the configuration, the device is offered in a 16-lead SOIC or 16-lead TSSOP package.
(c) Motorola, Inc. 2004
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MPC962308
Block Diagram
/2 REF /2 Extra Divider (-3, -4) Extra Divider (-5H) S2 S1 Select Input Decoding
Pin Configuration
SOIC/TSSOP Top View REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1
PLL MUX
FBK CLKA1 CLKA2 CLKA3 CLKA4 /2
CLKB1 CLKB2 CLKB3
Extra Divider (-2, -3)
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CLKB4
Table 1. Select Input Decoding
S2 0 0 1 1 S1 0 1 0 1 CLOCK A1--A4 Three-State Driven Driven1 Driven CLOCK B1--B4 Three-State Three-State Driven1 Driven Output Source PLL PLL Reference PLL PLL Shutdown Y N Y N
1. Outputs inverted on MPC962308-2 in bypass mode, S2=1 and S1=0.
Table 2. Available MPC962308 Configurations
Device MPC962308-1 MPC962308-1H MPC962308-2 MPC962308-2 MPC962308-3 MPC962308-3 MPC962308-4 MPC962308-5H Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A or Bank B Bank A or Bank B Bank A Frequency Reference Reference Reference 2 X Reference 2 X Reference 4 X Reference 2 X Reference Reference /2 Bank B Frequency Reference Reference Reference/2 Reference Reference or Reference[1] 2 X Reference 2 X Reference Reference /2
1. Output phase is indeterminate (0 or 180 from input clock). If phase integrity is required, use the MPC962308-2.
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MPC962308
Table 3. Pin Description
Pin 1 2 3 4 5 6 7 8 REF
1
Signal
Description Input reference frequency, 5 V tolerant input Clock output, Bank A Clock output, Bank A 3.3 V supply Ground
CLKA12 CLKA22 VDD GND CLKB1
2
Clock output, Bank B Clock output, Bank B Select input, bit 2 Select input, bit 1 Clock output, Bank B Clock output, Bank B Ground 3.3 V supply Clock output, Bank A Clock output, Bank A PLL feedback input
CLKB22 S23 S13 CLKB32 CLKB42 GND VDD CLKA32 CLKA42 FBK
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9 10 11 12 13 14 15 16
1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs.
Table 4. Maximum Ratings
Characteristics Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage REF Storage Temperature Junction Static Discharge Voltage (per MIL-STD-883, Method 3015) Value -0.5 to +3.9 -0.5 to VDD+0.5 -0.5 to 5.5 -65 to +150 150 >2000 Unit V V V C C V
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MPC962308
Table 5. Operating Conditions for MPC962308-X Industrial Temperature Devices
Parameter VDD TA CL Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz CIN Input Capacitance1 Description Min 3.0 -40 Max 3.6 85 30 15 7 Unit V C pF pF pF
1. Applies to both REF clock and FBK.
Table 6. Electrical Characteristics for MPC962308-X Industrial Temperature Devices1
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Parameter VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD
Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage2 Output HIGH Voltage2 Power Down Supply Current Supply Current VIN = 0V VIN = VDD
Test Conditions
Min
Max 0.8
Unit V V
2.0 50.0 100.0 0.4 2.4 25.0 45.0 70(-1H, -5H) 35.0 20.0
A A V V A mA mA mA mA
IOL = 8 mA (-1, -2, -3, -4) IOL = 12 mA (-1H, -5H) IOH = -8 mA (-1, -2, -3, -4) IOH = -12 mA (-1H, -5H) REF = 0 MHz Unloaded outputs, 100 MHz, Select inputs at VDD or GND Unloaded outputs, 66-MHz REF (-1, -2, -3, -4) Unloaded outputs, 35-MHz REF (-1, -2, -3, -4)
1. All parameters are specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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MPC962308
Table 7. Switching Characteristics for MPC962308-X Industrial Temperature Devices1
Parameter t1 t1 t1 Name Output Frequency Output Frequency2 Output Frequency2 Duty Cycle2 = t2 / t1 (-1, -2, -3, -4, -1H, -5H) Duty Cycle2 = t2 / t1 (-1, -2, -3, -4, -1H, -5H) t3 Rise Time2 (-1, -2, -3, -4) Rise Time2 (-1, -2, -3, -4) Rise Time2 (-1H, -5H) t4 Fall Time2 (-1, -2, -3, -4) Fall Time2 (-1, -2, -3, -4) Fall Time2 (-1H, -5H) Output-to-Output Skew on same Bank (-1, -2, -3, -4)2 t5 Output-to-Output Skew (-1H, -5H) Output Bank A to Output Bank B Skew (-1, -4, -5H) Output Bank A to Output Bank B Skew (-2, -3) t6 t7 t8 tJ Delay, REF Rising Edge to FBK Rising Edge2 Device-to-Device Skew2 Output Slew Rate
2
Test Conditions 30-pF load, All devices 20-pF load, -1H, -5H devices 15-pF load, -1, -2, -3, -4 devices Measured at 1.4 V, FOUT =66.66 MHz 30-pF load Measured at 1.4 V, FOUT <50.0 MHz 15-pF load Measured between 0.8 V and 2.0 V, 30-pF load Measured between 0.8 V and 2.0 V, 15-pF load Measured between 0.8 V and 2.0 V, 30-pF load Measured between 0.8 V and 2.0 V, 30-pF load Measured between 0.8 V and 2.0 V, 15-pF load Measured between 0.8 V and 2.0 V, 30-pF load All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the FBK pins of devices Measured between 0.8 V and 2.0 V on -1H, -5H device using Test Circuit # 2 Measured at 66.67 MHz, loaded outputs, 15-pF load Measured at 66.67 MHz, loaded outputs, 30-pF load Measured at 133.3 MHz, loaded outputs, 15 pF load
Min 10 10 10 40.0 45.0
Typ
Max 100 133.3 133.3 60.0 55.0 2.50 1.50 1.50 2.50 1.50 1.25 200 200 200 400
Unit MHz MHz MHz % % ns ns ns ns ns ns ps ps ps ps ps ps V/ns
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0 0 1
250 700
Cycle-to-Cycle Jitter (-1, -1H, -4, -5H)2
200 200 100 400 400 1.0
ps ps ps ps ps ms
tJ
Cycle-to-Cycle Jitter (-2, -3)2
Measured at 66.67 MHz, loaded outputs 30-pF load Measured at 66.67 MHz, loaded outputs 15-pF load
tLOCK
PLL Lock Time2
Stable power supply, valid clocks presented on REF and FBK pins
1. All parameters are specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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MPC962308
APPLICATIONS INFORMATION
VCC 1.4 V GND VCC 1.4 V GND t5 The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device t6 FB_IN CCLK
VCC VCC / 2 GND VCC VCC / 2 GND
Figure 1. Output-to-Output Skew tSK(O)
Figure 2. Static Phase Offset Test Reference
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VCC 1.4 V GND t2 t1 DC = t2/t1 x 100%
VCC DEVICE 1 VCC / 2 GND DEVICE 2 VCC VCC / 2 GND t7
The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
Figure 4. Device-to-Device Skew
Figure 3. Output Duty Cycle (DC)
VCC = 3.3 V 2.0 tJ = |tN-tN+1| t4 t3 0.8
tN
tN+1
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
Figure 5. Cycle-to-Cycle Jitter
Figure 6. Output Transition Time Test Reference
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MPC962308
Test Circuit #1
VDD 0.1 F OUTPUTS CLKOUT CLOAD 0.1 F VDD GND GND 0.1 F VDD GND GND 0.1 F
Test Circuit #2
VDD OUTPUTS 1 K
1 K
CLKOUT 10 pF
Test Circuit for all parameters except t8
Test Circuit for t8, Output slew rate on -1H, -5 device
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Ordering Information (Available)
Ordering Code MPC962308D-1 MPC962308D-1R2 MPC962308D-1H MPC962308D-1HR2 MPC962308DT-1H MPC962308DT-1HR2 MPC962308D-2 MPC962308D-2R2 Package Name D16 D16 D16 D16 DT16 DT16 D16 D16 16-pin 150-mil SOIC 16-pin 150-mil SOIC -- Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC -- Tape and Reel 16-pin 150-mil TSSOP 16-pin 150-mil TSSOP -- Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC -- Tape and Reel Package Type
Ordering Information (Planned)
Ordering Code MPC962308D-3 MPC962308D-3R2 MPC962308D-4 MPC962308D-4R2 MPC962308D-5H MPC962308D-5HR2 MPC962308DT-5H MPC962308DT-5HR2 Package Name D16 D16 D16 D16 D16 D16 DT16 DT16 16-pin 150-mil SOIC 16-pin 150-mil SOIC -- Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC -- Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC -- Tape and Reel 16-pin 150-mil TSSOP 16-pin 150-mil TSSOP -- Tape and Reel Package Type
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MPC962308
PACKAGE DIMENSIONS D SUFFIX
16 LEAD SOIC PACKAGE CASE 751B-05 ISSUE K
0.25
PIN'S NUMBER 1 8X M
B A
6.2 5.8
16
1.75 1.35
0.25 0.10
16X
0.49 0.35 0.25
6
M
TAB
PIN 1 INDEX
14X
1.27 4 A A 10.0 9.8
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS A AND B TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. INTER-LEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.62MM.
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8
9
T 4.0 3.8 5 0.50 0.25 B
16X
SEATING PLANE
0.1 T
X45
0.25 0.19
1.25 0.40 SECTION A-A
7 0
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MPC962308
PACKAGE DIMENSIONS DT SUFFIX
16 LEAD TSSOP PACKAGE CASE 948F-01 ISSUE O
K 0.15 (0.006) T U
S 16X
REF
M
0.10 (0.004)
TU
S
V
S
K K1
2X
L/2
16
9
J1 B -USECTION N-N J
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L
PIN 1 IDENT. 1 8
N 0.25 (0.010) 0.15 (0.006) T U
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-.
A -VN F DETAIL E
M
DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8
C 0.10 (0.004) -TSEATING PLANE
-W-
H D G
DETAIL E
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MPC962308
NOTES
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NOTES
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