View NBWLVEP16VR_1287435.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NBLVEP16VR 2.5V/3.3V/5V ECL Differential Receiver/Driver with Oscillator Gain Stage and Enabled High Gain Outputs
The NBLVEP16VR is an ECL/LVPECL oscillator gain stage with high-gain output buffers, selectable output enable and a feedback buffer. The NBLVEP16VR is a solution for crystal oscillators and SAW-based voltage-controlled oscillators. * Q and Q Outputs have Selectable 4 mA or 8 mA, Self Bias Current Sources * QHG and QHG have a Selectable 10 mA, Self Bias Current Sources * Synchronous Output Enable of the High-Gain Outputs with Selectable Disabled State * Selectable LVCMOS/LVTTL or LVPECL Level Input of the Output Enable Pin * Maximum Frequency > 2.5 GHz Typical * (LV)PECL Mode Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V * NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -5.5 V * Temperature Compensated Inputs and Outputs * Excellent Clock Input Sensitivity * VBB Output Supports Current Source/Sink Capability up to a Robust 1.5 mA
http://onsemi.com MARKING DIAGRAM
Bottom View QFN-16 MN SUFFIX CASE 485G XXXX A L Y W XXXX XXXX ALYW
= Device Code = Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device NBLVEP16VRMN NBLVEP16VRMNR2 Package QFN-16 QFN-16 Shipping 123 / Rail 3000/ Tape & Reel Refer to Note 1.
NBWLVEP16VR
Wafer
1. Contact Sales Representative. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications 4 mA ea. (opt.) Brochure, BRD8011/D.
4 mA ea. CS_SEL VEE
Q Q D D 470 W VBB VBB_ADJ OD_MODE LEN Q LATCH D 470 W 0 VBB Q Q
1
QHG QHG 10 mA ea. (opt.) VEEP
EN
LVCMOS/LVTTL Threshold
EN_SEL
Figure 1. Logic Diagram
(c) Semiconductor Components Industries, LLC, 2003
1
December, 2003 - Rev. 2
Publication Order Number: NBLVEP16VR/D
NBLVEP16VR
4 mA ea.
4 mA ea. (opt.) CS_SEL VEE
Q Q D D 470 W VBB VBB_ADJ OD_MODE LEN Q LATCH D 470 W 0 VBB Q Q
1
QHG QHG 10 mA ea. (opt.) VEEP
EN
LVCMOS/LVTTL Threshold
EN_SEL
Figure 2. Logic Diagram
Table 1. Q AND Q INTERNAL CURRENT SOURCE SELECTOR
CS_SEL OPEN VEE VCC Q 4 mA Typical 8 mA Typical 0 mA Q 4 mA Typical 8 mA Typical 4 mA Typical See Figure 13, 13 10, 13 13, 13
Table 2. QHG AND QHG INTERNAL CURRENT SOURCE SELECTOR
VEEP OPEN VEE QHG 0 mA 10 mA Typical QHG 0 mA 10 mA Typical See Figure 8, 11 9, 12
Table 3. OUTPUT ENABLE AND OUTPUT DISABLED STATE TRUTH TABLE
EN_SEL VCC or OPEN VCC or OPEN VEE VEE VCC or OPEN VCC or OPEN VEE VEE OD-MODE* Low or OPEN Low or OPEN Low or OPEN Low or OPEN High High High High EN* LVPECL Low, VEE or OPEN LVPECL High or VCC LVCMOS Low, VEE, or OPEN LVCMOS High or VCC LVPECL Low, VEE or OPEN LVPECL High or VCC LVCMOS Low, VEE, or OPEN LVCMOS High or VCC Q and Q Data Data Data Data Data Data Data Data QHG Data Low Low Data Data High High Data QHG Data High High Data Data Low Low Data
*Pins will default LOW when left open. Pin will default HIGH when left open.
http://onsemi.com
2
NBLVEP16VR
Exposed Pad (EP) Q 16 1 2 NBLVEP16VR D VBB 3 4 5 EN 6 7 8 10 9 QHG EN_SEL Q 15 NC 14 VCC 13 NC OD_MODE D 12 11 CS_SEL QHG D VBB VBB OD_MODE D NBLVEP16VR CS_SEL Die: 1.16 x 1.19 mm (x) (y) Bond Pad: 84 mm Diameter QHG QHG EN_SEL VEEP VCC NC Q Q VCC
EN VBB_ADJ VEE VEE
VBB_ADJ VEE VEEP
Figure 4. Die Map
Figure 3. Pinout Diagram (Top View) Table 4. PIN DESCRIPTION
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name OD_MODE* D D VBB EN* VBB_ADJ VEE VEEP EN_SEL QHG QHG CS_SEL VCC NC Q Q EP Positive Power Supply No Connect ECL / LVPECL Output ECL / LVPECL Output Power Supply (OPT) LVCMOS / LVTTL Input (See Table 3) ECL / LVPECL Output ECL / LVPECL Output Negative Power Supply I/O LVCMOS/LVTTL Input (See Table 3) ECL / LVPECL Input ECL / LVPECL Input Reference Voltage Output ECL / LVPECL or LVCMOS/LVTTL Input (see Table 3) Description Selectable Mode of Output Disabled Level Clock / Data Input Inverted Clock / Data Input Reference Voltage Output Output Enable Synchronous with D and D Adjust Standard VBB Levels Upward When Tied to VCC for 2.5 V Power Supply. Open for 3.3 V and 5 V Power Supply. Negative Power Supply Open or Tied to VEE (See Table 1) Optional 10mA Current Source For QHG and QHG Input LVEL Selector Pin for EN Inverted High-Gain Output, Gain > 200 High-Gain Output, Gain > 200 Selects Q and Q Current Source Magnitude (see Table 1), Open or Tied to VEE or VCC Positive Power Supply No Connect ECL/LVPECL Output for Feedback Loop Inverted ECL/LVPECL Output for Feedback Loop Exposed Pad on Package Bottom Should Only Be Connected to VEE or Left Open
*Pins will default LOW when left open. Pin will default HIGH when left open.
AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA
3
http://onsemi.com
NBLVEP16VR
APPLICATIONS INFORMATION The NBLVEP16VR is an ECL/LVPECL oscillator gain stage with high-gain output buffers, selectable output enable and a feedback buffer. The NBLVEP16VR is a solution for crystal oscillators and SAW-based voltage-controlled oscillators. Design versatility is enhanced with EN, a synchronous output enable pin to eliminate runt pulses; EN_SEL, an input state selector pin offering LVCMOS/LVTTL or ECL/LVPECL level control of EN; and OD_MODE, an output disable mode state pin which selects the polarity of the high-gain output's disabled state. The NBLVEP16VR Q and Q outputs are ideal for feedback applications common in crystal oscillator gain blocks. They each have a selectable on-chip pull-down current source. External resistors may be used to increase the pull-down current to a maximum of 25 mA. The QHG and QHG outputs each have an optional on-chip pull-down current source of 10 mA. When VEEP is left open, the 10 mA output current sources are disabled and the QHG and QHG outputs operate as standard ECL/LVPECL. When VEEP is connected to VEE, the 10 mA current sources are activated. The QHG and QHG pull-down current can be decreased by using a resistor connect from VEEP to VEE. See current source truth table for functions and options. The output enable input pin, EN, is synchronized with the D and D data input signals in a way that furnishes glitchless gating of the QHG and QHG outputs and allows continuous oscillator operation. For applications that require output enable control, the NBLVEP16VR provides expanded output enable selectability. The logic level of the input state selector pin, EN_SEL, will determine whether the EN pin accepts ECL/LVPECL or LVCMOS/LVTTL logic levels. The output disable mode state pin, OD_MODE, adds functional flexibility by giving the designer a choice of the QHG outputs' polarity when these high-gain outputs are disabled. For example, with OD_MODE LOW and EN LOW (LVPECL), the input is passed to the outputs and the data output equals the data input. If the D input is LOW when the EN goes HIGH, the next data transition to a HIGH is ignored and QHG remains LOW and QHG remains HIGH. The next positive transition of the data input is not passed on to the QHG outputs under these conditions. The QHG and QHG outputs remain in their disabled state as long as the EN input is held HIGH. The EN input has no influence on the Q or Q outputs and the data inputs are passed on to these outputs whether EN is HIGH or LOW. When the data input is HIGH and EN goes HIGH, it will force QHG LOW and QHG HIGH on the next negative transition of the D input. This configuration is ideal for crystal oscillator applications where the oscillator can be free-running and QHG/QHG gate on and off synchronously without adding extra counts to the output. See truth table and timing diagram for detailed ENable functions and options. The NBLVEP16VR provides a VBB and internal 470 W bias resistors from D to VBB and D to VBB for ac coupled single-ended or differential input signal(s). The VBB_ADJ pin is used for 2.5 V single-ended operation when it is connected to VCC. The VBB output current source/sink capability can support a robust 1.5 mA. For single-ended input conditions, the unused differential input is internally connected to VBB as a switching reference voltage. Decouple VBB and VCC with a 0.01 mF capacitor. This internal VBB will rebias AC coupled input(s). Inputs D or D must be signal driven or auto oscillation may result.
D D
(PECL) EN_SEL HIGH (OPEN) EN EN_SEL LOW (CMOS) (SHORTED TO VEE)
OD_MODE Q Q
QHG QHG
Figure 5. Timing Diagram
http://onsemi.com
4
NBLVEP16VR
ATTRIBUTES
Characteristics ESD Protection Human Body Model Machine Model Charged Device Model Value > 2 kV > 150 V > 1 kV Level 1 UL 94 V-0 @ 0.125 in
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
MAXIMUM RATINGS
Symbol VCC VEE VI IBB IIN Iout TA Tstg qJA qJC LVPECL Mode Power Supply NECL Mode Power Supply LVPECL Mode Input Voltage NECL Mode Input Voltage VBB Current Sink/Source Input Current (VIN - VBB) B 470 W Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) 0 LFPM 500 LFPM Standard Board D, D Continuous Surge Parameter Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Rating 6 -6 6 -6 $1.5 $5 50 100 -40 to +85 -65 to +150 Unit V V V V mA mA mA mA C C C/W C/W C/W
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum-rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions.
http://onsemi.com
5
NBLVEP16VR
DC CHARACTERISTICS, LVPECL VCC = 2.5 V, VEE = 0 V (Note 2, 6)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL NOTE: Characteristic Negative Power Supply Current (Note 3) Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input High Voltage (Single-Ended) (D, D, EN) (Notes 5, 6) Input Low Voltage (Single-Ended) (D, D, EN) (Notes 5, 6) Output Voltage Reference (Note 6) Input High Voltage Common Mode Range (Differential Configuration) Input HIGH Current (Note 5) Input LOW Current (Note 5) EN EN 0.5 Min 30 1340 620 1655 1050 1420 1.2 1525 Typ 35 Max 48 1670 950 2000 1395 1630 2.5 150 0.5 Min 30 1340 620 1655 1050 1420 1.2 1525 25C Typ 38 Max 48 1670 950 2000 1395 1630 2.5 150 0.5 Min 35 1340 620 1655 1050 1420 1.2 1525 85C Typ 40 Max 54 1670 950 2000 1395 1630 2.5 150 Unit mA mV mV mV mV mV V mA mA
2. 3. 4. 5. 6.
LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. Input and output parameters vary 1:1 with VCC. VEEP and CS_SEL open. QHG/QHG outputs loaded with 50 W to VCC - 2.0 V (VEEP = OPEN) Figure 11 or with optional current source (VEEP = VEE) Figure 12. Q/Q outputs loaded with 8 mA current source (CS_SEL = VEE). EN_SEL Open. VBB_ADJ tied to VCC for 2.5 V single-ended input operation.
DC CHARACTERISTICS, LVPECL VCC = 3.3 V, VEE = 0 V (Note 7)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL NOTE: Characteristic Negative Power Supply Current (Note 8) Output High Voltage (Note 9) Output Low Voltage (Note 9) Input High Voltage (Single-Ended) (D, D, EN) (Note 10) Input Low Voltage (Single-Ended) (D, D, EN) (Note 10) Output Voltage Reference Input High Voltage Common Mode Range (Differential Configuration) Input HIGH Current (Note 10) Input LOW Current (Note 10) EN EN 0.5 Min 30 2140 1420 2075 1355 1790 1.2 1900 Typ 38 Max 48 2470 1750 2420 1675 2030 3.3 150 0.5 Min 30 2140 1420 2075 1355 1790 1.2 1900 25C Typ 40 Max 48 2470 1750 2420 1675 2030 3.3 150 0.5 Min 35 2140 1420 2075 1355 1790 1.2 1900 85C Typ 42 Max 54 2470 1750 2420 1675 2030 3.3 150 Unit mA mV mV mV mV mV V mA mA
LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 7. Input and output parameters vary 1:1 with VCC. 8. VEEP and CS_SEL open. 9. QHG/QHG outputs loaded with 50 W to VCC - 2.0 V (VEEP = OPEN) Figure 11 or with optional current source (VEEP = VEE) Figure 12. Q/Q outputs loaded with 8 mA current source (CS_SEL = VEE). 10. EN_SEL Open.
http://onsemi.com
6
NBLVEP16VR
DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 11)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL NOTE: Characteristic Negative Power Supply Current (Note 12) Output High Voltage (Note 13) Output Low Voltage (Note 13) Input High Voltage (Single-Ended) (D, D, EN) (Note 14) Input Low Voltage (Single-Ended) (D, D, EN) (Note 14) Output Voltage Reference Input High Voltage Common Mode Range (Differential Configuration) Input HIGH Current (Note 14) Input LOW Current (Note 14) EN EN 0.5 Min 30 3840 3120 3775 3055 3490 2.0 3600 Typ 41 Max 48 4170 3450 4120 3375 3730 5.0 150 0.5 Min 30 3840 3120 3775 3055 3490 2.0 3600 25C Typ 43 Max 48 4170 3450 4120 3375 3730 5.0 150 0.5 Min 35 3840 3120 3775 3055 3490 2.0 3600 85C Typ 45 Max 54 4170 3450 4120 3375 3730 5.0 150 Unit mA mV mV mV mV mV V mA mA
LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 11. Input and output parameters vary 1:1 with VCC. 12. VEEP and CS_SEL open. 13. QHG/QHG outputs loaded with 50 W to VCC - 2.0 V (VEEP = OPEN) Figure 11 or with optional current source (VEEP = VEE) Figure 12. Q/Q outputs loaded with 8 mA current source (CS_SEL = VEE). 14. EN_SEL Open.
DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -5.5V to -2.375 V (Note 15)
-40C Symbol
IEE VOH VOL VIH
25C Max
48 -830 -1550
85C Max
48 -830 -1550
Characteristic
Negative Power Supply Current (Note 16) Output High Voltage (Note 17) Output Low Voltage (Note 17) Input High Voltage (Single-Ended) (D, D, EN) (Notes 18, 19) -3.3 V VBB_ADJ = OPEN -2.5 V VBB_ADJ = VCC Input Low Voltage (Single-Ended) (D, D, EN) (Notes 18, 19) -3.3 V VBB_ADJ = OPEN -2.5 V VBB_ADJ = VCC Output Voltage Reference -3.3 V or -5.2 V VBB_ADJ = OPEN -2.5 V (Note 19) VBB_ADJ = VCC Input High Voltage Common Mode Range (Differential Configuration) VEE v -5 V Input HIGH Current (Note 18) Input LOW Current (Note 18) EN EN
Min
30 -1160 -1880
Typ
38
Min
30 -1160 -1880
Typ
40
Min
35 -1160 -1880
Typ
42
Max
54 -830 -1550
Unit
mA mV mV mV
-1225 -845
-880 -500
-1225 -845
-880 -500
-1225 -845
-880 -500 mV
VIL
-1945 -1450 -1510 -1080 VEE+1.2 VEE+2.0 -1400 -975
-1625 -1105 -1270 -870 0
-1945 -1450 -1510 -1080 VEE+1.2 VEE+2.0 -1400 -975
-1625 -1105 -1270 -870 0
-1945 -1450 -1510 -1080 VEE+1.2 VEE+2.0 -1400 -975
-1625 -1105 mV -1270 -870 0 V V 150 mA mA
VBB
VIHCMR
IIH IIL
150
150
0.5
0.5
0.5
LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. Input and output parameters vary 1:1 with VCC. 16. VEEP and CS_SEL open. 17. QHG/QHG outputs loaded with 50 W to VCC - 2.0 V (VEEP = OPEN) Figure 11 or with optional current source (VEEP = VEE) Figure 12. Q/Q outputs loaded with 8 mA current source (CS_SEL = VEE). 18. EN_SEL Open. 19. VBB_ADJ tied to VCC for -2.5 V single-ended operation.
NOTE:
http://onsemi.com
7
NBLVEP16VR
(LVCMOS/LVTTL DC CHARACTERISTICS
VCC = 2.375 V or 5.0 V, VEE = 0 V or VCC = 0 V, VEE = -2.375 V to -5.5 V (Note 20) -40C Symbol VIH VIL IIH IIL Characteristic Input High Voltage Input Low Voltage Input HIGH Current Input LOW Current Min VEE+2.0 VEE -150 -150 Typ Max VCC VEE+0.8 150 150 Min VEE+ 2.0 VEE -150 -150 25C Typ Max VCC VEE+0.8 150 150 Min VEE+2.0 VEE -150 -150 85C Typ Max VCC VEE+0.8 150 150 Unit V V mA mA
20. EN_SEL = LOW When EN is Used as a LVCMOS/LVTTL Input.
AC CHARACTERISTICS VCC = 2.375 V to 5.5 V; VEE = 0 V or VCC = 0 V VEE = -2.375 V to -5.5 V (Note 21)
-40C Symbol VOUTPP Characteristic Differential Output (QHG) Voltage (Peak-to-Peak) fout < 1 GHz fout < 2 GHz fout < 2.5 GHz Min 500 260 210 215 155 315 320 0.5 1.0 0.5 5 D to QHG D to Q D to QHG 25 50 50 70 90 45 800 800 20 1200 1200 25 50 50 70 90 45 Typ 660 500 400 290 270 390 400 385 395 475 490 Max Min 500 310 210 215 165 335 335 0.5 1.0 0.5 5 800 800 20 1200 1200 25 50 50 70 90 45 25C Typ 700 500 380 300 280 410 415 385 405 495 505 Max Min 500 280 190 230 205 360 360 0.5 1.0 0.5 5 800 800 20 1200 1200 85C Typ 700 450 330 315 300 440 450 400 445 520 530 ns ns ps ps mV mV mV ps 120 150 50 300 210 55 120 150 50 300 210 55 120 150 50 300 210 55 % Max Unit mV mV ps
tPLH, tPHL
Propagation Delay (Differential) Figure 10 D to Q (CS_SEL = OPEN) Figure 10 D to Q (CS_SEL = VEE) Figure 8 D to QHG (VEEP Open) Figure 9 D to QHG (VEEP = VEE) Set-Up Time Hold Time Random Clock Jitter (RMS) Duty Cycle Skew (Note 23) Differential Input Voltage (Peak-to-Peak) (Note 22) Single-Ended Configuration EN to D EN to D
tS tH tJITTER tSKEW VINPP
tr tf DCO
Output Rise/Fall Times (20% - 80%) Q, Q (CS_SEL = VEE or OPEN) QHG, QHG (VEEP = VEE or OPEN) Output Duty Cycle (Note 24) (QHG)
21. QHG/QHG and Q/Q outputs loaded with AC coupled 50 W loads. VEEP and CS_SEL connected to VEE. 22. VINPP is the minimum differential Peak-to-Peak input swing for which AC parameters are guaranteed. 23. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs, (tpLH - tpHL). 24. Assumes 50% Input Duty Cycle, see Figures 11 or 12.
http://onsemi.com
8
NBLVEP16VR
Differential Inputs
900 800 VOUTpp (mV) 700 600 500 400 300 200 100 0 0 500 1000 1500 2000 2500 3000 FREQUENCY (MHz) 9 8 7 6 5 4 3 2 1 JITTEROUT ps (RMS)
Figure 6. Fmax/Jitter for QHG, QHG Output
800 700 600 QHG/QHG VOUTpp (mV) 500 400 300 200 100 0 50 40 VINPP (mV) 30 20
Figure 7. Differential Gain vs. Input Voltage (100 MHz)
http://onsemi.com
9
NBLVEP16VR
Zo = 50 W
QHG Driver QHG
D Receiver
Zo = 50 W 50 W 50 W
D
VEEP (OPEN)
VTT VTT = VCC - 2.0 V
Figure 8. Typical Termination for Output Driver VEEP Open (See Application Note AND8020 - Termination of ECL Logic Devices.)
QHG Driver QHG
Zo = 50 W *R Zo = 50 W
D Receiver D
*R = 2 Zo = 100 W for 50 W Transmission Lines VEEP VEE
Figure 9. QHG/QHG Output Loading and Termination, VEEP = VEE.
Q Driver Q
Zo = 50 W *R
D Receiver
Zo = 50 W
D *R = 2 Zo = 100 W for 50 W Transmission Lines
VEE VEE VEE CS_SEL (Open or Tied to VEE)
Figure 10. Q/Q Output Loading and Termination, CS_SEL Open or Tied to VEE or VCC
http://onsemi.com
10
NBLVEP16VR
QHG Driver QHG Zo = 50 W Zo = 50 W 50 W Oscilliscope 50 W
VEEP (OPEN)
Figure 11. QHG/QHG Device Evaluation Set-up; VEEP = OPEN
QHG Driver
Zo = 50 W 50 W Oscilliscope
QHG
Zo = 50 W 50 W
VEEP VEE
Figure 12. QHG/QHG Device Evaluation Set-up; VEEP = VEE
Q Driver Q
Zo = 50 W 50 W Zo = 50 W Oscilliscope 50 W
VEE VEE CS_SEL (Open or Tied to VEE) VEE
Figure 13. Q/Q Device Evaluation Set-up; CS_SEL = VEE or OPEN
http://onsemi.com
11
NBLVEP16VR
VR
4.0 mA ea. Q Q CS_SEL VEE
D D 470 W VBB VBB_ADJ OD_MODE VBB
1
Q Q 10 mA ea.
QHG QHG
0
VEEP
EN
LEN Q LATCH D EN_SEL
LVCMOS/LVTTL Threshold
Figure 14. Typical Application
The VCXO, or voltage controlled crystal oscillator, is an oscillator where the output frequency is controlled by the crystal and an external control voltage. The VCXO can have the output frequency change with a change in voltage at a control pin of the oscillator. Most, if not all, VCXO's use varactor diodes to vary the frequency. A varactor diode is a semiconductor device that behaves as a variable capacitor
when a voltage is applied to it. Thus, when a change in the control voltage is applied to the control pin of the oscillator, it causes a change in the capacitance seen by the crystal internal to the oscillator. These changes in the circuit load capacitance cause changes in the oscillator output frequency due to crystal loading.
http://onsemi.com
12
NBLVEP16VR
Resource Reference of Application Notes
AN1404 AN1406 AND8002 AND8009 AND8020 - - - - - ECLinPS Circuit Performance at Non-Standard VIH Levels Designing with LVPECL (ECL at +5.0 V) Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
http://onsemi.com
13
NBLVEP16VR
PACKAGE DIMENSIONS
QFN-16 CASE 485G-01 ISSUE A
-X- A M -Y-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 3.00 BSC 3.00 BSC 0.80 1.00 0.23 0.28 1.75 1.85 1.75 1.85 0.50 BSC 0.875 0.925 0.20 REF 0.00 0.05 0.35 0.45 1.50 BSC 1.50 BSC 0.875 0.925 0.60 0.80 INCHES MIN MAX 0.118 BSC 0.118 BSC 0.031 0.039 0.009 0.011 0.069 0.073 0.069 0.073 0.020 BSC 0.034 0.036 0.008 REF 0.000 0.002 0.014 0.018 0.059 BSC 0.059 BSC 0.034 0.036 0.024 0.031
B N 0.25 (0.010) T 0.25 (0.010) T J R 0.08 (0.003) T E H G
5 8
DIM A B C D E F G H J K L M N P R
C K -T-
SEATING PLANE
L
4
9
F
1 12
16
13
P
D
NOTE 3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
http://onsemi.com
14
NBLVEP16VR/D

▲Up To Search▲

Price & Availability of NBWLVEP16VR

	To Download NBWLVEP16VR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .