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PACVGA105 VGA Port Companion Circuit
Features
* 7 channels of ESD protection designed to meet IEC-1000-4-2 Level-4 ESD requirements (8kV contact discharge) Very low loading capacitance from ESD protection diodes at less than 5pF typical TTL to CMOS level-translating buffers for the HSYNC and VSYNC lines Three independent supply pins (VCC, VRGB and VAUX) to facilitate operation with sub-micron Graphics Controller ICs High impedance pull-ups (50k nominal to VAUX) for HSYNC and VSYNC inputs Pull-up resistors (1.8k nominal to VCC) for DDC_CLK and DDC_DATA lines Compact 16-pin QSOP package Lead-free version available
Product Description
The PACVGA105 incorporates 7 channels of ESD protection for signal lines commonly found in a VGA port for PCs. ESD protection is implemented with current steering diodes designed to safely handle the high peak surge currents associated with the IEC-1000-4-2 Level-4 ESD Protection Standard (8kV contact discharge). When the channels are subjected to an electrostatic discharge, the ESD current pulse is diverted via the protection diodes into the positive supply rails or ground where they may be safely dissipated. The upper ESD diodes for the R, G and B channels are connected to a separate supply rail (VRGB) to facilitate interfacing to graphics controller ICs with low voltage supplies. The remaining channels are connected to the main 5V rail (VCC). The lower diodes for the R, G and B channels are also connected to a dedicated ground pin (GNDA) to minimize crosstalk due to common ground impedance. Two non-inverting buffers are also included in this IC for buffering the HSYNC and VSYNC signals from the graphics controller IC. These buffers will accept TTL input levels and convert them to CMOS output levels that swing between GND and VCC. These drivers have a nominal 60 output impedance to match the characteristic impedance of the HSYNC and VSYNC lines of the video cables typically used. The inputs of these drivers also have high impedance pull-ups (50k nom.) pulling up to the VAUX rail. In addition, the DDC_CLOCK and DDC_DATA channels have 1.8k resistors pulling these inputs up to the main 5V (VCC) rail.
* * *
* * * *
Applications
* * * * ESD protection and termination resistors for VGA (video) port interfaces Desktop PCs Notebook computers LCD monitors
Simplified Electrical Schematic
VRGB
VCC
VAUX
1.8k
1.8k
50k
50k
R G B
DDC_CLK
VSYNC_OUT
GNDD
GNDA
DDC_DATA HSYNC VSYNC
HSYNC_OUT
(c) 2004 California Micro Devices Corp. All rights reserved. 01/28/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214
L Fax: 408.263.7846
L
www.calmicro.com
1
PACVGA105
PACKAGE / PINOUT DIAGRAM
Top View
HSYNC_OUT HSYNC GNDD VRGB B G R GNDA 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC VSYNC_OUT VSYNC VAUX DDC_CLK GNDD DDC_DATA VCC
16 Pin QSOP
Note: This drawing is not to scale.
PIN DESCRIPTIONS
LEAD(s) 1 2 3, 11 4 5 6 7 8 9, 16 NAME HSYNC_OUT HSYNC GNDD VRGB B G R GNDA VCC DESCRIPTION Horizontal sync signal buffer output. Connects to the video connector side of the horizontal sync line. Horizontal sync signal buffer input. Connects to the VGA Controller side of the horizontal sync line. Digital ground reference supply pin. VRGB supply pin. This is an isolated supply pin for the R, G and B ESD protection circuits. Blue signal video protection channel. This pin is typically tied to the B video line between the VGA controller device and the video connector. Green signal video protection channel. This pin is typically tied to the G video line between the VGA controller device and the video connector. Red signal video protection channel. This pin is typically tied to the R video line between the VGA controller device and the video connector. Analog ground reference supply pin. VCC supply pin. This is the main supply input for the DDC_CLK and DDC_DATA pullup resistors and ESD protection circuits. It is also connected to the sync buffers and to the ESD protection diodes present on the HSYNC_OUT and VSYNC_OUT lines. DDC data pin. DDC clock pin. VAUX supply pin. This is the supply input for the 50k pullups connected to the HSYNC and VSYNC buffer inputs. Vertical sync signal buffer input. Connects to the VGA Controller side of the vertical sync line. Vertical sync signal buffer output. Connects to the video connector side of the vertical sync line.
10 12 13 14 15
DDC_DATA DDC_CLK VAUX VSYNC VSYNC_OUT
(c) 2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214
L Fax: 408.263.7846
L
www.calmicro.com
01/28/04
PACVGA105
Ordering Information
PART NUMBERING INFORMATION
Standard Finish Pins 16 Package QSOP Ordering Part Number1 PACVGA105Q Part Marking PACVGA105Q Lead-free Finish Ordering Part Number1 PACVGA105QR Part Marking PACVGA105QR
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER VCC,VRGB,VAUX Supply Voltage Inputs Diode Forward Current (one diode conducting at a time) DC Voltage at Inputs R, G, B HSYNC, VSYNC DDC_CLK, DDC_DATA Operating Temperature Range Storage Temperature Range Package Power Rating RATING [GND - 0.5] to +6.0 20 [GND - 0.5] to [VRGB + 0.5] [GND - 0.5] to [VAUX + 0.5] [GND - 0.5] to [VCC + 0.5] 0 to +70 -40 to +150 750 UNITS V mA V V V C C mW
STANDARD OPERATING CONDITIONS
SYMBOL VCC VRGB VAUX VIH VIL VI PARAMETER Main Supply Voltage RGB Supply Voltage Auxiliary Supply Voltage Logic High Input Voltage (Note 1) Logic Low Input Voltage (Note 1) Input Voltage RGB HSYNC, VSYNC DDC_CLK, DDC_DATA High Level Output Current (Note 1) Low Level Output Current (Note 1) Free-air Operating Temperature
Note 1: These parameters apply only to the HSYNC and VSYNC signals.
MIN 4.5 1.7 2.9 2.0
MAX 5.5 3.7 3.7
UNITS V V V V
0.8 0 0 0 VRGB VAUX VCC -8 8 0 +70
V V V V mA mA C
IOH IOL TA
(c) 2004 California Micro Devices Corp. All rights reserved. 01/28/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L Tel: 408.263.3214
L
Fax: 408.263.7846
L
www.calmicro.com
3
PACVGA105
Specifications (cont'd)
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
SYMBOL VF VOH VOL IIN PARAMETER Diode Forward Voltage Logic High Output Voltage Logic Low Output Voltage Input Current R, G and B pins HSYNC, VSYNC pins HSYNC, VSYNC pins VCC Supply Current VRGB Supply Current Input Capacitance R, G and B pins HSYNC, VSYNC pins DDC_DATA, DDC_CLK pins Pull-up Resistance DDC_DATA, DDC_CLK pins ESD Withstand Voltage SYNC Buffer L => H Propagation Delay SYNC Buffer H => L Propagation Delay SYNC Buffer Output Rise & Fall Times VCC = 5V; VRGB = 3.3V; VAUX = 3.3V; Note 3 CL = 50pF; VCC = 5.0V; RL = 500; Note 4 CL = 50pF; VCC = 5.0V; RL = 500; Note 4 CL = 50pF; VCC = 5.0V; RL = 500; Note 4 CONDITIONS IF = 10mA IOH = -4mA, VCC = 4.5V IOL = 4mA, VCC = 4.5V VRGB = 3.63V, VIN = VRGB or GND VAUX = 3.63V, VIN = VAUX VAUX = 3.63V, VIN = GND VCC = 5.5V; VAUX = VRGB = 2.97V; All inputs and outputs floating R, G and B pins at VCC or GND; All inputs and outputs floating Note 2 applies for all cases 5 10 5 1.62 8 7.0 7.0 7.0 15.0 15.0 1.8 1.98 pF pF pF k kV ns ns ns 4.0 0.4 +1 +1 -95 100 10 MIN TYP MAX 1.0 UNITS V V V A A A A A
-30
-72.5 35
ICC IRGB CIN
RPU VESD tPLH tPHL tR, tF
Note 1: All parameters specified over standard operating conditions unless otherwise noted. Note 2: Measured at 1MHz. R/G/B inputs biased at 1.65V with VRGB = 3.3V. DDC_CLK and DDC_DATA biased at 2.5V with V CC=5V. HSYNC and VSYNC inputs biased at VAUX or GND with VAUX = 3.3V and VCC = 5V. These parameters are guaranteed by design and characterization Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. VRGB and VCC must be bypassed to GND via a low impedance ground plane with a 0.2uF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: R, G, B, HSYNC_OUT, VSYNC_OUT, DDC_CLK and DDC_DATA. The HSYNC and VSYNC inputs are ESD protected to the industry standard 2kV per the Human Body Model (MIL-STD-883, Method 3015). Note 4: Applicable to the SYNC buffers only. Input signals swing between 0V and 3.0V, with rise and fall times 5ns. Guaranteed by correlation to buffer output drive currents.
(c) 2004 California Micro Devices Corp. All rights reserved.
4
430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214
L Fax: 408.263.7846
L
www.calmicro.com
01/28/04
PACVGA105
Application Information
To Video DAC VDD
0.2uF
5V
3.3V
0.2uF 4 9,16 13
VRGB
VCC
VAUX GNDA GNDD
8 3, 11
Video Controller
H-Sync V-Sync DDC_Data DDC_Clk Red Grn Blue
VF** VF** VF**
2 14 10 12
HSYNC VSYNC DDC_DATA DDC_CLK
PACVGA105
1
DIGITAL ANALOG GND GND
HSYNC_OUT VSYNC_OUT 15 SF** SF**
VF** - VIDEO EMI Filter SF** - SYNC EMI Filter
7 6 5
R G B
Video Connector
H-Sync V-Sync DDC_Data DDC_Clk Red Green Blue L
Figure 1. Typical Connection Diagram GNDA, the negative voltage rail for the R, G and B diodes is not connected internally to GNDD. GNDA should ideally be connected to the ground of the video DAC IC. This will prevent any ground bounce caused by digital signals from injecting noise onto the R, G and B signals. Analog GND and digital GND are typically connected on the printed circuit board.
(c) 2004 California Micro Devices Corp. All rights reserved. 01/28/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L Tel: 408.263.3214
L
Fax: 408.263.7846
www.calmicro.com
5
PACVGA105
Mechanical Details
QSOP Mechanical Specifications PACVGA105 devices are packaged in 16-pin QSOP packages. Dimensions are presented below. For complete information on the QSOP-16 package, see the California Micro Devices QSOP Package Information document. Mechanical Package Diagrams
TOP VIEW
D
16 15 14 13 12 11 10 9
PACKAGE DIMENSIONS
Package Pins Dimensions A A1 B C D E e H L # per tube # per tape and reel Millimeters Min 1.35 0.10 0.20 0.18 4.80 3.81 5.79 0.40 Max 1.75 0.25 0.30 0.25 5.00 3.98 6.19 1.27 Min 0.053 0.004 0.008 0.007 0.189 0.150 0.228 0.016 QSOP (JEDEC name is SSOP) 16 Inches Max 0.069 0.010 0.012 0.010 0.197 0.157 0.244 0.050
C
END VIEW SIDE VIEW 1 2 3 4 5 6 7 8
H
Pin 1 Marking
E
A
SEATING PLANE
A1 B e
0.64 BSC
0.025 BSC
100 pcs* 2500 pcs Controlling dimension: inches
L
* This is an approximate number which may vary.
Package Dimensions for QSOP-16
(c) 2004 California Micro Devices Corp. All rights reserved.
6
430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214
L Fax: 408.263.7846
L
www.calmicro.com
01/28/04

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