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PRELIMINARY
PDM31096
4 Megabit 3.3V Static RAM 512K x 8-Bit
Features
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Description
The PDM31096 is a high-performance CMOS static RAM organized as 524,288 x 8 bits. Writing is accomplished when the write enable (WE) and chip enable CE inputs are both LOW. Reading is accomplished when WE remains HIGH and CE and OE are both LOW. The PDM31096 operates from a single +3.3V power supply and all the inputs and outputs are fully TTLcompatible. The PDM31096 is available in a 36-pin 400-mil plastic SOJ package and a 44-pin plastic TSOP (II) package.
1 2 3 4 5 6
High-speed access times Com'l: 8, 10, 12, 15, and 20 ns Ind'l.: 12, 15 and 20 ns Low power operation - PDM31096SA Active: 300 mA (Max) Standby: 25mW Single +3.3V (0.3V) power supply TTL-compatible inputs and outputs Packages Plastic SOJ (400 mil) - SO Plastic TSOP (II) - T
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Functional Block Diagram
A0 * * * * * A18
7
Decoder * * * * * * Memory Matrix
8 9 10
Addresses
I/O 0 * * I/O 7
***** Input Data Control Column I/O
* *
11 12
1
CE WE OE
*
Rev. 2.4 - 5/27/98
PRELIMINARY
PDM31096
Pin Configuration TSOP (II)
NC NC A4 A3 A2 A1 A0 CE I/OO I/O1 Vcc Vss I/O2 I/O3 WE A18 A17 A16 A15 A14 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A5 A6 A7 A8 OE I/O7 I/O6 Vss Vcc I/O5 I/O4 A9 A10 A11 A12 A13 NC NC NC
A4 A3 A2 A1 A0 CE I/O0 I/O1 Vcc Vss I/O2 I/O3 WE A18 A17 A16 A15 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
SOJ Pin Description
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A5 A6 A7 A8 OE I/O7 I/O6 Vss Vcc I/O5 I/O4 A9 A10 A11 A12 A13 NC
Name A18-A0 I/O7-I/O0 OE WE CE NC VCC VSS
Description Address Inputs Data Inputs/Outputs Output Enable Input Write Enable Input Chip Enable Inputs No Connect Power (+3.3V) Ground
Truth Table(1)
OE X X L X H WE X X H L H CE H X L L L I/O Hi-Z Hi-Z DOUT DIN Hi-Z MODE Standby Standby Read Write Output Disable
NOTE: 1. H = VIH, L = VIL, X = DON'T CARE
Absolute Maximum Ratings (1)
Symbol VTERM TBIAS TSTG PT IOUT Tj Rating Terminal Voltage with Respect to VSS Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Maximum Junction Temperature (2) Com'l. -0.5 to +4.6 -55 to +125 -55 to +125 1.0 50 125 Ind. -0.5 to +4.6 -65 to +135 -65 to +150 1.0 50 145 Unit V C C W mA C
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Appropriate thermal calculations should be performed in all cases and specifically for those where the chosen package has a large thermal resistance (e.g., TSOP). The calculation should be of the form: Tj = Ta + P * ja where Ta is the ambient temperature, P is average operating power and ja the thermal resistance of the package. For this product, use the following ja value: SOJ: 59o C/W TSOP : TBD 2 Rev. 2.4 - 5/27/98
PRELIMINARY
PDM31096
DC Electrical Characteristics (VCC = 3.3V 0.3V)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Conditions VCC = Max., VIN = VSS to VCC VCC = Max., CE = VIH VOUT = VSS to VCC Min. -5 -5 Max. 5 5 Unit A A
1 2 3 4
VIL VIH VOL VOH
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 8 mA, VCC = Min. IOH = -4 mA, VCC = Min.
-0.3(1) 2.2 -- 2.4
0.8 Vcc+0.3 0.4 --
V V V V
NOTE:1.VIL(min) = -3.0V for pulse width less than 20 ns
Power Supply Characteristics
-8 Symbol Parameter ICC Operating Current CE = VIL f = fMAX = 1/tRC VCC = Max. IOUT = 0 mA ISB Standby Current CE = VIH f = fMAX = 1/tRC VCC = Max. ISB1 Full Standby Current CE VCC - 0.2V f=0 VCC = Max., VIN VCC - 0.2V or 0.2V 10 10 10 15 10 15 10 15 mA 50 45 40 45 35 40 30 35 mA Com'l. 230 -10 Com'l. 215 -12 -15 -20 Unit mA Com'l Ind. Com'l Ind. Com'l Ind. 200 220 160 200 120 160
5 6 7 8 9 10
NOTES: All values are maximum guaranteed values.
Capacitance(1) (TA = +25C, f = 1.0 MHz)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Max. 8 8 Unit pF pF
11 12
NOTE: 1. This parameter is determined by device characterization but is not production tested.
Rev. 2.4 - 5/27/98
3
PRELIMINARY
PDM31096
Recommended DC Operating Conditions
Symbol VCC VSS Industrial Commercial Parameter Supply Voltage Supply Voltage Ambient Temperature Ambient Temperature Min. 3.0 0 -40 -0 Typ. 3.3 0 25 25 Max. 3.6 0 85 70 Unit V V C C
AC Test Conditions
Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load VSS to 3.0V 2.5 ns 1.5V 1.5V See Figures 1 and 2
+3.3V 317 DOUT 351 30 pF DOUT 351
+3.3V 317
5 pF
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent (for tLZCE, tHZCE, tLZWE, tHZWE, tLZOE, tHZOE)
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Rev. 2.4 - 5/27/98
PRELIMINARY
PDM31096
Read Cycle No. 1(4, 5)
tRC
ADDR
1 2
DATA VALID
tAA tOH
DOUT
PREVIOUS DATA VALID
Read Cycle No. 2(2, 4, 6)
tRC
ADDR
3
tAA tACE
4 5
CE
tLZCE
OE
tHZCE
tLZOE
DOUT
tHZOE
DATA VALID
6 7 8
tAOE
AC Electrical Characteristics
Description READ Cycle READ cycle time Address access time Chip enable access time Output hold from address change Chip enable to output in low Z
(1,3) (1,2,3)
-8* Sym tRC tAA tACE tOH tLZCE tHZCE tAOE tLZOE tHZOE Min Max Min
-10* Max Min
-12 Max Min
-15 Max Min
-20 Max Units ns ns ns ns ns ns ns ns ns
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-- 20 20 -- -- 7 8 -- 7
8 -- -- 3 3 -- -- 0 --
-- 8 8 -- -- 4 4 -- 4
10 -- -- 3 3 -- -- 0 --
-- 10 10 -- -- 5 5 -- 4
12 -- -- 3 3 -- -- 0 --
-- 12 12 -- -- 6 6 -- 5
15 -- -- 3 3 -- -- 0 --
-- 15 15 -- -- 7 7 -- 6
20 -- -- 3 3 -- -- 0 --
10 11 12
5
Chip disable to output in high Z Output enable access time
Output Enable to output in low Z (1,3) Output disable to output in high Z
(1,3)
* Vcc = 3.3V +5%
Rev. 2.4 - 5/27/98
PRELIMINARY
PDM31096
Write Cycle No. 1 (Write Enable Controlled)
tWC
ADDR
tAW tCW
tAH
CE
tAS
WE
tWP
tDS
DIN
DATA VALID
tDH
tHZWE
DOUT
HIGH-Z
tLZWE
Write Cycle No. 2 (Write Enable Controlled)
tWC
ADDR
tAW tCW
tAH
CE
tAS
WE
tWP
tDS
DIN
DATA VALID
tDH
DOUT
HIGH-Z
NOTE: Output Enable (OE) is inactive (high)
6
Rev. 2.4 - 5/27/98
PRELIMINARY
PDM31096
Write Cycle No. 3 (Chip Enable Controlled)
tWC
ADDR
1
tAH
tAW tAS tCW
2
tWP
CE
3
tDH
WE
tDS
DIN
DATA VALID
4 5 6
DOUT
HIGH-Z
NOTE: Output Enable (OE) is inactive (high)
AC Electrical Characteristics
Description WRITE Cycle Sym
-8*
-10*
-12
-15
-20
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 8 8 8 0 0 7 5 0 0 -- -- -- -- -- -- -- -- -- -- 4 10 10 10 0 0 8 6 0 0 -- -- -- -- -- -- -- -- -- 5 12 10 10 0 0 8 7 0 0 -- -- -- -- -- -- -- -- -- -- 6 15 11 11 0 0 9 8 0 0 -- -- -- -- -- -- -- -- -- -- 7 20 13 13 0 0 10 9 0 0 -- -- -- -- -- -- -- -- -- -- 9 ns ns
ns
7 8 9 10 11 12
WRITE cycle time Chip enable to end of write
Address valid to end of write
tWC tCW
tAW
Address setup time Address hold from end of write
Write pulse width Data setup time Data hold time Write disable to output in low Z
(1,3) (1,3)
tAS tAH
tWP tDS tDH tLZWE tHZWE
ns ns
ns ns ns ns ns
Write enable to output in high Z
* VCC = 3.3V +5% NOTES: (For two previous Electrical Characteristics tables) 1. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured 200 mV from steady state voltage. 2. At any given temperature and voltage condition, tHZCE is less than tLZCE. 3. This parameter is sampled. 4. WE is high for a READ cycle. 5. The device is continuously selected. All the Chip Enables are held in their active state. 6. The address is valid prior to or coincident with the latest occuring Chip Enable.
Rev. 2.4 - 5/27/98
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