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PH4530L
N-channel TrenchMOSTM logic level FET
Rev. 02 -- 26 January 2005 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode field effect transistor in a plastic package using TrenchMOSTM technology.
1.2 Features
s Low thermal resistance s Logic level gate drive s SO8 equivalent area footprint s Low on-state resistance.
1.3 Applications
s DC-to-DC converters s Portable appliances s Switched-mode power supplies s Notebook computers.
1.4 Quick reference data
s VDS 30 V s Ptot 62.5 W s ID 80 A s RDSon 5.7 m.
2. Pinning information
Table 1: Pin 1,2,3 4 mb Discrete pinning Description source gate mounting base; connected to drain
mb
Simplified outline
Symbol
D
G
mbb076
S
1
2
3
4
Top view
SOT669 (LFPAK)
Philips Semiconductors
PH4530L
N-channel TrenchMOSTM logic level FET
3. Ordering information
Table 2: Ordering information Package Name PH4530L LFPAK Description plastic single-ended surface mounted package (LFPAK); 4 leads Version SOT669 Type number
4. Limiting values
Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tmb = 25 C peak source (diode forward) current Tmb = 25 C; pulsed; tp 10 s unclamped inductive load; ID = 36.2 A; tp = 0.24 ms; VDD 30 V; VGS = 10 V; starting Tj = 25 C Tmb = 25 C; VGS = 10 V; Figure 2 and 3 Tmb = 100 C; VGS = 10 V; Figure 2 Tmb = 25 C; pulsed; tp 10 s; Figure 3 Tmb = 25 C; Figure 1 Conditions 25 C Tj 150 C Min -55 -55 Max 30 20 80 240 50.7 62.5 +150 +150 52 150 130 Unit V V A A A W C C A A mJ
Source-drain diode
Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy
9397 750 14031
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 26 January 2005
2 of 12
Philips Semiconductors
PH4530L
N-channel TrenchMOSTM logic level FET
120 Pder (%) 80
03aa15
120 Ider (%)
03aa23
80
40
40
0 0 50 100 150 Tmb (C) 200
0 0 50 100 150 200 Tmb (C)
P tot P der = ---------------------- x 100% P
tot ( 25 C )
ID I der = ------------------- x 100% I
D ( 25 C )
Fig 1. Normalized total power dissipation as a function of mounting base temperature.
103 ID (A) 102
Fig 2. Normalized continuous drain current as a function of mounting base temperature.
003aaa525
Limit RDSon = VDS / ID tp = 10 s
100 s DC
10
1 ms 10 ms 100 ms
1 10-1
1
10 VDS (V)
102
Tmb = 25 C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 14031
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 26 January 2005
3 of 12
Philips Semiconductors
PH4530L
N-channel TrenchMOSTM logic level FET
5. Thermal characteristics
Table 4: Rth(j-mb) Thermal characteristics Conditions Min Typ Max 2 Unit K/W thermal resistance from junction to mounting base Figure 4 Symbol Parameter
5.1 Transient thermal impedance
003aaa526
10 Zth(j-mb) (K/W) 1 = 0.5 0.2 0.1 0.05 10-1 0.02 single pulse
tp T P
=
tp T
t
10-2 10-5
10-4
10-3
10-2
10-1
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 14031
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 26 January 2005
4 of 12
Philips Semiconductors
PH4530L
N-channel TrenchMOSTM logic level FET
6. Characteristics
Table 5: Characteristics Tj = 25 C unless otherwise specified. Symbol V(BR)DSS VGS(th) IDSS Parameter drain-source breakdown voltage gate-source threshold voltage drain-source leakage current Conditions ID = 250 A; VGS = 0 V ID = 1 mA; VDS = VGS; Figure 9 VDS = 30 V; VGS = 0 V Tj = 25 C Tj = 150 C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = 15 V; VDS = 0 V VGS = 10 V; ID = 15 A; Figure 7 and 8 Tj = 25 C Tj = 150 C VGS = 5 V; ID = 15 A; Figure 7 and 8 Dynamic characteristics Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VSD trr total gate charge gate-source charge gate-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain (diode forward) voltage IS = 15 A; VGS = 0 V; Figure 12 reverse recovery time IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V VDS = 10 V; ID = 25 A; VGS = 5 V; RG = 4.7 VGS = 0 V; VDS = 10 V; f = 1 MHz; Figure 11 ID = 25 A; VDS = 10 V; VGS = 5 V; Figure 13 23.5 5.8 6.5 769 304 22 40 48 18 0.85 38 1.2 nC nC nC pF pF pF ns ns ns ns V ns 4.8 8.2 5.8 5.7 9.7 7.2 m m m 0.06 2 1 500 100 A A nA Min 30 1 Typ 1.5 Max 2 Unit V V Static characteristics
1972 -
Source-drain diode
9397 750 14031
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 26 January 2005
5 of 12
Philips Semiconductors
PH4530L
N-channel TrenchMOSTM logic level FET
40 ID (A) 30
003aaa527
40 ID (A) 30
003aaa528
10 5
3
VGS (V) = 2.9
2.8
2.7 20 2.6 2.5 10 2.4 2.2 0 0 0.5 1 1.5 VDS (V) 2 0 0 1 2 10 20 Tj = 150 C
25 C
3
VGS (V)
4
Tj = 25 C
Tj = 25 C and 150 C; VDS > ID x RDSon
Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values.
20 RDSon (m) 15
003aaa529
Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values.
1.8
03al00
2.6
2.7
2.8
2.9
3
a
1.2
10
VGS (V) = 3.5
5
5 10
0.6
0 0 10 20 30 ID (A) 40
0 -60
0
60
120
Tj (C)
180
Tj = 25 C
R DSon a = ---------------------------R DSon ( 25 C ) Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature.
Fig 7. Drain-source on-state resistance as a function of drain current; typical values.
9397 750 14031
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 26 January 2005
6 of 12
Philips Semiconductors
PH4530L
N-channel TrenchMOSTM logic level FET
2.5 VGS(th) (V) 2 max
03aa33
10-1 ID (A) 10-2
03aa36
1.5
typ
10-3 min typ max
1
min
10-4
0.5
10-5
0 -60
10-6 0 60 120 Tj (C) 180 0 1 2 VGS (V) 3
ID = 1 mA; VDS = VGS
Tj = 25 C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of junction temperature.
104 C (pF)
Fig 10. Sub-threshold drain current as a function of gate-source voltage.
003aaa530
Ciss 103
Coss Crss
102 10-1
1
10
VDS (V)
102
VGS = 0 V; f = 1 MHz
Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values.
9397 750 14031
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 26 January 2005
7 of 12
Philips Semiconductors
PH4530L
N-channel TrenchMOSTM logic level FET
40 IS (A) 30
003aaa531
10 VGS (V) 8
003aaa532
6 20 150 C Tj = 25 C 2 4
10
0 0.2
0 0.4 0.6 0.8 VSD (V) 1 0 10 20 30 40 50 QG (nC)
Tj = 25 C and 150 C; VGS = 0 V
ID = 25 A; VDD = 10 V
Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values.
Fig 13. Gate-source voltage as a function of gate charge; typical values.
9397 750 14031
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 26 January 2005
8 of 12
Philips Semiconductors
PH4530L
N-channel TrenchMOSTM logic level FET
7. Package outline
Plastic single-ended surface mounted package (LFPAK); 4 leads SOT669
E b2 L1
A c2
A2
C E1 b3
mounting base D1 H D
b4
L2
1
e
2
3
b
1/2 e
4
wM A c X
A A1 C
(A 3)
detail X L yC 0 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A A1 A2 A3 b b2 b3 2.2 2.0 b4 0.9 0.7 c c2 D (1) D1(1) E(1) E1(1) max 5.0 4.8 3.3 3.1 e 1.27 H 6.2 5.8 L 0.85 0.40 L1 1.3 0.8 L2 1.3 0.8 w 0.25 y 0.1 8 0
1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62
0.25 0.30 4.10 4.20 0.19 0.24 3.80
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT669 REFERENCES IEC JEDEC MO-235 JEITA EUROPEAN PROJECTION ISSUE DATE 03-09-15 04-10-13
Fig 14. SOT669 (LFPAK) package outline.
9397 750 14031 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 26 January 2005
9 of 12
Philips Semiconductors
PH4530L
N-channel TrenchMOSTM logic level FET
8. Revision history
Table 6: Revision history Release date Data sheet Change status notice Doc. number 9397 750 14031 Supersedes PH4530L_1 Document ID PH4530L_2 Modifications:
20050126 Product data sheet
* * * *
Section 1.4 "Quick reference data" ID and RDSon values updated Table 3 "Limiting values" ID and IDM values updated Figure 3, Figure 6, Figure 11 and Figure 13 updated Table 5 "Characteristics" RDSon, Qg(tot), Qgs, Qgd, Ciss, Coss and Crss values updated. 9397 750 12813 -
PH4530L_1
20040304 Preliminary data sheet
9397 750 14031
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 26 January 2005
10 of 12
Philips Semiconductors
PH4530L
N-channel TrenchMOSTM logic level FET
9. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
10. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
12. Trademarks
TrenchMOS -- is a trademark of Koninklijke Philips Electronics N.V.
11. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
13. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 14031
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 -- 26 January 2005
11 of 12
Philips Semiconductors
PH4530L
N-channel TrenchMOSTM logic level FET
14. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 5.1 6 7 8 9 10 11 12 13 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information . . . . . . . . . . . . . . . . . . . . 11
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 26 January 2005 Document number: 9397 750 14031
Published in The Netherlands

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