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PI6C20800
1:8 Clock Driver for Intel PCI Express Chipsets
Features
* Eight Pairs of Differential Clocks * Low skew < 50ps * Low Cycle-to-cycle jitter < 50ps * Output Enable for all outputs * Outputs Tristate control via SMBus * Power Management Control * Programmable PLL Bandwidth * PLL or Fanout operation * 3.3V Operation * Packaging (Pb-Free & Green): -- 48-Pin SSOP (V) -- 48-Pin TSSOP (A)
Description
PI6C20800 is a high-speed, low-noise differential clock buffer designed to be a companion to PI6C410B. The device distributes the differential SRC clock from PI6C410B to eight differential pairs of clock outputs either with or without PLL. The input SRC clock can be divided by 2 when SRC_DIV# is LOW. The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When input of either SRC_STOP# or PWRDWN# is LOW, the output clocks are Tristated. When PWRDWN# is LOW, the SDA and SCLK inputs must be Tristated.
Block Diagram
Pin Configuration
SRC_DIV# VDD VSS SRC SRC# OE_0 OE_3 OUT0 OUT0# VSS VDD OUT1 OUT1# OE_1 OE_2 OUT2 OUT2# VSS VDD OUT3 OUT3# PLL/BYPASS# SCLK SDA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
OE_INV OE [0:7] SRC_STOP# PWRDWN# SCLK SDA
Output Control
OUT0 OUT0# OUT0 OUT1# OUT2 OUT2# OUT3 OUT3# OUT4 OUT4#
OUT5 OUT5#
SMBus Controller
PLL/BYPASS#
SRC_DIV#
SRC SRC#
PLL_BW#
PLL
DIV
OUT6 OUT6# OUT7 OUT7#
LOCK
VDD_A VSS_A IREF LOCK OE_7 OE_4 OUT7 OUT7# OE_INV VDD OUT6 OUT6# OE_6 OE_5 OUT5 OUT5# VSS VDD OUT4 OUT4# PLL_BW# SRC_STOP PWRDWN# VSS
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PI6C20800 1:8 Clock Driver for Intel PCI Express Chipsets Pin Descriptions
Pin Name SRC_DIV# SRC & SRC# OE [0:7] Type Input Input Input Pin # 1 4, 5 6, 7, 14, 15, 35, 36, 43, 44 40 8, 9, 12, 13, 16 17, 20, 21, 29, 30, 33, 34, 37, 38, 41, 42 22 23 24 46 27 28 26 45 2, 11, 19, 31, 39 3, 10, 18, 25, 32 47 48 Descriptions 3.3V LVTTL input for selecting input frequency divide by 2, active LOW. 0.7V Differential SRC input from PI6C410 clock synthesizer 3.3V LVTTL input for enabling outputs, active HIGH. 3.3V LVTTL input for inverting the OE, SRC_STOP# and PWRDWN# pins. When 0 = same stage When 1 = OE[0:7], SRC_STOP#, PWRDWN# inverted. 0.7V Differential outputs 3.3V LVTTL input for selecting fan-out of PLL operation. SMBus compatible SCLOCK input SMBus compatible SDATA External resistor connection to set the differential output current 3.3V LVTTL input for SRC stop, active LOW 3.3V LVTTL input for selecting the PLL bandwidth 3.3V LVTTL input for Power Down operation, active LOW 3.3V LVTTL output, transition high when PLL lock is achieved (Latched output) 3.3V Power Supply for Outputs Ground for Outputs Ground for PLL 3.3V Power Supply for PLL
OE_INV
Input
OUT[0:7] & OUT[0:7]# PLL/BYPASS# SCLK SDA IREF SRC_STOP# PLL_BW# PWRDWN# LOCK VDD VSS VSS_A VDD_A
Output Input Input I/O Input Input Input Input Output Power Ground Ground Power
Serial Data Interface (SMBus)
PI6C20800 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below.
Address assignment
A6 1 A5 1 A4 0 A3 1 A2 1 A1 1 A0 0 R/W 0/1
Data Protocol(1)
1 bit Start bit 7 bits Slave Addr 1 R/W 1 Ack 8 bits Register offset 1 Ack 8 bits Byte Count =N 1 Ack 8 bits Data Byte 0 1 Ack 8 bits Data Byte N -1 1 Ack 1 bit Stop bit
Note: 1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
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PI6C20800 1:8 Clock Driver for Intel PCI Express Chipsets Data Byte 0: Control Register
Bit 0 Descriptions SRC_DIV# 0 = Divide by 2 1 = Normal PLL/BYPASS# 0 = Fanout 1 = PLL PLL Bandwidth 0 = HIGH Bandwidth, 1 = LOW Bandwidth TBD TBD TBD SRC_STOP# 0 = Driven when stopped 1 = Tristate PWRDWN# 0 = Driven when stopped 1 = Tristate RW 0 = Driven when stopped OUT[0:7], OUT[0:7]# Type RW Power Up Condition 1 = x1 Output(s) Affected OUT[0:7], OUT[0:7]# Pin NA
1
RW
1 = PLL
OUT[0:7], OUT[0:7]#
NA
2 3 4 5 6
RW
1 = Low
OUT[0:7], OUT[0:7]#
NA NA NA NA
7
RW
0 = Driven when stopped
OUT[0:7], OUT[0:7]#
NA
Data Byte 1: Control Register
Bit 0 1 2 3 4 5 6 7 OUTPUTS enable 1 = Enabled 0 = Disabled Descriptions Type RW RW RW RW RW RW RW RW Power Up Condition 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled Output(s) Affected OUT0, OUT0# OUT1, OUT1# OUT2, OUT2# OUT3, OUT3# OUT4, OUT4# OUT5, OUT5# OUT6, OUT6# OUT7, OUT7# Pin NA NA NA NA NA NA NA NA
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PI6C20800 1:8 Clock Driver for Intel PCI Express Chipsets Data Byte 2: Control Register
Bit 0 1 2 3 4 5 6 7 Allow control of OUTPUTS with assertion of SRC_STOP# 0 = Free running 1 = Stopped with SRC_Stop# Descriptions Type RW RW RW RW RW RW RW RW Power Up Condition 0 = Free running 0 = Free running 0 = Free running 0 = Free running 0 = Free running 0 = Free running 0 = Free running 0 = Free running Output(s) Affected OUT0, OUT0# OUT1, OUT1# OUT2, OUT2# OUT3, OUT3# OUT4, OUT4# OUT5, OUT5# OUT6, OUT6# OUT7, OUT7# Pin NA NA NA NA NA NA NA NA
Data Byte 3: Control Register
Bit 0 1 2 3 4 5 6 7 TBD Descriptions Type RW RW RW RW RW RW RW RW Power Up Condition Output(s) Affected Pin
Data Byte 4: Pericom ID Register
Bit 0 1 2 3 4 5 6 7 Pericom ID Descriptions Type R R R R R R R R Power Up Condition 0 0 0 0 0 1 0 0 Output(s) Affected NA NA NA NA NA NA NA NA Pin NA NA NA NA NA NA NA NA
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PI6C20800 1:8 Clock Driver for Intel PCI Express Chipsets Functionality
PWRDWN# 1 0 OUT Normal IREF x 2 or Float OUT# Normal LOW SRC_Stop# 1 0 OUT Normal IREF x 6 or Float OUT# Normal LOW
Power Down (PWRDWN# assertion)
PWRDWN#
OUT OUT#
Figure 1. Power down sequence
Power Down (PWRDWN# De-assertion)
Tstable <1ms PWRDWN# OUT
OUT# Tdrive_PwrDwn# <300us, >200mV
Figure 2. Power down de-assert sequence
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PI6C20800 1:8 Clock Driver for Intel PCI Express Chipsets Current-mode output buffer characteristics of OUT[0:7], OUT[0:7]#
VDD (3.3V 5%)
Slope ~ 1/Rs RO IOUT ROS Iout VOUT = 0.85V max 0V 0.85V
Figure 9. Simplified diagram of current-mode output buffer
Differential Clock Buffer characteristics
Symbol RO ROS VOUT Minimum 3000 unspecified N/A Maximum N/A unspecified 850mV
Current Accuracy
Symbol IOUT Conditions VDD = 3.30 5% Configuration RREF = 475 1% IREF = 2.32mA Load Nominal test load for given configuration Min. -12% INOMINAL Max. +12% INOMINAL
Note: 1. INOMINAL refers to the expected current based on the configuration of the device.
Differential Clock Output Current
Board Target Trace/Term Z 100 (100 differential 15% coupling ratio) Reference R, Iref = VDD/(3xRr) RREF = 475 1%, IREF = 2.32mA Output Current IOH = 6 x IREF VOH @ Z 0.7V @ 50
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PI6C20800 1:8 Clock Driver for Intel PCI Express Chipsets Absolute Maximum Ratings(1) (Over operating free-air temperature range)
Symbol VDD_A VDD VIH VIL Ts VESD 3.3V Core Supply Voltage 3.3V I/O Supply Voltage Input HIGH Voltage Input LOW Voltage Storage Temperature ESD Protection -0.5 -65 2000 150 C V Parameters Min. -0.5 -0.5 Max. 4.6 4.6 4.6 V Units
Note: 1. Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
DC Electrical Characteristics (VDD = 3.35%, VDD_A = 3.35%)
Symbol VDD_A VDD VIH VIL IIK VOH VOL IOH CIN COUT LPIN IDD ISS ISS TA Parameters 3.3V Core Supply Voltage 3.3V I/O Supply Voltage 3.3V Input HIGH Voltage 3.3V Input LOW Voltage Input Leakage Current 3.3V Output HIGH Voltage 3.3V Output LOW Voltage Output HIGH Current Logic Input Pin Capacitance Output Pin Capacitance Pin Inductance Power Supply Current Power Down Current Power Down Current Ambient Temperature VDD = 3.465V, FCPU = 200MHz Driven outputs Tristate outputs 0 0 < VIN < VDD IOH = -1mA IOL = 1mA IOH = 6 x IREF, IREF = 2.32mA 12.2 15.6 1.5 5 6 7 250 60 12 70 C mA VDD Condition Min. 3.135 3.135 2.0 VSS - 0.3 -5 2.4 0.4 Max. 3.465 3.465 VDD + 0.3 0.8 +5 A V mA pF nH V Units
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PI6C20800 1:8 Clock Driver for Intel PCI Express Chipsets AC Switching Characteristics(1,2,3) (VDD = 3.35%, VDD_A = 3.35%)
Symbol Trise / Tfall Trise / Tfall Tskew VHIGH VOVS VUDS VLOW Vcross Vcross TDC Tjcyc-cyc Parameters Rise and Fall Time (measured between 0.175V to 0.525V) Rise and Fall Time Variation Output-to-Output Skew Voltage HIGH Max. Voltage Min. Voltage Voltage LOW Absolute crossing poing voltages Total Variation of Vcross over all edges Duty Cycle Jitter, Cycle-to-cycle (PLL Mode, Measurement for differential waveform) Jitter, Cycle-to-cycle (BYPASS mode as additive jitter) 45 -300 -150 250 +150 550 140 55 50 % ps 660 Min 175 Max. 700 125 50 850 1150 mV 2 2 2 3 ps ps Units Notes 2 2 3 2
Notes: 1. Test configuration is RS = 33.2, Rp = 49.9, and 2pF. 2. Measurement taken from Single Ended waveform. 3. Measurement taken from Differential waveform.
Configuration Test Load Board Termination
Rs 33 5% TLA PI6C20800 Rs 33 5% TLB 475 1% Rp 49.9 1% Rp 49.9 1% 2pF 5% 2pF 5% OUT# OUT
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PI6C20800 1:8 Clock Driver for Intel PCI Express Chipsets Packaging Mechanical: 48-Pin SSOP (V)
48
.291 .299 7.39 7.59
.395 .420 10.03 10.67
Gauge Plane
.010 0.25
1
.02 0.51 .04 1.01
.620 .630 15.75 16.00
.008 0.20 Nom.
.015 0.381 x 45 .025 0.635
.110 2.79 Max
.025 BSC 0.635
.008 0.20 .0135 0.34
0-8
.008 0.20 .016 0.40
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
Packaging Mechanical: 48-Pin TSSOP (A)
48
.236 .244
6.0 6.2
1
.488 12.4 .496 12.6
.047 1.20 Max
SEATING PLANE
.004 0.09 .008 0.20
X.XX X.XX
DENOTES DIMENSIONS IN MILLIMETERS
.0197 BSC 0.50
.007 .010
0.17 0.27
.002 .006 0.05 0.15
0.45 .018 0.75 .030
.319 BSC 8.1
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PI6C20800 1:8 Clock Driver for Intel PCI Express Chipsets Ordering Information(1,2)
Ordering Code PI6C20800VE PI6C20800AE Package Code VE AE Package Description 48-pin, 300-mil wide, SSOP, Pb-Free and Green 48-pin, 240-mil wide, TSSOP, Pb-Free and Green
Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
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