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Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
DESCRIPTION
The new PLC42VA12 CMOS PLD from Philips Semiconductors exhibits a unique combination of the two architectural concepts that revolutionized the PLD marketplace. The Philips Semiconductors unique Output Macro Cell (OMC) embodies all the advantages and none of the disadvantages associated with the "V" type Output Macro Cell devices. This new design, combined with added functionality of two programmable arrays, represents a significant advancement in the configurability and efficiency of multi-function PLDs. The most significant improvement in the Output Macro Cell structure is the implementation of the register bypass function. Any of the 10 J-K/D registers can be individually bypassed, thus creating a combinatorial I/O path from the AND array to the output pin. Unlike other "V" type devices, the register in the PLC42VA12 Macro Cell remains fully functional as a buried register. Both the combinatorial I/O and buried register have separate input paths (from the AND array). In most V-type architectures, the register is lost as a resource when the cell is configured as a combinatorial I/O. This feature provides the capability to operate the buried register independently from the combinatorial I/O. The PLC42VA12 is an EPROM-based CMOS device. Designs can be generated using Philips Semiconductors SNAP PLD design software packages or one of several other commercially available JEDEC standard PLD design software packages.
FEATURES
* High-speed EPROM-based CMOS
Multi-Function PLD - Super set of 22V10, 32VX10 and 20RA10 PAL(R) ICs
PIN CONFIGURATIONS
FA and N Packages
I0/CLK I1 I2 I3 I4 I5 I6 I7 I8 1 2 3 4 5 6 7 8 9 24 VCC 23 M9 22 M8 21 M7 20 M6 19 M5 18 M4 17 M3 16 M2 15 M1 14 M0 13 I9/OE
* Two fully programmable arrays eliminate
"P-term Depletion" - Up to 64 P-terms per OR function
* Improved Output Macro Cell Structure
- Individually programmable as: * Registered Output with feedback * Registered Input * Combinatorial I/O with Buried Register * Dedicated I/O with feedback * Dedicated Input (combinatorial) - Bypassed Registers are 100% functional with separate input and feedback paths - Individual Output Enable control functions * From pin or AND array
B0 10 B1 11 GND 12
* Reprogrammable - 100% tested for
programmability
N = Plastic DIP (300mil-wide) FA = Ceramic DIP with Quartz Window (300mil-wide)
* Eleven clock sources * Register Preload and Diagnostic Test Mode
Features
A Package
I2 4 I0/ I1 CLK N/C VCC M9 M8 3 2 1 28 27 26 25 M7 24 M6 23 M5 22 N/C 21 M4 20 M3 19 M2 12 13 14 15 16 17 18
* Security fuse
APPLICATIONS
- Synchronous - Asynchronous
I3 I4 I5 N/C I6 5 6 7 8 9
* Mealy or Moore State Machines * Multiple, independent State Machines * 10-bit ripple cascade * Sequence recognition * Bus Protocol generation * Industrial control * A/D Scanning
I7 10 I8 11
B0 B1 GND N/C I9/ M0 M1 OE A = Plastic Leaded Chip Carrier (450mil-square)
ORDERING INFORMATION
DESCRIPTION 24-Pin Ceramic Dual In-Line with window, Reprogrammable (300mil-wide) 24-Pin Plastic Dual In-Line, One Time Programmable (300mil-wide) 28-Pin Plastic Leaded Chip Carrier, One Time Programmable (450mil-wide) ORDER CODE PLC42VA12FA PLC42VA12N PLC42VA12A DRAWING NUMBER 1478A 0410D 0401F
PAL is a registered trademark of Advanced Micro Devices, Inc.
October 22, 1993
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853-1414 11164
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
LOGIC DIAGRAM
63 I1 I2 I3 I4 I5 I6 I7 I8 2 3 4 5 6 7 8 9 56 55 48 47 40 39 32 31 24 23 16 15 87 0 FC RRRR C P MMMM K A8 7 6 5 8
PR J CK KQ
PR J CK KQ
PR J CK KQ
PR J CK KQ
NOTE: Programmable Connection
October 22, 1993
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Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
LOGIC DIAGRAM (Continued)
CCC KKK L 765 A RRRR C P MMMM K B4 3 2 1 4 CCC KKK L 321 B PRPR C MMMM K 9900 9 C L L DDDD DDDD K M MMMMM MMMM 0 9 01234 5678 DD MM 09 DD 10 13 I9/OE
I0/CLK 1
CK
22 M8
CK
21 M7
CK
20 M6
CK
19 M5
PR J CK KQ
CK
18 M4
PR J CK KQ CK
17 M3
PR J CK KQ CK
16 M2
PR J CK KQ CK
15 M1
PR J CK KQ CK
23 M9
PR J CK KQ CK
14 M0 11 B1 10 B0
October 22, 1993
75
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
FUNCTIONAL DIAGRAM
P63 I1 - I8 P0 FC Ln Pn Rn CKn LMn PMn RMn CKn DMn DMn DBn
I9/OE
X8 I0/CLK
X1
X2
X2
X8
X8
X2
X2
X2
X2
X8
X2
X2
CLK CONTROL P J X8 X8 K Q OMC CONFIG. OEn X8 R CK En (X2)
X8
POLARITY
X8 M1 - M8 CLK CONTROL P J X2 X2 K Q OMC CONFIG. OEn R CK En (X2) X2
X2
M0, M9 POLARITY X2
B0 - B1 POLARITY X2
October 22, 1993
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Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
ABSOLUTE MAXIMUM RATINGS1
SYMBOL VCC VIN VOUT IIN IOUT Tamb Tstg PARAMETER Supply voltage Input voltage Output voltage Input currents Output currents Operating temperature range Storage temperature range RATINGS -0.5 to +7 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -10 to +10 +24 0 to +75 -65 to +150 UNIT VDC VDC VDC mA mA C C
PLC42VA12
THERMAL RATINGS
TEMPERATURE Maximum junction Maximum ambient Allowable thermal rise ambient to junction 150C 75C 75C
NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
AC TEST CONDITIONS
VCC +5V S1
VOLTAGE WAVEFORMS
+3.0V 90%
C1
C2 In OE MZ
R1 0V 5ns R2 CL +3.0V tR tF 5ns
10%
INPUTS
In BM BM CK
DUT
90%
10% GND MZ 0V OUTPUTS 5ns 5ns
NOTE: C1 and C2 are to bypass VCC to GND.
MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
Test Load Circuit
Input Pulses
October 22, 1993
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Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
DC ELECTRICAL CHARACTERISTICS
0C Tamb +75C, 4.75V VCC 5.25V LIMITS SYMBOL Input voltage2 VIL VIH VOL VOH IIL IIH Low High Low High Low High VCC = MIN VCC = MAX VCC = MIN; IOL = 16mA VCC = MIN; IOH = -3.2mA VIN = GND VIN = VCC VOUT = VCC VOUT = GND VOUT = GND IOUT = 0mA, f = 15MHz6, VCC = MAX IOUT = 0mA, f = 15MHz6, VCC = MAX VCC = 5V; VIN = 2.0V 90 70 12 15 2.4 -0.3 2.0 0.3 4.3 -1 +1 -10 10 10 -10 -130 120 100 0.8 VCC + 0.3 0.5 V V V V A A A A mA mA mA pF pF PARAMETER TEST CONDITION MIN TYP1 MAX UNIT
Output voltage2
Input current
Output current IO(OFF) IOS ICC1 ICC2 Capacitance CI Input CB I/O VB = 2.0V NOTES: 1. All typical values are at VCC = 5V. Tamb = +25C. 2. All voltage values are with respect to network ground terminal. 3. Duration of short-circuit should not exceed one second. Test one at a time. 4. Tested with VIL = 0.45V, VIH = 2.4V. 5. Tested with VIL = 0V, VIH = VCC. 6. Refer to Figure 1, ICC vs Frequency (worst case). (Referenced from 15MHz) The ICC increases by 1.5mA per MHz for the frequency range of 16MHz up to 25MHz. The ICC remains at a worst case for the frequency range of 26MHz up to 37MHz. The ICC decreases by 1.0mA per MHz for the frequency range of 14MHz down to 1MHz. The worst case ICC is calculated as follows: - All dedicated inputs are switching. - All OMCs are configured as JK flip-flops in the toggle mode. . .all are toggling. - All 12 outputs are disabled. - The number of product terms connected does not impact the ICC. 7. Refer to Figure 2 for tPD vs output capacitance loading.
+30 +25 +20 I CC(mA) +15 +10 +5 0 -5 -10 -15 1 5 10 15 20 f(MHz) 25 30 35 40 t PD(ns) 3 2 1 0 -1 -2 6 5 4
Hi-Z state Short-circuit3,7 VCC supply current (Active)4 VCC supply current (Active)5
1 -1
0
20
40
60
80 100 120 140 160 180 200
OUTPUT CAPACITANCE LOADING (pF)
Figure 1. ICC vs Frequency (Worst Case) (Referenced from 15MHz)
Figure 2. tPD vs Output Capacitance Loading (Typical)
October 22, 1993
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Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
AC ELECTRICAL CHARACTERISTICS
0C Tamb +75C, 4.75V VCC 5.25V; R1 = 238, R2 = 170 TEST2 SYMBOL Set-up Time tIS1 tIS2 tIS3
3
PLC42VA12 MIN TYP1 MAX UNIT
PARAMETER
FROM
TO
CONDITION (CL (pF)) 50 50 50 50 50 50
Input; dedicated clock Input; P-term clock Preload; dedicated clock Preload; P-term clock Input through complement array; dedicated clock Input through complement array; P-term clock Propagation Delay Propagation Delay with complement array (2 passes) Clock to Output; Dedicated clock Clock to output; P-term clock Registered operating period; Dedicated clock (tIS1 + tCKO1) Registered operating period; P-term clock (tIS2 + tCKO2) Register preload operating period; Dedicated clock (tIS3 + tCKO1) Register preload operating period; P-term clock (tIS4 + tCKO2) Registered operating period with complement array; dedicated clock (tIS5 + tCKO1) Registered operating period with complement array; P-term clock (tIS6 + tCKO2) Output Enable; from /OE pin4 Output Enable; from P-term4 Output Disable; from /OE pin4 Output Disable; from P-term4 Preset to Output Power-on Reset (Mn = 1) Input (Dedicated clock) Input (P-term clock) Input; from Mn (Dedicated clock) Input; from Mn (P-term clock) Clock High; Dedicated clock Clock Low; Dedicated clock Clock High; P-term clock Clock Low; P-term clock
3
(I, B, M) +/- (I, B, M) +/- (M) +/- (M) +/- (I, B, M) +/- (I, B, M) +/-
CK+ (I, B, M) +/- CK+ (I, B, M) +/- CK+ (I, B, M) +/-
23 20 10 2 50 40
16 13 3.5 -1.0 34 30
ns ns ns ns ns ns
tIS43 tIS53 tIS63
Propagation Delay tPD1 tPD2 tCKO1 tCKO2 tRP1 tRP2 tRP33 tRP43 tRP53 (I, B, M) +/- (I, B,) +/- CK+ (I, B, M) +/- (I, B, M) +/- (I, B, M) +/- (M) +/- (M) +/- (I, B, M) +/- (I, B, M) +/- (I, B, M) +/- (M) +/- (M) +/- (M) +/- (M) +/- (M) +/- (M) +/- (M) +/- 50 50 50 50 50 50 50 50 50 20 36 13 18 29 31 16.5 17 47 35 55 17 27 40 47 27 29 67 ns ns ns ns ns ns ns ns ns
tRP63 tOE1 tOE2 tOD1 tOD2 tPRO3 tPPR3 Hold Time tIH1 tIH2 tIH33 tIH4
(I, B, M) +/- /OE - (I, B, M) +/- /OE + (I, B, M) +/- (I, B, M) +/- VCC + CK+ (I, B, M) +/- CK+ (I, B, M) +/- CK+ CK- CK+ CK- (I, B, M) +/-
(M) +/- (M) +/- (B, M) +/- Outputs disabled Outputs disabled (M) +/- (M) +/- (I, B, M) +/- (I, B, M) +/- (M) +/- (M) +/- CK- CK+ CK- CK+ (I, B, M) +/-
50 50 50 5 5 50 50 50 50 50 50 50 50 50 50 50 0 5 5 10 10 10 15 15 30
48 10 12.5 10 14.5 25
67 20 25 20 25 35 15
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-13 -7.5 -1.5 3.5 5 5 7 7 7
Pulse Width tCKH1 tCKL1 tCKH2 tCKL2
tPRH3 Width of preset/reset input pulse Notes on page 80.
October 22, 1993
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Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
AC ELECTRICAL CHARACTERISTICS (Continued)
0C Tamb +75C, 4.75V VCC 5.25V; R1 = 238, R2 = 170 TEST2 SYMBOL PARAMETER FROM TO CONDITION (CL (pF)) 50 50 50 50 50 MIN PLC42VA12 TYP1 MAX UNIT
Frequency of Operation fCK1 fCK2 fMAX1 fMAX2 fMAX33 Dedicated clock frequency P-term clock frequency Registered operating frequency; Dedicated clock (tIS1 + tCKO1) Registered operating frequency; P-term clock (tIS2 + tCKO2) Register preload operating frequency; Dedicated clock (tIS3 + tCKO1) Register preload operating frequency; P-term clock (tIS4 + tCKO2) Registered operating frequency with complement array; Dedicated clock (tIS5 + tCKO1) Registered operating frequency with complement array; P-term clock (tIS6 + tCKO2) C+ C+ (I, B, M) +/- (I, B, M) +/- (M) +/- C+ C+ (M) +/- (M) +/- (M) +/- 50 33 25 21.3 37 100 71.4 34.5 32.3 60.6 MHz MHz MHz MHz MHz
fMAX43
(M) +/-
(M) +/-
50
34.5
58.8
MHz
fMAX53
(I, B, M) +/-
(M) +/-
50
14.9
21.3
MHz
fMAX63
(I, B, M) +/-
(M) +/-
50
14.9
20.8
MHz
NOTES: 1. All typical values are at VCC = 5V, Tamb = +25C. These limits are not tested/guaranteed. 2. Refer also to AC Test Conditions (Test Load Circuit). 3. These limits are not tested, but are characterized periodically and are guaranteed by design. 4. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH - 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed.
BLOCK DIAGRAM
I1 65 X 105 PROGRAMMABLE AND ARRAY
64 LOGIC TERMS
41 CONTROL TERMS
I8
CK COMPLEMENT MUX 64 X 32 PROGRAMMABLE OR ARRAY JK/D JP RLD OMC (10) K BYPASS OE Q Q MUX M0 - M9 MUX I0/CLK I9/OE
B0 - B1
October 22, 1993
80
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
OUTPUT MACRO CELL (OMC)
FROM AND ARRAY FC CONTROL LOAD PRESET RESET CK OE O E
FROM OR ARRAY JK/D MUX
P J
R CK
CLOCK 0 SELECT MUX 1
0 1 OUTPUT ENABLE SELECT MUX
CLK
FROM OR ARRAY TO AND ARRAY
K
Q
1
M
M
OUTPUT SELECT MUX (REGISTER BYPASS)
FROM OR ARRAY
TO AND ARRAY
Output Macro Cell Configuration
Philips Semiconductors unique Output Macro Cell design represents a significant advancement in the configurability of multi-function Programmable Logic Devices. The PLC42VA12 has 10 programmable Output Macro Cells. Each can be individually programmed in any of 5 basic configurations: * Dedicated I/O (combinatorial) with feedback to AND array
These 14 configurations, combined with the fully programmable OR array, make the PLC42VA12 the most versatile and silicon efficient of all the Output Macro Cell-type PLDs. The most significant Output Macro Cell (OMC) feature is the implementation of the register bypass function. Any of the 10 J-K/D registers can be individually bypassed, thus creating a combinatorial I/O path from the AND array to the output pin. Unlike other Output Macro Cell-type devices, the register in the OMC is fully functional as a buried register. Furthermore, both the combinatorial I/O and the buried register have separate input paths (from the AND array) and separate feedback paths (to the AND array). This feature provides the capability to operate the buried register independently from the combinatorial I/O. The PLC42VA12 is ideally suited for both synchronous and asynchronous logic functions. Eleven clock sources - 10 driven from the AND array and one from an external
source - make it possible to design synchronous state machine functions, event-driven state machine functions and combinatorial (asynchronous) functions all on the same chip. Sophisticated control functions support individual OE control and Reset functions from the AND array. OE control is also available from the I9/OE pin. Register Preset and Load functions are controlled from the AND array, in 2 banks of 4 for OMCs M1 - M8. Output Macro Cells M0 and M9 have individual Preset and Load Control terms. Output Polarity for the combinatorial I/O paths is configurable via 12 programmable EX-OR gates. The output of each register can be configured as inverting (active Low) or non-inverting (active High) via manipulation of the logic equations. The output of each buried register can also be configured as inverting or non-inverting via the input buffer which feeds back to the AND array.
* * * *
Dedicated Input Combinatorial I/O with feedback and Buried Register with feedback (register bypass) Registered Input Registered Output with feedback
Each of the registered options can be further customized as J-K type or D-type, with either an internally derived clock (from the AND array) or clocked from an external source. With these additional programmable options, it is possible to program each Output Macro Cell in any one of 14 different configurations.
October 22, 1993
81
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
OUTPUT MACRO CELL PROGRAMMABLE OPTIONS
OMC Programmable Options
For purposes of programming, the Output Macro Cell should be considered to be partitioned into five separate blocks. As shown in the drawing titled "Output Macro Cell Programmable Options", the programmable blocks are: Register Select Options, Polarity Options, Clock Options, OMC Configuration Options and Output Enable Control Options.
OUTPUT M
OUTPUT MACRO CELL REGISTER SELECT OPTIONS CLOCK OPTIONS
OMC CONFIGURATION OPTIONS
OUTPUT ENABLE CONTROL OPTIONS
POLARITY OPTIONS
There is one programmable location associated with each block except the Output Enable Control block which has two programmable fuse locations per OMC. The following drawings detail the options associated with each programmable block. The associated programming codes are also included. The table titled "Output Macro Cell Configurations" (page 87) lists all the possible combinations of the five programmable options.
ARCHITECTURAL OPTIONS REGISTER SELECT OPTIONS
P R
Register Select Options
Each OMC Register can be configured either as a dedicated D-type or a J-K flip-flop. The Flip-Flop Control term, Fc, provides the option to control each Register dynamically--switching from D-type to J-K type, based on the Fc control signal. Register Preset and Reset are controlled from the AND array. Each OMC has an individual Reset Control term (RMn). The Register Preset function is controlled in two banks of 4 for OMCs M1 - M3 and M4 - M8 (via the control terms PA and PB). OMCs M0 and M9 have individual control terms (PM0 and PM9 respectively).
P FROM OR ARRAY D
R CK
CLOCK OPTIONS
Q FROM AND ARRAY
OMC CONFIG. OPTIONS
OUTPUT CONTROL OPTIONS
REGISTER MODE (D or JK) D-TYPE FC CONTROL P-TERM
CODE A L
P
R
P J FROM OR ARRAY K
R CK
CLOCK OPTIONS
Q
OMC CONFIG. OPTIONS
OUTPUT CONTROL OPTIONS
FROM AND ARRAY
REGISTER MODE (D or JK) JK-TYPE FC CONTROL P-TERM
CODE
*
-
Notes on page 87.
October 22, 1993
82
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
REGISTER SELECT OPTIONS (Continued)
P R FC P R
P FROM OR ARRAY D
R CK
CLOCK OPTIONS FROM OR ARRAY
P J
R CK
CLOCK OPTIONS
Q FROM AND ARRAY
OMC CONFIG. OPTIONS
OUTPUT CONTROL OPTIONS
K
Q
OMC CONFIG. OPTIONS
OUTPUT CONTROL OPTIONS
FROM AND ARRAY REGISTER MODE (D or JK) DYNAMICALLY CONTROLLABLE FC = LOW FC = HIGH FC CONTROL P-TERM CODE A L or H
POLARITY OPTIONS (for Combinatorial I/O Configurations Only1)
FROM OR ARRAY OMC CONFIG. OPTIONS OUTPUT SELECT OPTIONS M
Polarity Options
When an OMC is configured as a Combinatorial I/O with Buried Register, the polarity of the combinatorial path can be programmed as Active-High or Active-Low. A configurable EX-OR gate provides polarity control. If an OMC is configured as a Registered Output, /Q is propagated to the output pin. Note that either Q or /Q can be fedback to the AND array by manipulating the feedback logic equations. (TRUE or COMPLEMENT).
POLARITY ACTIVE-HIGH (NON-INVERTING)
CODE H4
FROM OR ARRAY
OMC CONFIG. OPTIONS
OUTPUT CONTROL OPTIONS
M
POLARITY ACTIVE-LOW (INVERTING)
CODE L4
CLOCK OPTIONS
REGISTER SELECT OPTIONS CLK OPTIONS EXTERNAL CLOCK (FROM PIN 1) CODE A
Clock Options
In the unprogrammed state, all Output Macro Cell clock sources are connected to the External Clock pin (I0/CLK pin 1). Each OMC can be individually programmed such that its P-term Clock (CKn) is enabled, thus disabling it from the External Clock and providing event-driven clocking capability. This feature supports multiple state machines, clocked at several different rates, all on one chip, or the ability to collect large amounts of random logic, including 10 separately clocked flip-flops.
CODE
D (OR J) CK FROM OR ARRAY (K) TO AND ARRAY Q
CLK
OMC CONFIG. OPTIONS
OUTPUT CONTROL OPTIONS
REGISTER SELECT OPTIONS
CK
CLK OPTIONS P-TERM CLOCK
*
D (OR J) CK FROM OR ARRAY (K) TO AND ARRAY Q OMC CONFIG. OPTIONS OUTPUT CONTROL OPTIONS
Notes on page 87. 83
October 22, 1993
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
OUTPUT MACRO CELL CONFIGURATION OPTIONS
REGISTER SELECT OPTIONS
REGISTER SELECT OPTIONS FROM OR ARRAY D (OR J) CK FROM OR ARRAY (K) TO AND ARRAY Q OMC CONFIG. OPTIONS M CLOCK OPTIONS TO AND ARRAY
D (OR J) CK
CLOCK OPTIONS
(K)
Q
COMBINATORIAL OPTIONS FROM OR ARRAY OUTPUT CONTROL OPTIONS M
OMC CONFIGURATION OMC CONFIGURATION REGISTERED OUTPUT (D or JK) CODE A COMBINATORIAL OUTPUT WITH BURIED REGISTER (D or JK)
CODE
*
L
OMC Configuration Options
Each OMC can be configured as a Registered Output with feedback, a Registered Input or a Combinatorial I/O with Buried Register. Dedicated Input and dedicated I/O configurations are also possible. When the Combinatorial I/O option is selected, (the Register Bypass option), the Buried Register remains 100% functional, with its own inputs from the AND array and a separate feedback path. This unique feature is ideal for designing any type of state machine; synchronous Mealy-types that require both Buried and Output Registers, or asynchronous Mealy-types that require buried registers and combinatorial output functions. Both synchronous and asynchronous Moore-type state machines can also be easily accommodated with the flexible OMC structure. Note that an OMC can be configured as either a Combinatorial I/O (with Buried Register) or a Registered Output with feedback and it can still be used as a Registered Input. By disabling the outputs via any OE control function, the M pin can be used as an input. When the Load Control P-term is asserted HIGH, the register is preloaded from the M pin(s). When the LC P-term is Active-Low and the output is enabled, the OMC will again function as configured (either a combinatorial I/O or a registered output with feedback). This feature is suited for synchronizing input signals prior to commencing a state sequence.
M CLOCK OPTIONS
D
CK
Q TO AND ARRAY
OUTPUT CONTROL OPTIONS
OMC CONFIGURATION REGISTERED INPUT LOAD CONTROL P-TERM
CODE A or
*5
H6
Notes on page 87.
October 22, 1993
84
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
OUTPUT CONTROL OPTIONS
OE
Output Enable Control Options
Similar to the Clock Options, the Output Enable Control for each OMC can be connected either to an external source (I9/OE, pin 13) or controlled from the AND array (P-terms DMn). Each Output can also be permanently enabled. Output Enable control for the two bi-directional I/O (B pins 10 and 11) is from the AND array only (P-terms DB0 and DB1 respectively).
OMC CONFIG. OPTIONS
M
TO AND ARRAY CODE A CODE A
OE CONTROL FUSE FROM OE PIN
En FUSE FROM OE PIN
DM
OMC CONFIG. OPTIONS TO AND ARRAY OE FUSE FROM P-TERM CONTROL CODE En FUSE FROM P-TERM CONTROL
OMC CONFIG. OPTIONS M TO AND ARRAY
M
CODE A or 0
OE CONTROL FUSE ALWAYS ENABLED
CODE A
*
En FUSE ALWAYS ENABLED
CODE 0
COMPLEMENT ARRAY DETAIL
Complement Array Detail
The complement array is a special sequencer feature that is often used for detecting illegal states. It is also ideal for generating IF-THEN-ELSE logic statements with a minimum number of product terms. The concept is deceptively simple. If you subscribe to the theory that the expressions (/A * /B * /C) and (A + B + C) are equivalent, you will begin to see the value of this single term NOR array. The complement array is a single OR gate with inputs from the AND array. The output of the complement array is inverted and fedback to the AND array (NOR function). The output of the array will be LOW if any one or more of the AND terms connected to it are active (HIGH). If, however, all the connected terms are inactive (LOW), which is a classic unknown state, the output of the complement array will be HIGH. Consider the product terms A, B and D that represent defined states. They are also connected to the input of the complement array. When the condition (not A and not B and not D) exists, the Complement Array will detect this and propagate an Active-High signal to the AND array. This signal can be connected to product term E, which could be used in turn to preset the state machine to known state. Without the complement array, one would have to generate product terms for all unknown or illegal states. With very complex state machines, such an approach can be prohibitive, both in terms of time and wasted resources.
P63
P62
P61
P1
P0
FC
LMn
PMn
RMn
C0
A
B
D
E
C0
TO OR ARRAY
TO OMCs AND BIDIRECTIONAL I/O
Notes on page 87.
October 22, 1993
85
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
LOGIC PROGRAMMING
The PLC42VA12 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABELTM and CUPLTM design software packages also support the PLC42VA12 architecture. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format.
PLC42VA12 logic designs can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SNAP only. To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below. Symbols for OMC
configuration have been previously defined in the Architectural Options section.
PROGRAMMING AND SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this data handbook for additional information.
LOGIC IMPLEMENTATION "AND" ARRAY - (I), (B), (Qp)
I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q
(T, FC, L, P, R, D)n STATE INACTIVE1 CODE O STATE I, B, Q
(T, FC, L, P, R, D)n CODE H STATE I, B, Q
(T, FC, L, P, R, D)n CODE L STATE DON'T CARE
(T, FC, L, P, R, D)n CODE -
"COMPLEMENT" ARRAY - (C)
C C C C
C (Tn, FC) ACTION INACTIVE1, 3 CODE O ACTION GENERATE (Tn, FC) CODE A
C (Tn, FC) ACTION PROPAGATE CODE
C (Tn, FC) ACTION TRANSPARENT CODE -
C
*
"OR" ARRAY - (J-K Type)
Tn J M = DISABLED K CODE O Q M = DISABLED K CODE H Tn J Q M = DISABLED K CODE L Tn J Q M = DISABLED K CODE - Tn J Q
ACTION TOGGLE
ACTION SET
ACTION RESET
ACTION HOLD
"OR" ARRAY
Tn P, R, L (OR B) Tn P, R, L (OR B)
"OR" ARRAY - (D-Type)
Tn J M = ENABLED K Q M = ENABLED K Tn STATUS INACTIVE (RESET) CODE Tn J Q
Tn STATUS ACTIVE1
CODE A
Tn STATUS INACTIVE
CODE
*
Tn STATUS ACTIVE (SET)
CODE A
*
Notes on page 87.
ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc.
October 22, 1993
86
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
LOGIC IMPLEMENTATION (Continued) OUTPUT MACRO CELL CONFIGURATIONS
PROGRAMMING CODES OUTPUT MACRO CELL CONFIGURATION REGISTER SELECT FUSE OMC CONFIGURATION FUSE POLARITY FUSE CLOCK FUSE
Combinatorial I/O with Buried D-type register External clock source P-term clock source Combinatorial I/O with Buried J-K type register External clock source P-term clock source Registered Output (D-type) with feedback External clock source P-term clock source Registered Output (J-K type) with feedback External clock source P-term clock source A A A A N/A N/A A A A
* * * *
H or L H or L
A
*
A
* *
H or L H or L
*
*
A
* *
A A
A A A or *5 A or
N/A N/A
*
A
Registered Input (Clocked Preload) with feedback External clock source P-term clock source Optional5 Optional5
*5
*
OUTPUT CONTROL FUSES OUTPUT ENABLE CONTROL8 CONFIGURATION OMC controlled by /OE pin Output Enabled Output Disabled OMC controlled by P-term Output Enabled Output Disabled Output always Enabled OE CONTROL FUSE A En FUSES A Low High CONTROL SIGNAL
*
A or 0 High Low
A
0
Not Applicable
NOTES: 1. This is the initial (unprogrammed) state of the device. 2. Any gate will be unconditionally inhibited if both the TRUE and COMPLEMENT fuses are left intact. 3. To prevent oscillations, this state is not allowed for Complement Array fuse pairs that are coupled to active product terms. 4. The OMC Configuration fuse must be programmed as Combinatorial I/O in order to make use of the Polarity Option. 5. Regardless of the programmed state of the OMC Configuration fuse, an OMC can be used as a Registered Input. Note that the Load Control P-term must be asserted Active-High. 6. Output must be disabled. 7. Program code definitions: A = Active (unprogrammed fuse) 0, * = Inactive (programmed fuse) - = Don't Care (both TRUE and COMPLEMENT fuses unprogrammed) H = Active-High connection L = Active-Low connection 8. OE control for B0 and B1 (Pins 10 and 11) is from the AND array only.
October 22, 1993
87
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
TIMING DIAGRAMS
+3V I, B, M (INPUTS) 1.5V 1.5V 0V tIH2 P-TERM CK (I, B, M) tIS2,6 M (OUTPUTS) tCKO2 tRP2,6 I, B, M, OE TERM OR OE PIN (OUTPUT ENABLE) 1.5V tOE1,2 1.5V tIS2,6 +3V 1.5V 1.5V 0V tCKH2 1.5V tOD1,2 tCKL2 VOH VT VOL
TIMING DEFINITIONS
SYMBOL PARAMETER fCK1 fCK2 tCKH1 tCKH2 tCKL1 tCKL2 tCKO1
+3V 1.5V 0V
Clock Frequency; External Clock Clock Frequency; P-term Clock Width of Input Clock Pulse; External Clock Width of Input Clock Pulse; P-term Clock Interval between Clock pulses; External Clock Interval between Clock Pulses; P-term Clock Delay between the Positive Transition of External Clock and when M Outputs become valid. Delay between the Positive Transition of P-term Clock and when M Outputs become valid. Delay between beginning of Valid Input and when the M outputs become Valid when using External Clock. Delay between beginning of Valid Input and when the M outputs become Valid when using P-term Clock. Delay between beginning of Valid Input and when the M outputs become Valid when using Preload Inputs (from M pins) and External Clock. Delay between beginning of Valid Input and when the M outputs become valid when using Preload inputs (from M pins) and P-term Clock. Delay between beginning of Valid Input and when the M outputs become Valid when using Complement Array and External clock. Delay between beginning of Valid Input and when the M outputs become Valid when using Complement Array and P-term Clock. Minimum guaranteed Operating Frequency; Dedicated Clock Minimum guaranteed Operating Frequency; P-term Clock Minimum guaranteed Operating Frequency using Preload; Dedicated Clock (M pin to M pin) Minimum guaranteed Operating Frequency using Preload; P-term Clock (M pin to M pin) Minimum guaranteed Operating Frequency using Complement Array; Dedicated Clock Minimum Operating Frequency using Complement Array; P-term Clock Required delay between positive transition of External Clock and end of valid input data.
tCKO2
Flip-Flop Outputs with P-term Clock
tRP1
tRP2
+3V I, B, M (INPUTS) 1.5V 1.5V 0V tIH1 EXTERNAL CK 1.5V tIS1,5 +3V 1.5V 1.5V 0V tIS1,5 M (OUTPUTS) tCKO1 tRP1,5 I, B, M, OE TERM OR OE PIN (OUTPUT ENABLE) 1.5V tOE1,2 tCKH1 1.5V tOD1,2 tCKL1 VOH VT VOL +3V 1.5V 0V
tRP3
tRP4
tRP5
tRP6 Flip-Flop Outputs with External Clock fMAX1 fMAX2
+3V I, B (INPUTS) 1.5V
fMAX3
0V
B, M (COMBINATORIAL OUTPUTS)
I, B, M, OE TERM OR OE PIN (OUTPUT ENABLE)
October 22, 1993
CCCC CCCC CCCC CCCC
tPD tOE2 +1.5V
VOH 1.5V VT VOL tOD2 +3V +1.5V 0V
fMAX4
fMAX5
fMAX6
Gated Outputs
tIH1
88
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
TIMING DIAGRAMS (Continued)
I, B (LOAD SELECT) +3V 1.5V 1.5V 0V +3V 1.5V 1.5V 0V tOE1,2 L
TIMING DEFINITIONS (Continued)
SYMBOL PARAMETER tIH2 Required delay between positive transition of P-term Clock and end of valid input data. Required delay between positive transition of External Clock and end of valid input data when using Preload Inputs (from M pins). Required delay between positive transition of P-term Clock and end of valid input data when using Preload Inputs (from M pins). Required delay between beginning of valid input and positive transition of External Clock. Required delay between beginning of valid input and positive transition of P-term Clock input. Required delay between beginning of valid Preload input (from M pins) and positive transition of External Clock. Required delay between beginning of valid Preload input (from M pins) and positive transition of P-term Clock input. Required delay between beginning of valid input through Complement Array and positive transition of External Clock. Required delay between beginning of valid input through Complement Array and positive transition of P-term Clock input. Delay between beginning of Output Enable signal (Low) from /OE pin and when Outputs become valid. Delay between beginning of Output Enable signal (High or Low) from OE P-term and when Outputs become valid. Delay between beginning of Output Enable signal (HIGH) from /OE pin and when Outputs become disabled. Delay between beginning of Output Enable signal (High or Low) from OE P-term and when Outputs become disabled. Delay between beginning of valid input and when the Outputs become valid (Combinatorial Path). Width of Preset/Reset Pulse. Delay between beginning of valid Preset/Reset Input and when the registered Outputs become Preset ("1") or Reset ("0"). Delay between VCC (after power-up) and when flip-flops become Reset to "0". Note: Signal at Output (M pin) will be inverted.
I, B, OE TERM OR OE PIN (OUTPUT ENABLE)
tIH3
M (INPUT) tOD1,2 P-TERM OR EXTERNAL CK
+3V VT (FORCED DIN) tIS3,4 tIH3,4 1.5V 0V tCKL +3V 0V
tIH4
tIS1
Q
P-TERM OR EXTERNAL CK tIS* PRESET/RESET (I, B, M INPUTS) 1.5V
tPRH Q
tPRO M (OUTPUTS) 1.5V (RESET) (PRESET) 1.5V VOH VOL *Preset and Reset functions override Clock. However, M outputs may glitch with the first positive Clock Edge if tIS cannot be guaranteed by the user.
Asynchronous Preset/Reset tOD1
+5V 4.5V
M (OUTPUTS)
I, B, M (INPUTS)
P-TERM OR EXTERNAL CK tIS
October 22, 1993
CCCC CCCC CCCC CCCC
VCC
tPPR
1.5V tCKO1,2
1.5V tIH 1.5V tCKH
Power-On Reset
CCCC CCCC CCCC CCCC
1.5V tIS 1.5V (PRESET) (RESET) 1.5V 1.5V 1.5V tCK1,2
I, B, M (INPUTS)
CCCCCCCCCCC CCCCCCCCCCC CCCCCCCCCCC CCCCCCCCCCC
tCKH tIH3,4
tIS2
(DIN)
Flip-Flop Input Mode (Preload)
tIS3
+3V
tIS4
0V +3V 0V +3V 0V
1.5V tCKO
tIS5
tIS6
tOE1
tOE2
0V VOH VOL +3V 0V tIS +3V 1.5V 0V
tOD2
tPD tPRH tPRO
tCKL
tPPR
89
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
LOGIC FUNCTION
Q3 1 Q2 0 Q1 1 Q0 0 SR PRESENT STATE A B C ... Sn + 1 NEXT STATE
PLC42VA12 UNPROGRAMMED STATE
A factory shipped unprogrammed device is configured such that all cells are in a conductive state. The following are:
ERASURE CHARACTERISTICS (For Quartz Window Packages Only)
The erasure characteristics of the PLC42VA12 devices are such that erasure begins to occur upon exposure to light with wavelength shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000 - 4000A range. Data shows that constant exposure to room level fluorescent lighting could erase a typical PLC42VA12 in approximately three years, while it would take approximately one week to cause erasure when exposed to direct sunlight. If the PLC42VA12 is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be placed over the window to prevent unintentional erasure. The recommended erasure procedure for the PLC42VA12 is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity x exposure time) for erasure should be a minimum of 15Wsec/cm2. The erasure time with this dosage is approximately 30 to 35 minutes using an ultraviolet lamp with a 12,000W/cm2 power rating. The device should be placed within one inch of the lamp tubes during erasure. The maximum integrated dose a CMOS EPLD can be exposed to without damage is 7258Wsec/cm2 (1 week @ 12000W/cm2). Exposure of these CMOS EPLDs to high intensity UV light for longer periods may cause permanent damage. The maximum number of guaranteed erase/write cycles is 50. Data retentions exceeds 20 years.
STATE REGISTER 0 0 0 1
SET Q0: J0 = (Q2 Q1 Q0) A B C . . . K0 = 0 RESET Q1: J1 = 0 K1 = (Q3 Q2 Q1 Q0) A B C . . .

ACTIVE: - OR array logic terms - Output Macro Cells M1 - M8;
*
D-type registered outputs (D = 0)
HOLD Q2: J2 = 0 K2 = 0 RESET Q3: J3 = (Q3 Q2 Q1 Q0) A B C . . . K3 = (Q3 Q2 Q1 Q0) A B C . . .
- External clock path - Inputs: B0, B1, M0, M9 INACTIVE: - AND array logic and control terms (except flip-flop mode control term, FC) - Bidirectional I/O (B0, B1);

NOTE: Similar logic functions are applicable for D mode flip-flops.
* * *
Inputs are active. Outputs are 3-Stated via the OE P-terms, D0 and D1. D-type registers (D = 0).
- Output Macro Cells M0 and M9;
FLIP-FLOP TRUTH TABLE
OE H L L L L L L L H H +10V X X X L L L L H H X X X X X H L L L L L L L X X L H L L L L L L X X X X L L H H L H L X X X L H L H H L H L H L Q L H Q L H L Ln CKn Pn Rn J K Q M Hi-Z H L H Q H L Q H* L* H**
Bidirectional I/O, 3-Stated via the OE P-terms, DM0 and DM9. The inputs are active. - P-term clocks - Complement Array - J-K Flip-Flop mode
PROGRAMMING AND SOFTWARE SUPPORT
Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) in this data handbook for additional information.
X X X H L H L** NOTES: 1. Positive Logic: J-K = T0 + T1 + T2 + ... + T31 Tn = C (I0 I1 I2...) (Q0 Q1...) (B0 B1...) 2. denotes transition for Low to High level. 3. X = Don't care 4. * = Forced at Mn pin for loading the J-K flip-flop in the Input mode. The load control term, Ln must be enabled (HIGH) and the p-terms that are connected to the associated flip-flop must be forced LOW (disabled) during Preload. 5. At P = R = H, Q = H. The final state of Q depends on which is released first. 6. ** = Forced at Fn pin to load J/K flip-flop (Diagnostic mode).
October 22, 1993
90
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
PROGRAM TABLE
October 22, 1993
91
Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD (42 x 105 x 12)
PLC42VA12
SNAP RESOURCE SUMMARY DESIGNATIONS
P63 I1 - I8 DIN42 NIN42 X8 I0/CK P0 FC Ln Pn Rn CKn LMn PMn RMn CKn DMn DMn DBn
I9/OE
NOR X1
AND
ANDFC X2 X2 X8 X8 X2
CAND X2 X2 X2 X8 X2 X2
NTIM42 DTIM42 OR X8 P J X8 X8 OR K Q OMC CONFIG. OEBUFF OEn X8 OENAND R CK CLK CONTROL
CK42 En (X2)
JKFFPR42
POLARITY
X8 EXOR42 TNOO42 CLK CONTROL OR X2 P J X2 X2 OR K Q OMC CONFIG. OEBUFF M0, M9 POLARITY X2 EXOR42 TNOU42 B0 - B1 POLARITY X2 EXOR42 TNOU42 OEn R CK M1 - M8
CK42 En (X2) X2 OENAND
JKFFPR42
October 22, 1993
92

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