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Preliminary
PLL103-07
2 DIMM DDR Fanout Buffer
FEATURES
* * * * * * * * * * Generates 12-output buffers from one input. Supports VIA Pro266 DDR chipset. Supports up to 2 DDR DIMMS. Supports up to 400MHz DDR, SDRAMS. One additional output for feedback. 6 differential clock distribution. Less than 5ns delay. Skew between any outputs is less than 100 ps. 2.5V Supply range. Available in 28-pin SSOP.
PIN CONFIGURATION
FBOUT GND DDRT0 DDRC0 VDD2.5 GND DDRT1 DDRC1 VDD2.5 BUF_IN GND DDRT2 DDRC2 VDD2.5 DDR0T Note: #: Active Low 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND DDRT5 DDRC5 VDD2.5 GND DDRT4 DDRC4 VDD2.5 GND DDRT3 DDRC3 VDD2.5 SCLK SDATA
PLL103-07
BLOCK DIAGRAM
SDATA SCLK
I2C Control
DDR0C DDR1T DDR1C DDR2T DDR2C
DESCRIPTIONS
The PLL103-07 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 2 DDR DIMMs. The PLL103-07 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 266 chipset.
BUF_IN
DDR3T DDR3C DDR4T DDR4C DDR5T DDR5C FBOUT
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/03/01 Page 1
Preliminary
PLL103-07
2 DIMM DDR Fanout Buffer
PIN DESCRIPTIONS
Name
FBOUT BUF_IN DDRT[0:5] DDRC[0:5] VDD2.5 GND
Number
1 10 3,7,12,19, 23,27 4,8,13,18, 22,26 5,9,14, 17,21,25 6,11,20,24
Type
O I O O P P Feedback clock for chipset. Reference input from chipset.
Description
"True" clocks of differential pair outputs. "Complementary" clocks of differential pair outputs. 2.5V power supply. Ground.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/03/01 Page 2
Preliminary
PLL103-07
2 DIMM DDR Fanout Buffer
I2C BUS CONFIGURATION SETTING
Address Assignment Slave Receiver/Transmitter Data Transfer Rate A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W _
Provides both slave write and readback functionality Standard mode at 100kbits/s This serial protocol is designed to allow both blocks write and read from the controller. The bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will terminate the transfer. The write or read block both begins with the master sending a slave address and a write condition (0xD2) or a read condition (0xD3). Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at power-up is = (0x09).
Data Protocol
I2C CONTROL REGISTERS
1. BYTE 6: Outputs Register (1=Enable, 0=Disable) Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin#
27, 26 23, 22 19, 18
Default
1 0 0 0 1 1 1 1
Description
Reserved Reserved Reserved Reserved Reserved DDRT5, DDRC5 DDRT4, DDRC4 DDRT3, DDRC3
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/03/01 Page 3
Preliminary
PLL103-07
2 DIMM DDR Fanout Buffer
2. BYTE 7: Outputs Register (1=Enable, 0=Disable) Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin#
12, 13 7, 8 3, 4
Default
1 1 1 1 1 1 1 1
Description
Reserved Reserved Reserved DDRT2, DDRC2 Reserved DDRT1, DDRC1 Reserved DDRT0, DDRC0
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/03/01 Page 4
Preliminary
PLL103-07
2 DIMM DDR Fanout Buffer
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature ESD Voltage
SYMBOL
V DD VI VO TS TA
MIN.
V SS -0.5 V SS -0.5 V SS -0.5 -65 0
MAX.
7.0 V DD +0.5 V DD +0.5 150 70 2
UNITS
V V V C C KV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied.
2. Operating Conditions PARAMETERS
Supply Voltage Input Capacitance Output Capacitance
SYMBOL
V DD2.5 CIN COUT
MIN.
2.375
MAX.
2.625 5 6
UNITS
V pF pF
3. Electrical Specifications PARAMETERS
Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage Output High Current Output Low Current
Note: TBM: To be measured
SYMBOL
V IH V IL I IH I IL V OH V OL I OH I OL
CONDITIONS
All Inputs except I2C All inputs except I2C V IN = V DD V IN = 0 IOL = -12mA, IOL = 12mA, VDD = 2.375V VDD = 2.375V
MIN.
2.0 VSS-0.3
TYP.
MAX.
VDD+0.3 0.8 TBM TBM
UNITS
V V uA uA V
1.7 0.6 -18 26 -32 35
V mA mA
VDD = 2.375V, VOUT=1V VDD = 2.375V, VOUT=1.2V
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/03/01 Page 5
Preliminary
PLL103-07
2 DIMM DDR Fanout Buffer
3. Electrical Specifications (Continued) PARAMETERS
Supply Current (DDR-only mode) Supply Current (SDRAM mode) Supply Current Output Crossing Voltage Output Voltage Swing Duty Cycle Max. Operating Frequency Rising Edge Rate Falling Edge Rate DDR Rising Edge Rate DDR Falling Edge Rate Clock Skew(pin to pin) Stabilization Time
Note: TBM: To be measured
SYMBOL
IDD IDD IDDS VOC VOUT DT
CONDITIONS
Unloaded outputs, 133MHz Unloaded outputs, 133MHz PD = 0
MIN.
TYP.
MAX.
TBM TBM TBM
UNITS
mA mA mA V V % MHz V/ns V/ns V/ns V/ns ps ms
(VDD/2) -0.1 0.7 Measured @ 1.5V 45 66
VDD/2
(VDD/2)+ 0.1 VDD-0.4 55 170
50
TOR TOF TOR TOF TSKEW TST
Measured @ Measured @
0.4V ~ 2.4V 2.4V ~ 0.4V
1.0 1.0 0.25 0.25
1.5 1.5 0.6 0.6
2.0 2.0 1.0 1.0 100 0.1
Measured between 20% to 80% of output Measured between 20% to 80% of output All outputs equally loaded
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/03/01 Page 6
Preliminary
PLL103-07
2 DIMM DDR Fanout Buffer
PACKAGE INFORMATION
0.301 - 0.311 7.645 - 7.899
0.205- 0.212 5.207 - 5.385
0.010 - 0.015 0.254 - 0.381 0.015 (0.381) 0.005 - 0.008 (0.127 - 0.203) 45 0 0.396 - 0.407 (10.06 - 10.33)
0.0256 0.6502 0.066 - 0.070 (1.676 - 1.778)
0.068 - 0.078 (1.727 - 1.981) 00-8 0 0.022 - 0.037 (0.55 - 0.95) 0.002 - 0.008 (0.0508- 0.2032)
28 PIN SSOP
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PART NUMBER
PLL103-07 X C
PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by PhaseLink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/03/01 Page 7

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