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| Release PM7328 S/UNI-ATLAS-1K800 ATM Layer Solution FEATURES * Monolithic single chip device which handles bi-directional ATM Layer functions including VPI/VCI address translation, cell appending, policing (ingress only), cell counting and OAM requirements for 1024 VCs (virtual connections). * Instantaneous bi-directional transfer rate of 800 Mbit/s supports a bidirectional cell transfer rate of 1.42x106 cell/s. * Ingress input interface supports an 8 or 16 bit PHY interface using direct addressing for up to 4 PHY devices (Utopia Level 1) and Multi-PHY addressing for up to 32 PHY devices (Utopia Level 2). * Ingress output interface supports an 8 or 16 bit SCI-PHY (52 - 64 byte cell) interface (Utopia Level 1) to a switch fabric. * Egress input and output interfaces support an 8 or 16 bit SCI-PHY (52 64 byte cell) interface using direct addressing for up to 4 PHY devices (Utopia Level 1) and Multi-PHY addressing for up to 32 PHY devices (Utopia Level 2). * Compatible with the PM7329 S/UNIAPEX-1K800 Traffic Manager, and PMC-Sierra's VORTEX Architecture. * Ingress functionality includes a highly flexible search engine that covers the entire PHYID/VPI/VCI address range, dual leaky bucket policing, per-VC cell counts, OAM-FM and OAM-PM processing. * Egress functionality includes direct address lookup, per-VC cell counts, OAM-FM and OAM-PM processing. Per-PHY output buffering scheme resolves the head-of-line blocking issue. * Includes a FIFO buffered 16-bit microprocessor bus interface for cell insertion and extraction, deterministic VC Table access, status monitoring and configuration of the device. * Supports DMA access for cell extraction. * The UTOPIA and external SRAM interfaces are 52 MHz max. POLICING * ITU-I.371, ATM Forum TM4.0 compliant, per-VC programmable dual leaky bucket policing with a programmable action (tag, discard, or count only) for each bucket, each with 3 programmable 16 bit non-compliant cell counts. * Per-PHY single leaky bucket policing with a programmable action (tag, discard, or count only). SCI-PHY Level 1/ Level 2 Interface (Master) RDAT[15:0] RPRTY RDRENB[1] RCA[1] RADDR[4:3]/RCA[3:2] RAVALID/RCA[4] RADDR[2:0]/RRDENB[4:2] RSOC RFCLK RPOLL ISYSCLK ISD[63:0] ISP[7:0] ISA[19:16] ISA[9:0] ISWRB ISOEB ISADSB BLOCK DIAGRAM To External Synchronous SRAM SCI-PHY Level 1 Interface (Slave) ODAT[15:0] OPRTY OSOC OFCLK OCA ORDENB OTSEN Ingress Input Cell Interface Ingress Search Engine Ingress Cell Processor Ingress Output Cell Interface Ingress Backward Cell Interface PHY Statistics Collection Egress Backward Cell Interface Egress Input Cell Interface IDAT[15:0] IPRTY IFCLK ISOC ICA[1] IWRENB[1] IAVALID/ICA[4] IADDR[4:3]/ICA[3:2] IADDR[2:0]/IWRENB[4:2] IPOLL TDAT[15:0] TPRTY TWRENB[1] TCA[1] TADDR[4:3]/TCA[3:2] TAVALID/TCA[4] TADDR[2:0]/TDWRENB[4:2] TSOC TFCLK TPOLL Egress Output Cell Egress Cell Processor Ingress Microprocessor Cell Interface Egress Microprocessor Cell Interface JTAG Interface Microprocessor Interface ESD[31:0] ESP[3:0] ESA[19:16] ESA[9:0] ESADSB ESRWB ESOEB ESYSCLK SCI-PHY Level 1/ Level 2 Interface (Master) SCI-PHY Level 1/ Level 2 Interface (Slave) To External Synchronous SRAM PMC-2010037 (r2) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE (c) Copyright PMC-Sierra, Inc. 2001 Release PM7328 S/UNI-ATLAS-1K800 ATM Layer Solution * Guaranteed Frame Rate (GFR) Policing with Minimum Cell Rate Frame Tagging. CELL COUNTING * Per-VC counts include CLP0 cells, CLP1 cells, policing violations. * Per-PHY counts include CLP0 cells, CLP1 cells, OAM cells, errored OAM cells, unassigned/invalid cells and policing violations. * Per-device counts include total cells received/transmitted, and physical layer cells. OAM * ITU-I.610 compliant OAM on both Ingress and Egress directions. * Complete Fault Management (AIS, RDI, CC) processing, for VP/VC, Segment/End-to-end flows on all VCs. * Complete Performance Monitoring processing, for VP/VC, Segment/Endto-end, Forward/Backward flows, on 256 Bi-directional VCs. * Low power 0.35 micron, 3.3V CMOS technology with a 3.3V UTOPIA (SCIPHY), 3.3/5V Microprocessor I/O interfaces and 3.3V external synchronous SRAM interfaces. * Packaged in 432-pin ball grid array (BGA) package. APPLICATIONS * Mini Digital Subscriber Loop Access Multiplexer (Mini-DSLAM). * Subscriber Access Equipment. * Digital Loop Card Traffic Aggregation. PACKAGING * Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes. TYPICAL APPLICATION S/UNI-ATLAS-1K800 IN OC3 MINI-DSLAM APPLICATION Any-PHY/ SCI-PHY line cards DSL PHY up to 31 Utopia L2 ports PM7351 S/UNIVORTEX PM7350 S/UNIDUPLEX line cards DSL PHY DSL PHY up to 31 Utopia L2 ports PM7350 S/UNIDUPLEX DSL PHY I- EX UN RT S/ O o I-V t ks UN lin S/ r DS pe LV s 8 ice to dev p UX E PL DU 200 Mbit/s LVDS PM7329 S/UNI-APEX1K800 PM7328 S/UNI-ATLAS1K800 PHY Context SSRAM Ingress SSRAM Host CPU Packet/Cell SDRAM Egress SSRAM Core Card S/UNI-ATLAS-1K800 IN OC3 DIGITAL LOOP CARD APPLICATION line interface Any-PHY/ SCI-PHY Bus DSL PHY PM7329 S/UNI-APEX1K800 PM7328 S/UNI-ATLAS1K800 PHY DSL PHY expansion Context SSRAM Ingress SSRAM Host CPU DSL PHY Packet/Cell SDRAM Egress SSRAM Digital Loop Card Head Office: PMC-Sierra, Inc. #105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com PMC-2010037 (r2) (c) Copyright PMC-Sierra, Inc. 2001. All rights reserved. August 2001 S/UNI is a registered trademark of PMC-Sierra, Inc. Any-PHY and SCI-PHY are trademarks of PMC-Sierra, Inc. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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