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| SCG9800 8-BIT MICROCONTROLLER SCG9800 Microcontroller Specification FEATURE SUMMARY Technology - CMOS technology. I/O Ports - - 1 8-bit programmable I/O port. 1 2-bit output port. CPU - - 8-bit CPU core. 128 powerful and easy-to-use instruction set. Timer - - - 2 8-bit pre-scalar auto reload timers which can be cascaded to form one 16-bit timer. 1 real time timer. 1 watch dog timer. Memory - - - Internal RAM: 240 x 8 Memory is organized as 16K-byte page. External memory access of up to 1M x 8, can be both ROM and RAM. Operating Voltage - 2.4V to 5.5V. I/O Structure - Memory mapped I/O structure. Oscillation Frequency - - RC Oscillator for the main system clock up to 4MHz, instruction cycle ~0.5us. Subsystem clock frequency of 32.768kHz for real time timer. Power Down - - Stop mode (stop main and subsystem clock to core) Sleep mode (stop main system clock only) Interrupts - - - - 2 timer interrupts. 1 real time interrupt. 1 external event interrupt. 1 software interrupt. Score Concept Semiconductor Ltd. 1 Sept 2000 SCG9800 8-BIT MICROCONTROLLER FUNCTION OVERVIEW Program Memory Map RAM Area: Address $00-$0F $10-$FF Description H/W registers and I/Os Data memory and Stack Figure 1. Memory map in RAM area External ROM Area: Physical Address $0000-$3FFF Page 0 Program Reset address at $0000 $4000-$7FFF $8000-$BFFF $C000-$FFFF Page 1 Page 2 Page 3 Software interrupt at $FFC0 External interrupt at $FFD0 Timer 1 interrupt at $FFE0 Timer 0/RTC interrupt at $FFF0 Description ~ $7C000-$7FFFF Page 31 : : ~ ~ $FC000-$FFFFF Page 63 : : ~ Figure 2. Memory map in external ROM area Score Concept Semiconductor Ltd. 2 Sept 2000 SCG9800 8-BIT MICROCONTROLLER CPU core An 8-bit accumulator based CPU core can directly address up to 64 x 16K byte addressing space. Most of the instructions are executed in two cycles. Instruction is generally one byte and will have an extra byte for some addressing modes. CPU Registers: Program Counter (PC) The 14-bit Program Counter stores address for instruction fetch during program execution. It makes up a page size of 16K bytes. Together with the Program Page Register (iPAGE), it becomes a 20-bit address that can access up to 1,048,576 bytes. When the CPU resets, the content of the iPAGE:PC will be 00:0000. If interrupt occurs, the type of interrupt will then determine its content. PC will automatically be incremented to the next instruction after an instruction fetch. Table 1. Different types of interrupt Interrupt Timer 0 / RTC Interrupt Timer 1 Interrupt External Interrupt Software Interrupt IPAGE:PC 3H:3FF0H 3H:3FE0H 3H:3FD0H 3H:3FC0H Page Register (PAGE) An 8-bit Page Register is used to change the program flow. The most significant two bits are always set to zero. Data Bank Register (BANK) An 8-bit Bank Register is used to access data memory. The most significant two bits are always set to zero. Program Page Register (iPAGE) An 8-bit Program Page Register is combined with PC for instruction fetch. The most significant two bits are always set to zero. Accumulator (A) An 8-bit Accumulator is used for arithmetic, logical and data movement operation. Temporary Register (B) An 8-bit temporarily storage is used for accumulator. Index Registers (X, Y) These two 8-bit registers can be used for general registers and index registers of the indirect addressing mode. They can also be used as pointer for table read and memory write instructions. Score Concept Semiconductor Ltd. 3 Sept 2000 SCG9800 8-BIT MICROCONTROLLER Stack Register (SP) An 8-bit Stack Register (SP) stores the address for stack operation. After CPU resets, the value is $00. The SP has to be initialized at $FF by software. This means the stack frame starts from the highest address memory location. Program Status (PS) This is an 8-bit Program Status Register. However only 4-bit is used for controlling ALU operations and instruction execution sequences. Program Status Bit 7 6 5 4 3 2 1 0 Sign Zero Carry Interrupt Mask Reserved Figure 3. 8-bit Program Status Carry Flag (C) Whenever there is a carry or borrow occurs after an arithmetic operation, carry flag is set to 1. Otherwise, it is cleared to 0. Besides, the "Rotate" instructions can also change the carry flag which value is a bit shifted out of the specified source operand. Executing single instruction of "SETC" or "CLRC" can also alter this flag. Upon returning from an interrupt service routine, this flag will be restored. Zero Flag (Z) For arithmetic and logical operations, Zero flag will be set to 1 if the result is zero. Besides, for operation that involves moving source operand to accumulator, zero flag will also be set to 1 if the content of the source operand is zero. Upon returning from an interrupt service routine, this flag will be restored. Sign Flag (N) Sign flag stores the most significant bit of a result after the following operations: a. Arithmetic b. Logic c. Move from source operand to accumulator This flag will also be restored upon returning from an interrupt service routine. Score Concept Semiconductor Ltd. 4 Sept 2000 SCG9800 8-BIT MICROCONTROLLER Interrupt Mask Flag (I) The flag will be set to 1 when entering an interrupt service routine. By that time, all other interrupt events will be pending. After exiting from the interrupt service routine, this interrupt mask flag will be cleared to 0. Then interrupt handling will be resumed. Memory By connecting PAD_EXT_ADDR to HIGH, external memory access of 512K bytes is allowed. In addition, setting bit5 of the internal register TCONG will expand memory access to another 512K bytes. This extra external memory block can be RAM or ROM. For this ROM-less chip, memory is arranged in 16K-byte page size each. Therefore, there can have 32 pages for 512K bytes of memory space. Regarding the instruction pointer, it is organized as iPAGE:PC for instruction fetch. Change of program flow between pages is by modifying the PAGE register and then followed by executing a JMP or CALL instruction. These two instructions will load the PAGE register to iPAGE and change the content in PC for long JMP or CALL instruction. It does not need to change the PAGE register if it is a short JMP/CALL (i.e. JMP/CALL within page) because the PAGE register is normally the same as the iPAGE register. To exit a subroutine, long or short return type must be specified for long or short CALL respectively. The microcontroller has 240 bytes internal RAM data storage of address $10-$FF. This area includes stack frame and data memory. The stack frame is usually initialized at the highest RAM address location, i.e. $FF. Oscillation Circuits Main system and subsystem oscillation circuitry generates the internal clock signal for the CPU and other hardware timings. The main system clock uses the RC oscillation source. The operating frequency is up to 4 MHz. This clock is for the CPU and the two timers. The subsystem clock is for the real time signals. It uses a 32.768 kHz crystal. It has to be tied to a voltage level, either HIGH or LOW, if the real time timer and the watch dog timer are not used. Power Down The microcontroller supports power down mode for saving power. Executing a STOP instruction will stop both main system and subsystem clock to the core to save most of the microcontroller power. To enter sleep mode, execute a SLEEP instruction will stop the system clock only. Only an external interrupt will release the microcontroller from STOP mode if external interrupt enable bit is set to 1. For SLEEP mode, the microcontroller will be awoken every 0.5 sec or by the external interrupt if corresponding enable bit is set to 1. Score Concept Semiconductor Ltd. 5 Sept 2000 SCG9800 8-BIT MICROCONTROLLER Interrupts The MICROCONTROLLER has 2 timer interrupts, one real time interrupt, one external event interrupt and one software interrupt. When interrupt occurs, the content of PC, iPAGE and PS are pushed onto the stack in sequence. And then, the corresponding interrupt vector is loaded into iPAGE:PC. Upon executing a RTI instruction, the registers are popped out of the stack in the reversed order. The preference of interrupt priority is Timer 0 / RTC interrupt, Timer 1 interrupt and then external interrupt. I/O Ports The microcontroller has one 2-bit output port and one software-controllable 8-bit I/O port. For I/O port 0, there is a pull-low resistor when it is configured in input mode, and this resistor is disabled when it is in output mode. For Port 5, it is a 2-bit output port only. Remark: Port 4 bit3 can be an output if the chip is not configured as 8M bits external memory access via setting bit6 of the internal register TCONG. Timers The microcontroller has two programmable 8-bit timers (T0 and T1) for system timing. It has also a real time timer and a watch dog timer when subsystem clock is employed. All the timers can be enabled or disabled by configuring an internal register, TCONG. At CPU resets, all of them are disabled. T0 and T1 are up-counters and can be configured as either two 8-bit pre-scalar auto reload timer or as a 16-bit pre-scalar auto reload timer. The timer overflow flag will be set if the timer overflows. Then an interrupt will be generated if the corresponding interrupt enable bit is set to 1. The real time timer provides 0.5 sec interrupt for RTC functions. Watch dog timer will overflow in ~1 sec and then will reset the CPU. Score Concept Semiconductor Ltd. 6 Sept 2000 SCG9800 8-BIT MICROCONTROLLER BLOCK DIAGRAM P0 OUTPUT LATCH P0 INTERRUPT CONTROL RTC D[7:0] A[18:0] WATCH DOG CONTROL P43 A19 XTAL ALU SEL A TIMER0 PC TIMER1 iPAGE PAGE OSC BANK X Y SP PS WR CS1 CS2 P43/A19 MUX B RD P5 OUTPUT LATCH P5 CPU CORE ADDRESS BUS & CONTROL DATA BUS INTERNAL RAM 240x8 Figure 4. Block diagram of SCG9800 Score Concept Semiconductor Ltd. 7 Sept 2000 SCG9800 8-BIT MICROCONTROLLER PIN DESCRIPTIONS Table 2. Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Name A0 A1 A2 A3 A4 A5 A6 A7 VDD VSS D0 D1 D2 D3 D4 D5 D6 D7 P50 P51 P00 P01 P02 VDD VSS P03 P04 P05 P06 P07 EXT_ADDR TEST_ROM VSS VDD Type O/P O/P O/P O/P O/P O/P O/P O/P Power Power I/O I/O I/O I/O I/O I/O I/O I/O O/P O/P Description Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Supply Voltage Ground Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Port 5 Port 5 Pad Type Pad type 2 Pad type 2 Pad type 2 Pad type 2 Pad type 2 Pad type 2 Pad type 2 Pad type 2 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 2 Pad type 2 I/O I/O I/O Power Power I/O I/O I/O I/O I/O I/P I/P Power Power I/P I/P I/P Port 0 Port 0 Port 0 Supply Voltage Ground Port 0 Port 0 Port 0 Port 0 Port 0 External address Test pin, no connection Ground Supply Voltage Reset pin External Interrupt pin 32.768kHz RTC Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 4 Pad type 4 RESET EXT_INT CLK32I Pad type 3 Pad type 4 Pad type 6 Score Concept Semiconductor Ltd. 8 Sept 2000 SCG9800 8-BIT MICROCONTROLLER Pin 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Name CLK320 TEST P_CLK_0 P_CLK A15 A14 A13 A12 A11 A10 A9 A8 VSS VDD Type O/P I/P O/P I/P I/O I/O I/O I/O I/O I/O I/O I/O Power Power O/P O/P O/P O/P O/P O/P O/P O/P Description 32.768KHz RTC Test pin, no connection RC oscillator output RC oscillator for the main system clock Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Ground Supply Voltage Chip select 2 Chip select 1 Write signal Read signal Port 4 bit3/ Address bus bit19 Address bus Address bus Address bus Pad Type Pad type 6 Pad type 4 Pad type 6 Pad type 5 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 CS2 CS1 WR RD P43/A19 A18 A17 A16 Pad type 2 Pad type 2 Pad type 2 Pad type 2 Pad type 2 Pad type 2 Pad type 2 Pad type 2 Score Concept Semiconductor Ltd. 9 Sept 2000 SCG9800 8-BIT MICROCONTROLLER data in bond pad Schmitt input data out output enable tristate control Figure 5. Pad type 1 (bi-directional pad) data out bond pad tristate control output enable Figure 6. Pad type 2 (output pad) Reset Schmitt input Figure 7. Pad type 3 ( Reset ) Score Concept Semiconductor Ltd. 10 Sept 2000 SCG9800 8-BIT MICROCONTROLLER INT Schmitt input Figure 8. Pad type 4 (external interrupt) Test Test=1 Test=0 RC circuitry Clock out RC pad enable Figure 9. Pad type 5 (RC oscillation pad) 47pF CLK32I 10M 32.768 kHz CLK32O 47pF Figure 10. Pad type 6 (Clock circuit) Score Concept Semiconductor Ltd. 11 Sept 2000 SCG9800 8-BIT MICROCONTROLLER Control Registers Summary Table 3. Summary of Control Registers Hex 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Mnemonic P0DIR P0PULL P0RW P1DIR P1RW P2W P4W P5W TCONG INTR TFLAG T0VAL T1VAL Control Registers Name Port 0 Direction Control Register Port 0 Pull-Low Control Register Port 0 Read/Write Port Port 1 Direction Control Register Port 1 Read/Write Port Port 2 Output Port Port 4 Output Port Port 5 Output Port Timer Configuration Port Interrupt Control Register Timer Flag Status Register/Watch-dog Reset Timer 0 Preset Value Register Timer 1 Preset Value Register R/W W W R/W W R/W W W W W W R/W W W - Descriptions P0DIR and P1DIR Bit R/W 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0 W 0: Input mode (default) 1: Output mode Figure 11. Port 0 and Port 1 Direction Control Registers P0PULL Bit R/W 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0 W 0: Pull-low resistor disable (default) 1: Pull-low resistor enable Figure 12. Port 0 Pull-low Control Register Score Concept Semiconductor Ltd. 12 Sept 2000 SCG9800 8-BIT MICROCONTROLLER P0RW and P1RW Bit R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Write to output latch. Read from input pin. Read value of Output pin will be the output latch value. Figure 13. Port 0 and Port 1 Read/Write Port P2W Bit R/W 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0 W Write to output latch Figure 14. Port 2 Output Port Score Concept Semiconductor Ltd. 13 Sept 2000 SCG9800 8-BIT MICROCONTROLLER TCONG Bit R/W 7 6 5 4 W 3 W 2 W 1 W 0 W Reserved 000 : disable T0 and T1 0x1 : enable T0 01x : enable T1 1xx : cascade T0:T1 as 16-bit timer Real time timer 0 : disable 1 : enable (0.5s interrupt) Watch dog timer 0 : disable 1 : enable (~1s) External memory access, EM 0 : disable (default) 1 : enable External memory access mode, EMM (see below) External memory access mode, EMM With external memory access enabled, i.e. EM set, EXT-ADDR 0 0 1 1 EMM 0 1 0 1 Size 4M-bit 2M-bit 2M-bit 4M bit 4M bit 8M bit External Memory Chip Select CS1 CS1 CS2 CS1 CS2 CS1 Figure 15. Timer Configuration Port Score Concept Semiconductor Ltd. 14 Sept 2000 SCG9800 8-BIT MICROCONTROLLER INTR Bit R/W 7 6 5 4 3 2 W 1 W 0 W Reserved External interrupt 0 : disable 1 : enable T1 interrupt 0 : disable 1 : enable T0/RTC (half second) interrupt 0 : disable 1 : enable Figure 16. Interrupt Control Register TFLAG Bit R/W 7 6 5 4 3 R 2 R 1 R 0 R Reserved CLK32I Input 0 : T0 not overflow 1 : T0 overflow 0 : T1 not overflow 1 : T1 overflow Note : Read will reset all flags. Any write operation to TFLAG will reset the watch dog timer. 0 : not half second 1 : half second Figure 17. Timer Flag Status Register/Watch-dog Reset Score Concept Semiconductor Ltd. 15 Sept 2000 SCG9800 8-BIT MICROCONTROLLER T0VAL and T1VAL Bit R/W 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0 W Write timer 0 and timer 1 preset value Timer frequency = system clock 1 x 2 counter value For either T0 or T1, Maximum counter value = 255 Minimum frequency 7840Hz For T0:T1, Maximum counter value = 65535 Minimun frequency 30Hz Figure 18. Timer 0 and Timer 1 Preset Value Register Score Concept Semiconductor Ltd. 16 Sept 2000 SCG9800 8-BIT MICROCONTROLLER INSTRUCTION SUMMARY There are 128 instructions. All instructions are one or two byte instructions. The followings are the notations used: A B C Z N X Y SP (SP) BANK PAGE iPAGE PC PS I (X) (Y) label (label) ADDR14 ADDR 8 #CONSTANT Accumulator B Register Carry bit Zero bit Negative bit X Index Register Y Index Register Stack Pointer Register Stack Data Bank Register Page Register The page register for PC19-PC14 Program Counter PC13-0 Program Status Interrupt flag RAM pointed by X RAM pointed by Y A 8-bit RAM/Register label RAM pointed by the label A 14-bit address A 8-bit address A 8-bit constant Score Concept Semiconductor Ltd. 17 Sept 2000 SCG9800 8-BIT MICROCONTROLLER INSTRUCTION SET 1. ADC Code Operation Flags A 0100 0000 A + A + CA N, Z, C 9. AND X Code Operation Flags 0100 1010 X AA N,Z 2. ADC X Code Operation Flags 0100 0010 X + A + CA N, Z, C 10. AND Y Code Operation Flags 0100 1011 Y AA N,Z 3. ADC Y Code Operation Flags 0100 0011 Y + A + CA N, Z, C 11. AND (X) Code Operation Flags 0100 1110 (X) AA N,Z 4. ADC (X) Code Operation Flags 0100 0110 (X) + A + CA N, Z, C 12. AND (Y) Code Operation Flags 0100 1111 (Y) AA N,Z 5. ADC (Y) Code Operation Flags 0100 0111 (Y) + A + CA N, Z, C 13. AND label Code Operation Flags 0100 1100 zzzz zzzz (zzzz zzzz)AA N,Z 6. ADC label Code Operation Flags 0100 0100 zzzz zzzz (zzzz zzzz)+A+CA N, Z, C 14. AND #CONSTANT Code Operation Flags 0100 1001 zzzz zzzz Zzzz zzzz A A N,Z 7. ADC #CONSTANT Code Operation Flags 0100 0001 zzzz zzzz Zzzz zzzz +A+CA N, Z, C 15. BRA ADDR8 Code Operation Flags 0011 0010 zzzz zzzz Zzzz zzzz PC0-7 ----- 8. AND A Code Operation Flags 0100 1000 A AA N,Z Score Concept Semiconductor Ltd. 18 Sept 2000 SCG9800 8-BIT MICROCONTROLLER 16. CALL ADDR14 Code Operation 24. 11zz zzzz zzzz zzzz PC (SP);SP-2SP ADDR14 PC[13:0] If PAGE iPAGE IPAGE(SP);SP-1SP PAGE iPAGE 25. CMP Code Operation Flags 0000 0001 zzzz zzzz A zzzz zzzz Z CMP label Code Operation Flags 0000 0101 zzzz zzzz A (zzzz zzzz) Z Flags ----- 17. CLR A Code Operation Flags 0010 1000 0 A N,Z 26. CPMX #CONSTANT Code Operation 0000 1001 zzzz zzzz (X) zzzz zzzz Z 18. CLR X Code Operation Flags 0010 1010 0 X ----27. Flags CPMX label Code Operation 0000 1101 zzzz zzzz (X) zzzz zzzz Z 19. CLR Y Code Operation Flags 0010 1011 0 Y ----28. Flags CPX #CONSTANT Code Operation 0001 0001 zzzz zzzz X zzzz zzzz Z 20. CLR (X) Code Operation Flags 0010 1110 0 (X) ----29. Flags CPX label Code Operation 0001 0101 zzzz zzzz X (zzzz zzzz) Z 21. CLR (Y) Code Operation Flags 0010 1111 0 (Y) ----30. Flags CPY #CONSTANT Code Operation 0001 1001 zzzz zzzz Y zzzz zzzz Z 22. CLR label Code Operation Flags 0010 1100 0 (zzzz zzzz) ----31. Flags CPY label Code Operation 0001 1101 zzzz zzzz Y (zzzz zzzz) Z 23. CLRC Code Operation Flags 0110 0001 0 C C Flags Score Concept Semiconductor Ltd. 19 Sept 2000 SCG9800 8-BIT MICROCONTROLLER 32. DEC A Code Operation Flags 0110 1000 A - 1 A N, Z, C 41. EOR (Y) Code Operation Flags 0101 1111 (Y) A A N, Z 33. DEC X Code Operation Flags 0110 1010 X - 1 X N, Z, C 42. EOR label Code Operation Flags 0101 1100 zzzz zzzz (zzzz zzzz) A A N, Z 34. DEC Y Code Operation Flags 0110 1011 Y - 1 Y N, Z, C 43. EOR #CONSTANT Code Operation Flags 0101 1001 zzzz zzzz zzzz zzzz A A N, Z 35. DEC (X) Code Operation Flags 0110 1110 (X) - 1 (X) N, Z, C 44. INC A Code Operation Flags 0110 0000 A + 1 A N, Z, C 36. DEC (Y) Code Operation Flags 0110 1111 (Y) - 1 (Y) N, Z, C 45. INC X Code Operation Flags 0110 0010 X + 1 X N, Z, C 37. DEC label Code Operation Flags 0110 1100 zzzz zzzz (zzzz zzzz)-1 (zzzzzzzz) N, Z, C 46. INC Y Code Operation Flags 0110 0011 Y + 1 Y N, Z, C 38. EOR X Code Operation Flags 0101 1010 X A A N, Z 47. INC (X) Code Operation Flags 0110 0110 (X) + 1 X N, Z, C 39. EOR Y Code Operation Flags 0101 1011 Y A A N, Z 48. INC (Y) Code Operation Flags 0110 0111 (Y) + 1 Y N, Z, C 40. EOR (X) Code Operation Flags 0101 1110 (X) A A N, Z Score Concept Semiconductor Ltd. 20 Sept 2000 SCG9800 8-BIT MICROCONTROLLER 49. INC label Code Operation Flags 0110 0100 zzzz zzzz (zzzz zzzz) + 1 (zzzz zzzz) 55. MOV A, (X) Code Operation Flags 0000 0110 A (X) ----- N, Z, C 50. INT Code Operation 0011 0110 PC LOW (SP), SP-1 SP PCHIGH(SP), SP-1 SP IPAGE (SP), SP-1 SP PS (SP), SP-1 SP 1I 3FC0H PC 3 iPAGE,PAGE Flags I 56. MOV A, (Y) Code Operation Flags 0000 0111 A (Y) ----- 57. MOV A label Code Operation Flags 0000 0100 zzzz zzzz A (zzzz zzzz) ----- 58. MOV X, A Code Operation Flags 0001 0000 X A N, Z 51. JA Code Operation Flags 0111 0001 A PC[7:0] ----59. MOV X, Y Code Operation Flags 0001 0011 X Y ----- 52. JUMP ADDR14 Code Operation 10zz zzzz zzzz zzzz ADDR14 PC[13:0] If PAGEiPAGE PAGE iPAGE Flags ----61. MOV X, label Code 0000 0010 A X ----62. MOV Y, A Code 0000 0011 A Y ----Operation Flags 0001 1000 Y A N, Z Operation Flags 0001 0100 zzzz zzzz X (zzzz zzzz) ----60. MOV X, (Y) Code Operation Flags 0001 0111 X (Y) ----- 53. MOV A, X Code Operation Flags 54. MOV A, Y Code Operation Flags Score Concept Semiconductor Ltd. 21 Sept 2000 SCG9800 8-BIT MICROCONTROLLER 63. MOV Y, X Code Operation Flags 0001 1010 Y X ----- 72. MOV (Y), (X) Code Operation Flags 0011 1110 (Y) (X) ----- 64. MOV Y, (X) Code Operation Flags 0001 1110 Y (X) ----- 73. MOV (Y), label Code Operation Flags 0011 1100 zzzz zzzz (Y) (zzzz zzzz) ----- 65. MOV Y, label Code Operation Flags 0001 1100 zzzz zzzz Y (zzzz zzzz) ----- 74. MOV label, A Code Operation Flags 0010 0000 zzzz zzzz (zzzz zzzz) A N, Z 66. MOV (X), A Code Operation Flags 0011 0000 (X) A N, Z 75. MOV label, X Code Operation Flags 0010 0010 zzzz zzzz (zzzz zzzz) X ----- 67. MOV (X), Y Code Operation Flags 0011 0011 (X) Y ----- 76. MOV label, Y Code Operation Flags 0010 0011 zzzz zzzz (zzzz zzzz) Y ----- 68. MOV (X), (Y) Code Operation Flags 0011 0111 (X) (Y) ----- 77. MOV label, (X) Code Operation Flags 0010 0110 zzzz zzzz (zzzz zzzz) (X) ----- 69. MOV (X), label Code Operation Flags 0011 0100 zzzz zzzz (X) (zzzz zzzz) ----- 78. MOV label, (Y) Code Operation Flags 0010 0111 zzzz zzzz (zzzz zzzz) (Y) ----- 70. MOV (Y), A Code Operation Flags 0011 1000 (Y) A N, Z 79. MOV #CONSTANT, A Code Operation Flags 0000 1000 zzzz zzzz Zzzz zzzz A N, Z 71. MOV (Y), X Code Operation Flags 0011 1010 (Y) X ----- Score Concept Semiconductor Ltd. 22 Sept 2000 SCG9800 8-BIT MICROCONTROLLER 80. MOV #CONSTANT, X 89. 0000 1010 zzzz zzzz Zzzz zzzz X ----- OR label Code Operation Flags 0101 0100 zzzz zzzz (zzzz zzzz)V AA N, Z Code Operation Flags 81. MOV #CONSTANT, Y 90. 0000 1011 zzzz zzzz Zzzz zzzz Y ----- OR #CONSTANT Code Operation Flags 0101 0001 zzzz zzzz Zzzz zzzzV AA N, Z Code Operation Flags 82. MOV #CONSTANT, (X) 91. 0000 1110 zzzz zzzz Zzzz zzzz (X) ----- POP Code Operation 0011 1111 SP+1SP (SP)A Flags ----- Code Operation Flags 83. MOV #CONSTANT, (Y) Code Operation Flags 0000 1111 zzzz zzzz zzzz zzzz (Y) ----- 92. PSHPAGE Code Operation Flags 0110 1101 PAGE (SP); SP-1SP ----- 84. NOP Code Operation Flags 0000 0000 No operation ----- 93. PUSH Code Operation Flags 0110 1001 A(SP),SP-1SP ----- 85. OR X Code Operation Flags 0101 0010 X V AA N, Z 94. ROL A Code Operation Flags 0111 0000 CAC N, Z, C 86. OR Y Code Operation Flags 0101 0011 Y V AA N, Z 95. ROL X Code Operation Flags 0111 0010 CXC N, Z, C 87. OR (X) Code Operation Flags 0101 0110 (X) V AA N, Z 96. ROL Y Code Operation Flags 0111 0011 CYC N, Z, C 88. OR (Y) Code Operation Flags 0101 0111 (Y) V AA N, Z Score Concept Semiconductor Ltd. 23 Sept 2000 SCG9800 8-BIT MICROCONTROLLER 97. ROL (X) Code Operation Flags 0111 0110 C(X)C N, Z, C 106. ROR (X) Code Operation Flags 0111 1110 C(X)C N, Z, C 98. ROL (Y) Code Operation Flags 0111 0111 C(Y)C N, Z, C 107. ROR (Y) Code Operation Flags 0111 1111 C(Y)C N, Z, C 99. ROL label Code Operation Flags 0111 0100 zzzz zzzz C(zzzz zzzz)C N, Z, C 108. ROR label Code Operation Flags 0111 1100 zzzz zzzz C(zzzz zzzz)C N, Z, C 100. ROM A Code Operation Flags 0111 1101 ROM (BANK,X,A)A ----- 109. RTI Code Operation 0100 0101 SP+1SP (SP)PS;SP+11 (SP)IPAGE,PAGE; 101. ROM Y Code Operation Flags 0111 1001 ROM (BANK,X,Y)A ----Flags SP+1SP (SP)PCHIGH; SP+1SP (SP)PCLOW ----- 102. ROMDBL Code Operation Flags 0001 1001 ROM (BANK,X,Y)B ROM (BANK,X,Y+1)A ----110. RTL Code Operation 0100 1101 SP+1SP (SP)iPAGE,PAGE; SP+1SP 103. ROR A Code Operation Flags 0111 1000 CAC N, Z, C 111. RTS Code 0111 1010 CXC N, Z, C Operation Flags (SP)PCHIGH SP+1SP (SP)PCLOW ----- 104. ROR X Code Operation Flags 0101 0101 SP+1SP (SP)PCHIGH; SP+1SP (SP)PCLOW 105. ROR Y Code Operation Flags 0111 1011 CYC N, Z, C Flags ----- Score Concept Semiconductor Ltd. 24 Sept 2000 SCG9800 8-BIT MICROCONTROLLER 112. SETC Code Operation Flags 0110 0101 1C C 121. STOP Code Operation Flags 0010 0100 Stop ------ 113. SETZ Code Operation Flags 0101 1000 1Z,0A, N, Z 122. TAPAGE Code Operation Flags 0011 1 0101 APAGE ----- 114. SKIPC Code Operation Flags 0011 0001 PC+2PC if C = 1 ----- 123. TZ Code Operation 0101 0000 Z=1 if A = 0 Z=0 if A 0 Flags N, Z 115. SKIPMI Code Operation Flags 0001 0110 PC+2PC if N = 1 ----124. WRITE Code Operation Flags 0101 1101 A(BANK,X,Y) ----- 116. SKIPNC Code Operation Flags 0011 1001 PC+2PC if C = 0 ----125. XB Code Operation Flags 0010 0101 BA ----- 117. SKIPNZ Code Operation Flags 0010 1001 PC+2PC if Z = 0 ----126. XBANK Code Operation Flags 0011 0101 BANKA ----- 118. SKIPPL Code Operation Flags 0001 1111 PC+2PC if N = 0 ----127. XSP Code Operation Flags 0011 1101 SPA ----- 119. SKIPZ Code Operation Flags 0010 0001 PC+2PC if Z = 1 ----128. XST Code Operation Flags 0010 1101 PSA N, Z, C, I 120. SLEEP Code Operation Flags 0000 1100 Sleep ----- Score Concept Semiconductor Ltd. 25 Sept 2000 SCG9800 8-BIT MICROCONTROLLER ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings: 1. 2. 3. 4. 5. VDD VIH VIL Operating Temperature Storage Temperature 7.0V VDD + 0.3V VSS - 0.3V 0C to + 60C -50C to + 150C Recommended Operating: MIN 2.4 TYP 3.0 4.0 MAX 5.5 Unit V MHz 1. Operating Voltage (VDD) 2. Operating Frequency (Fosc) 3. Input Voltage 3.1 VDD = 2.4V 3.2 VDD = 3.0V 3.3 VDD = 5.5V VIH VIL VIH VIL VIH VIL 1.6 0 2.0 0 3.6 0 2.0 0.4 2.4 0.6 4.0 1.5 2.4 0.8 3.0 1.0 5.5V 1.8V V V V V V V 4. Output Voltage 4.1 VDD = 2.4V @1mA 4.2 VDD = 3.0V @2mA 4.3 VDD = 5.5V @10mA 5. Input Current VIH = VDD VOH VOL VOH VOL VOH VOL 2.0 2.4 4.0 - - 0.4 0.6 1.5 V V V V V V A (P0, P1 and P3) A (P0 only via internal pull-low resistor) A (leakage) IH - - 0.3 150 0.3 VIL = OV IL 6. Output Current 6.1 VDD = 2.4V, 6.2 6.3 VDD = 3.0V, VDD = 5.5V, IOH@VOH =2.0V IOL@VOL =0.4V IOH@VOH =2.4V IOL@VOL =0.6V IOH@VOH =4.0V IOL@VOL =1.5V 1.0 2.0 1.5 3.0 8 16 1.5 3.0 3.5 7.0 10 20 - mA mA mA mA mA mA 7. Current Dissipation 7.1 Operating Current @4MHz, 3.0V & Output Pad Load = 50pF 7.2 Operating Current @4MHz, 5.0V & Output Pad Load = 50pF 7.3 Standby Current (OFF mode) 1.0 2.0 - 1.5 3.0 1.0 4.5 9.0 9.0 mA mA A Score Concept Semiconductor Ltd. 26 Sept 2000 SCG9800 8-BIT MICROCONTROLLER PAD Co-ordinates 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A0 60 A1 59 A2 58 A3 57 A4 56 A5 55 A6 54 A7 Y VDD 52 VSS X D0 (0,0) D1 49 D2 48 D3 47 D4 46 D5 45 D6 44 D7 P50 A15 A14 A13 A12 A11 A10 50 A9 51 A8 VSS 53 VDD CS 2 CS1 WR RD P43/A19 A18 A17 A16 20 P51 21 22 23 P00 24 P01 25 P02 26 VDD 27 VSS 28 P03 29 P04 30 P05 31 P06 32 P07 33 EXT_ADDR 34 TEST_ROM 35 VSS 36 VDD 37 RESET- 38 EXT_INT 39 CLK32I 40 CLK32O 41 TEST 42 P_CLK_O 43 P_CLK The substrate of IC should be connected to VSS Score Concept Semiconductor Ltd. 27 Sept 2000 SCG9800 8-BIT MICROCONTROLLER Pad No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pad Name A0 A1 A2 A3 A4 A5 A6 A7 VDD VSS D0 D1 D2 D3 D4 D5 D6 D7 P50 P51 P00 P01 P02 VDD VSS P03 P04 P05 P06 P07 EXT_ADDR TEST_ROM VSS VDD RESET EXT_INT CLK32I CLK320 X -1773.100 -1773.100 -1773.100 -1773.100 -1773.100 -1773.100 -1773.100 -1773.100 -1773.100 -1773.100 -1773.100 -1773.100 -1773.100 -1773.100 -1773.100 -1773.100 -1773.100 -1773.100 -1773.100 -1563.500 -1143.500 -1003.500 -863.500 -723.500 -583.500 -443.500 -303.500 -163.500 -23.500 116.500 256.500 396.500 656.500 796.500 936.500 1076.500 1216.500 1356.500 Y 1127.050 987.050 847.050 707.050 567.050 427.050 287.050 147.050 7.050 -132.950 -272.950 -412.950 -552.950 -692.950 -832.950 -972.950 -1112.950 -1252.950 -1512.950 -1722.550 -1722.550 -1722.550 -1722.550 -1722.550 -1722.550 -1722.550 -1722.550 -1722.550 -1722.550 -1722.550 -1722.550 -1722.550 -1722.550 -1722.550 -1722.550 -1722.550 -1722.550 -1722.550 Pad No 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Pad Name TEST P_CLK_0 P_CLK A15 A14 A13 A12 A11 A10 A9 A8 VSS VDD CS2 CS1 WR RD P43/A19 A18 A17 A16 X 1496.500 1636.500 1776.500 1766.900 1766.900 1766.900 1766.900 1766.900 1766.900 1766.900 1766.900 1766.900 1766.900 1766.900 1766.900 1766.900 1766.900 1766.900 1766.900 1766.900 1766.900 Y -1722.550 -1722.550 -1722.550 -746.700 -606.700 -466.700 -326.700 -186.700 -46.700 93.300 233.300 373.300 513.300 653.300 793.300 933.300 1073.300 1213.300 1353.300 1493.300 1633.300 Score Concept Semiconductor Ltd. 28 Sept 2000 SCG9800 8-BIT MICROCONTROLLER Application Circuit U4 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 RD12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 31 22 24 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 CE OE 27C040 O0 O1 O2 O3 O4 O5 O6 O7 13 14 15 17 18 19 20 21 D0 D1 D2 D3 D4 D5 D6 D7 RDP43/A19 A18 A17 A16 A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 A0 A1 A2 A3 A4 A5 A6 A7 U5 SCG9800 57 58 59 60 61 RD P43/A19 A18 A17 A16 D0 D1 D2 D3 D4 D5 D6 D7 P5W0 P5W1 9 10 11 12 13 14 15 16 17 18 19 20 23 24 VDD GND D0 D1 D2 D3 D4 D5 D6 D7 P50 P51 P00 P01 WR CS1 CS2 VDD GND A8 A9 A10 A11 A12 A13 A14 A15 P_CLK P_CLK_O TEST 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 WRCS1CS2A8 A9 A10 A11 A12 A13 A14 A15 OPTIONAL CLK32O CLK32I EXT_INT RESET VDD GND TEST_ROM EXT_ADDR P07 P06 P05 P04 P03 GND VDD P02 RESET- R2 100K C3 22p 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 D1 LED D2 LED D4 LED D3 LED VCC VCC OPTIONAL Y1 R3 47K 32768 R1 1M C4 0.1u C1 C2 SCORE CONCEPT SEMICONDUCTOR LIMITED Title SCG9800 application circuit Size A Date: Document Number SCG9800 Saturday, September 16, 2000 Sheet 1 of 1 Rev 1 Score Concept Semiconductor Ltd. 29 Sept 2000 |
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