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N-CHANNEL 24V - 0.0034 - 120A DPAK/TO-220 STripFETTM III POWER MOSFET FOR DC-DC CONVERSION
Table 1: General Features
TYPE STB130NH02L STP130NH02L

STB130NH02L STP130NH02L
Figure 1:Package
RDS(on) < 0.0044 < 0.0044 ID 90 A(2) 90 A(2)
VDSS 24 V 24 V
TYPICAL RDS(on) = 0.0034 @ 10 V TYPICAL RDS(on) = 0.005 @ 5 V RDS(ON) * Qg INDUSTRY's BENCHMARK CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED LOW THRESHOLD DEVICE SURFACE-MOUNTING D2PAK (TO-263) POWER PACKAGE IN TUBE (NO SUFFIX) OR IN TAPE & REEL (SUFFIX "T4")
3 1
3 1 2
D2PAK TO-263 (Suffix "T4")
TO-220
DESCRIPTION
The STB_P130NH02L utilizes the latest advanced design rules of ST's proprietary STripFETTM technology. It is ideal in high performance DC-DC converter applications where efficiency is to be achieved at very high output currents.
Figure 2: Internal Schematic Diagram
APPLICATIONS SYNCHRONOUS RECTIFICATIONS FOR TELECOM AND COMPUTER OR-ING DIODE
Table 2: Ordering Information
SALES TYPE STB130NH02LT4 STP130NH02L MARKING B130NH02L P130NH02L PACKAGE TO-263 TO-220 PACKAGING TAPE & REEL TUBE
ABSOLUTE MAXIMUM RATINGS
Symbol Vspike(1) VDS VDGR VGS ID(2) ID(2) IDM(3) Ptot EAS (4) Tstg Tj April 2005 Parameter Drain-source Voltage Rating Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature Value 30 24 24 20 90 90 360 150 1 900 -55 to 175 Unit V V V V A A A W W/C mJ C 1/13
Rev. 2.0
STB130NH02L STP130NH02L
Table 4: THERMAL DATA
Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max 1.0 62.5 300 C/W C/W C
ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED)
Table 5: OFF
Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 25 mA, VGS = 0 VDS = 20 V VDS = 20 V VGS = 20 V Min. 24 1 10 100 Typ. Max. Unit V A A nA
TC = 125C
Table 6: ON (*)
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V VGS = 5 V ID = 250 A ID = 45 A ID = 22.5 A Min. 1 0.0034 0.005 0.0044 0.008 Typ. Max. Unit V
Table 7: DYNAMIC
Symbol gfs (5) Ciss Coss Crss RG Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Input Resistance Test Conditions VDS = 10 V ID = 45 A Min. Typ. 55 4450 1126 141 Max. Unit S pF pF pF
VDS = 15V f = 1 MHz VGS = 0
f = 1 MHz Gate DC Bias = 0 Test Signal Level = 20 mV Open Drain
1.6
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STB130NH02L STP130NH02L
ELECTRICAL CHARACTERISTICS (continued)
Table 8: SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Qoss(6) Qgls(7) Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Output Charge Third-quadrant Gate Charge Test Conditions VDD = 10 V ID = 45 A VGS = 10 V RG = 4.7 (Resistive Load, Figure ) VDD=10 V ID=90 A VGS=10 V Min. Typ. 14 224 69 13 9 27 64 93 Max. Unit ns ns nC nC nC nC nC
VDS= 16 V VDS< 0 V
VGS= 0 V VGS= 10 V
Table 9: SWITCHING OFF
Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions VDD = 10 V ID = 45 A VGS = 10 V RG = 4.7, (Resistive Load, Figure 3) Min. Typ. 69 40 Max. 54 Unit ns ns
Table 10: SOURCE DRAIN DIODE
Symbol ISD ISDM VSD (5) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 45 A VGS = 0 47 58 2.5 Test Conditions Min. Typ. Max. 90 360 1.3 Unit A A V ns nC A
ISD = 90 A di/dt = 100A/s Tj = 150C VDD = 15 V (see test circuit, Figure 5)
(1) Garanted when external Rg=4.7 and tf < tfmax. (2) Value limited by wire bonding (3) Pulse width limited by safe operating area. (4) Starting Tj = 25 oC, ID = 45A, VDD = 10V .
(5) Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (6) Qoss = Coss* Vin , Coss = Cgd + Cds . See Appendix A (7) Gate charge for synchronous operation
Figure 3: Safe Operating Area
Figure 4: Thermal Impedance
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STB130NH02L STP130NH02L
Figure 5: Output Characteristics Figure 6: Transfer Characteristics
Figure 7: Transconductance
Figure 8: Static Drain-source On Resistance
Figure 9: Gate Charge vs Gate-source Voltage
Figure 10: Capacitance Variations
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STB130NH02L STP130NH02L
Figure 11: Normalized Gate Threshold Voltage vs Temperature Figure 12: Normalized on Resistance vs Temperature
Figure 13: Source-drain Diode Forward Characteristics
Figure 14: Normalized Breakdown Voltage vs Temperature
.
.
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STB130NH02L STP130NH02L
Figure 15: Unclamped Inductive Load Test Circuit Figure 16: Unclamped Inductive Waveform
Figure 17: Switching Times Test Circuits For Resis-
tive Load
Figure 18: Gate Charge test Circuit
Figure 19: Test Circuit For Inductive Load Switch-
ing And Diode Recovery Times
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STB130NH02L STP130NH02L TO-220 MECHANICAL DATA
DIM. A C D E F F1 F2 G G1 H2 L2 L3 L4 L5 L6 L7 L9 DIA 13 2.65 15.25 6.20 3.50 3.75 mm. MIN. 4.4 1.23 2.40 0.49 0.61 1.14 1.14 4.95 2.40 10 16.40 28.90 14 2.95 15.75 6.60 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147 TYP. MAX. 4.6 1.32 2.72 0.70 0.88 1.70 1.70 5.15 2.70 10.40 MIN. 0.173 0.048 0.094 0.019 0.024 0.044 0.044 0.194 0.094 0.393 0.645 1.137 0.551 0.116 0.620 0.260 0.154 0.151 inch. TYP. TYP. 0.181 0.051 0.107 0.027 0.034 0.067 0.067 0.203 0.106 0.409
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STB130NH02L STP130NH02L D2PAK MECHANICAL DATA
DIM. A A1 A2 B B2 C C2 D D1 E E1 G L L2 L3 M R V2 0 4.88 15 1.27 1.4 2.4 0.4 8 0 10 8.5 5.28 15.85 1.4 1.75 3.2 0.192 0.591 0.050 0.055 0.094 0.015 8 mm. MIN. 4.4 2.49 0.03 0.7 1.14 0.45 1.21 8.95 8 10.4 0.394 0.334 0.208 0.624 0.055 0.069 0.126 TYP. MAX. 4.6 2.69 0.23 0.93 1.7 0.6 1.36 9.35 MIN. 0.173 0.098 0.001 0.028 0.045 0.018 0.048 0.352 0.315 0.409 inch. TYP. TYP. 0.181
0.106
0.009 0.037 0.067 0.024 0.054 0.368
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STB130NH02L STP130NH02L
D2PAK FOOTPRINT
TUBE SHIPMENT (no suffix)*
TAPE AND REEL SHIPMENT (suffix "T4")*
REEL MECHANICAL DATA
DIM. A B C D G N T 1.5 12.8 20.2 24.4 100 30.4 BASE QTY 1000 26.4 13.2 mm MIN. MAX. 330 0.059 0.504 0.795 0.960 3.937 1.197 BULK QTY 1000 1.039 0.520 MIN. inch MAX. 12.992
TAPE MECHANICAL DATA
DIM. A0 B0 D D1 E F K0 P0 P1 P2 R T W mm MIN. 10.5 15.7 1.5 1.59 1.65 11.4 4.8 3.9 11.9 1.9 50 0.25 23.7 0.35 24.3 MAX. 10.7 15.9 1.6 1.61 1.85 11.6 5.0 4.1 12.1 2.1 MIN. 0.413 0.618 0.059 0.062 0.065 0.449 0.189 0.153 0.468 0075 1.574 .0.0098 0.933 0.0137 0.956 inch MAX. 0.421 0.626 0.063 0.063 0.073 0.456 0.197 0.161 0.476 0.082
* on sales type
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STB130NH02L STP130NH02L
APPENDIX A Buck Converter: Power Losses Estimation
SW1
SW2
The power losses associated with the FETs in a Synchronous Buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. The low side (SW2) device requires: * * * * * Very low RDS(on) to reduce conduction losses Small Qgls to reduce the gate charge losses Small Coss to reduce losses due to output capacitance Small Qrr to reduce losses on SW1 during its turn-on The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon;
The high side (SW1) device requires: * Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate * Small Q g to have a faster commutation and to reduce gate charge losses * Low RDS(on) to reduce the conduction losses.
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STB130NH02L STP130NH02L
High Side Switch (SW1)
Low Side Switch (SW2)
Pconduction
R DS(on)SW1 * I 2 * L
R DS(on)SW2 * I 2 * (1 - ) L
Pswitching
Vin * (Q gsth(SW1) + Q gd(SW1) ) * f *
IL Ig
Zero Voltage Switching
Pdiode
Recovery
Not Applicable
1
Vin * Q rr(SW2) * f
Conduction
Not Applicable
Vf(SW2) * I L * t deadtime * f Q gls(SW2) * Vgg * f
Pgate(Q G )
Q g(SW1) * Vgg * f
PQoss
Vin * Q oss(SW1) * f 2
Vin * Q oss(SW2) * f 2
Parameter d Qgsth Qgls Pconduction Pswitching Pdiode Pgate PQoss
Meaning Duty-cycle Post threshold gate charge Third quadrant gate charge On state losses On-off transition losses Conduction and reverse recovery diode losses Gate drive losses Output capacitance losses
1
Dissipated by SW1 during turn-on
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STB130NH02L STP130NH02L
Table 11:Revision History
Date
April 2005
Revision
2.0
Description of Changes
ADDED PACKAGE TO-220
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STB130NH02L STP130NH02L
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners.
(c) 2005 STMicroelectronics - All Rights Reserved
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