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STP80N05-09
N - CHANNEL ENHANCEMENT MODE "ULTRA HIGH DENSITY" POWER MOS TRANSISTOR
TYPE STP80N05-09
s s s s s s
VDS S 50 V
RDS(o n) < 0.009
ID 80 A
ULTRA HIGH DENSITY TECHNOLOGY TYPICAL RDS(on) = 7 m AVALANCHE RUGGED TECHNOLOGY LOW GATE CHARGE HIGH CURRENT CAPABILITY o 175 C OPERATING TEMPERATURE
1 2
3
APPLICATIONS s SYNCROUNOUS RECTIFIERS s HIGH CURRENT, HIGH SPEED SWITCHING s DC-DC & DC-AC CONVERTER ABSOLUTE MAXIMUM RATINGS
TO-220
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VDGR V GS ID ID I DM (*) Pt ot Parameter Drain-source Voltage (VGS = 0) Drain- gate Vol tage (R GS = 20 k) Gate-s ource Voltage Drain Current (conti nuous) at Tc = 25 C Drain Current (conti nuous) at Tc = 100 C Drain Current (pulsed) Total Dis sipation at Tc = 25 o C Derating Fac tor dV/dt(1) Peak Diode Recov ery vo ltage slo pe Tstg Tj Storage Temperature Max. Operating Junction Temperature
o o
Value 50 50 20 80 60 320 150 1 5 -65 to 175 175
(1) ISD 60 A, di/dt 200 A/ms, V DD V(BR)DSS, TJ TJMAX
Unit V V V A A A W W/ oC V/ns
o o
C C
(*) Pulse width limited by safe operating area
March 1997
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THERMAL DATA
Rt hj-case R th j-amb Rthc-sink Tl Thermal Resist ance Junc tion-case Max Thermal Resist ance Junc tion-ambi ent Max Thermal Resist ance Case -sink Typ Max imum Lead Temperature For Sol dering Purpose 1 62.5 0.5 300
o o
C/W C/W o C/W o C
AVALANCHE CHARACTERISTICS
Symbol I AR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limit ed by Tj max , < 1%) Sin gle Pul se Aval anc he Energy o (starting Tj = 25 C, ID = IAR, VDD = 25 V) Max Value 60 600 Unit A mJ
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF
Symbol V(BR)DSS IDS S I GSS Parameter Drain-so urce Breakdown Voltage Test Conditions I D = 250 A VGS = 0 Min. 50 1 10 100 Typ. Max. Unit V A A nA
Zero G ate Voltage VDS = Max Rating Drain Current (VG S = 0) VDS = Max Rating Gate-body Leak age Current (VDS = 0) VG S = 20 V
Tc = 125 oC
ON ()
Symbol VGS( th) RDS( on) I D(on) Parameter Gate Threshold Voltage VDS = V GS Static Drai n-s ource On Resistance Test Conditions ID = 250 A VG S = 10V I D = 40 A 80 Min. 2 Typ. 3 0.007 Max. 4 0.009 Unit V A
On State Drai n Current VDS > I D(on) x R DS(on)max VG S = 10 V
DYNAMIC
Symbol gfs () C iss C oss Crss Parameter Forward Transconductance Input Capac itance Output Capacitance Reverse Trans fer Capacitance Test Conditions VDS > I D(on) x R DS(on)max VDS = 25 V f = 1 MHz ID = 40 A VGS = 0 Min. Typ. 25 5900 900 230 Max. Unit S pF pF pF
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ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symbol t d(on) tr (di/ dt)on Parameter Turn-on Time Rise Time Turn-on Current Slope Test Conditions VDD = 30 V ID = 40 A RG = 4.7 V GS = 10 V (see test circuit, figure 3) VDD = 48 V ID = 80 A RG =5 0 VGS = 10 V (see test circuit, figure 5) VDD = 40 V I D = 80 A V GS = 10 V Min. Typ. 32 160 240 Max. 42 200 Unit ns ns A/s
Qg Qgs Qgd
Total Ga te Charge Gate-Source Charge Gate-Drain Charge
230 30 60
280
nC nC nC
SWITCHING OFF
Symbol tr(Vof f) tf tc Parameter Off-volt age Rise Time Fal l Time Cross-over Time Test Conditions VDD = 48 V ID = 40 A V GS = 10 V RG = 4.7 (see test circuit, figure 5) Min. Typ. 35 175 240 Max. 46 230 300 Unit ns ns ns
SOURCE DRAIN DIODE
Symbol I SD ISD M (*) VSD () t rr Qrr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Tim e Reverse Recovery Charge Reverse Recovery Current I SD = 80 A I SD = 80 A VGS = 0 di/dt = 100 A/s 125 0.6 10 Test Conditions Min. Typ. Max. 80 320 1.5 Unit A A V ns C A
VR = 30 V Tj = 150 o C (see test circuit, figure 5)
() Pulsed: Pulse duration = 300 s, duty cycle 1.5% (*) Pulse width limited by safe operating area
Safe Operating Area
Thermal Impedance
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STP80N05-09
Derating Curve Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
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STP80N05-09
Capacitance Variations Normalized Gate Threshold Voltage vs Temperature
Normalized On Resistance vs Temperature
Turn-on Current Slope
Turn-off Drain-source Voltage Slope
Cross-over Time
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STP80N05-09
Switching Safe Operating Area Accidental Overload Area
Source-drain Diode Forward Characteristics
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
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Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And DIode Recovery Times
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TO-220 MECHANICAL DATA
DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147
E
mm TYP. MAX. 4.60 1.32 2.72 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 MIN. 0.173 0.048 0.094 4.40 1.23 2.40
inch TYP. MAX. 0.181 0.051 0.107 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 0.645 0.551 0.116 0.620 0.260 0.154 0.151
A
C
D1
L2 F1
D
G1
Dia. F2 F
L5 L7 L6
L9
L4
G
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H2
P011C
STP80N05-09
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. (c) 1996 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A ...
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