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DUAL N-CHANNEL 30V - 0.017 - 8A SO-8 LOW GATE CHARGE STripFETTM II POWER MOSFET
TYPE STS8DNF3LL
s s s s
STS8DNF3LL
VDSS 30 V
RDS(on) <0.020
ID 8A
TYPICAL RDS(on) = 0.017 OPTIMAL RDS(on) x Qg TRADE-OFF @ 4.5V CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED
DESCRIPTION
This application specific Power MOSFET is the second generation of STMicroelectronis unique "Single Feature SizeTM" strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance.
SO-8
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS s SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS FOR MOBILE PCS
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VDGR VGS Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Single Operation Drain Current (continuous) at TC = 100C Single Operation Drain Current (pulsed) Total Dissipation at TC = 25C Dual operating Total Dissipation at TC = 25C Single operating Value 30 30 16 8 5 32 2 1.6 A Unit V V V
ID
IDM(*) Ptot
A W W 1/8
(*) Pulse width limited by safe operating area. October 2002
.
STS8DNF3LL
THERMAL DATA
Rthj-amb Tj Tstg (*)Thermal Resistance Junction-ambient Thermal Operating Junction-ambient Storage Temperature Single Operating Dual Operating 78 62.5 150 -55 to 150 C/W C/W C C
(*) When mounted on FR-4 board with 0.5 in2 pad of Cu.
ELECTRICAL CHARACTERISTICS (Tcase = 25 C unless otherwise specified) OFF
Symbol V(BR)DSS IDSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating TC = 125C VGS = 16 V Min. 30 1 10 100 Typ. Max. Unit V A A nA
IGSS
ON (*)
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V VGS = 4.5 V ID = 250 A ID = 4 A ID = 4 A Min. 1 0.017 0.020 0.020 0.024 Typ. Max. Unit V
DYNAMIC
Symbol gfs (*) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS=15 V ID = 4 A Min. Typ. 12.5 800 250 60 Max. Unit S pF pF pF
VDS = 25V, f = 1 MHz, VGS = 0
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STS8DNF3LL
ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions ID = 4 A VDD = 15 V RG = 4.7 VGS = 4.5 V (Resistive Load, Figure 1) VDD= 15 V ID= 8 A VGS= 5 V (see test circuit, Figure 2) Min. Typ. 18 32 12.5 3.2 4.5 17 Max. Unit ns ns nC nC nC
SWITCHING OFF
Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions ID = 4 A VDD = 15 V RG = 4.7, VGS = 4.5 V (Resistive Load, Figure 1) Min. Typ. 21 11 Max. Unit ns ns
SOURCE DRAIN DIODE
Symbol ISD ISDM (*) VSD (*) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 8 A VGS = 0 23 17 1.5 Test Conditions Min. Typ. Max. 8 32 1.2 Unit A A V ns nC A
di/dt = 100A/s ISD = 8 A VDD = 15 V Tj = 150C (see test circuit, Figure 3)
(*)Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (*)Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedance
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STS8DNF3LL
Output Characteristics Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
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STS8DNF3LL
Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics
Normalized Breakdown Voltage vs Temperature.
.
.
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Fig. 1: Switching Times Test Circuits For Resistive Load Fig. 2: Gate Charge test Circuit
Fig. 3: Test Circuit For Diode Recovery Behaviour
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STS8DNF3LL
SO-8 MECHANICAL DATA
DIM. MIN. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019
0016023
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STS8DNF3LL
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2002 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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