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 STW18NK80Z
N-channel 800V - 0.34 - 19A - TO-247 Zener-protected SuperMESHTM Power MOSFET
General features
Type STW18NK80Z

VDSS 800V
RDS(on) <0.38
ID 19A
pW 350W
Extremely high dv/dt capability 100% avalanche tested Gate charge minimized Very low intrinsic capacitances Very good manufacturing repeatibility
TO-247
Description
The SuperMESHTM series is obtained through an extreme optimization of ST's well established strip-based PowerMESHTM layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmeshTM products.
Internal schematic diagram
Applications
Switching application
Order codes
Part number STW18NK80Z Marking W18NK80Z Package TO-247 Packaging Tube
October 2006
Rev 4
1/14
www.st.com 14
Contents
STW18NK80Z
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Protection features of gate-to-source zener diodes . . . . . . . . . . . . . . . . . . 4
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Electrical characteristics (curves) ............................. 7
3 4 5
Test circuit
................................................ 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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STW18NK80Z
Electrical ratings
1
Electrical ratings
Table 1.
Symbol VDS VGS ID ID IDM
(1)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate- source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC = 100C Drain current (pulsed) Total dissipation at TC = 25C Derating Factor Value 800 30 19 12 76 350 2.4 6000 4.5 -55 to 150 Max. operating junction temperature Unit V V A A A W W/C V V/ns C
Ptot
VESD(G-S) dv/dt(2) Tstg Tj
Gate source ESD(HBM-C=100pF, R=1.5K) Peak diode recovery voltage slope Storage temperature
1. Pulse width limited by safe operating area. 2. ISD 19A, di/dt 300A/s, VDD VDD < 800V, Tj TJMAX
Table 2.
Rthj-case Rthj-amb TJ
Thermal data
Thermal resistance junction-case max Thermal resistance junction-ambient max Maximum lead temperature for soldering purpose 0.36 50 300 C/W C/W C
Table 3.
Symbol IAR EAS
Avalanche characteristics
Parameter Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) Single pulse avalanche energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) Max value 19 700 Unit A mJ
Table 4.
Symbol BVGSO
Gate-source zener diode
Parameter Gate-source breakdown voltage Test conditions Igs= 1mA (open drain) Min. 30 Typ. Max. Unit V
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Electrical ratings
STW18NK80Z
1.1
Protection features of gate-to-source zener diodes
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components.
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STW18NK80Z
Electrical characteristics
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 5.
Symbol V(BR)DSS
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate-body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 1mA, VGS =0 VDS = max rating VDS = max rating, TC = 125C VGS = 20V VDS = VGS, ID = 150A VGS = 10V, ID = 10A 3 3.75 0.34 Min. 800 1 50 10 4.5 0.38 Typ. Max. Unit V A A A V
IDSS
IGSS VGS(th) RDS(on)
Table 6.
Symbol gfs (1) Ciss Coss Crss Coss eq(2) td(on) tr td(off) tf Qg Qgs Qgd
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Equivalent output capacitance Turn-on delay time Rise time Turn-off delay time Fall time Total gate charge Gate-source charge Gate-drain charge Test conditions VDS = 15V, ID = 10A Min. Typ. 19 6100 500 100 240 46 32 140 32 192 34 102 250 Max. Unit S pF pF pF pF ns ns ns ns nC nC nC
VDS = 25V, f = 1MHz, VGS = 0 VGS = 0V, VDS = 0V to 640V VDD = 400V, ID = 9A RG = 4.7 VGS = 10V (see Figure 13) VDD = 640V, ID = 18A, VGS = 10V (see Figure 14)
1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS.
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Electrical characteristics
STW18NK80Z
Table 7.
Symbol ISD ISDM (1) VSD (2) trr Qrr IRRM trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage ISD = 19A, VGS = 0 920 11 24 1160 15 25.8 Test conditions Min. Typ. Max. 19 76 1.6 Unit A A V ns C A ns C A
Reverse recovery time ISD = 18A, di/dt = 100A/s, Reverse recovery charge VDD = 40V, Tj = 25C Reverse recovery current (see Figure 15) Reverse recovery time ISD = 18A, di/dt = 100A/s, Reverse recovery charge VDD = 40V, Tj = 150C Reverse recovery current (see Figure 15)
1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %
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STW18NK80Z
Electrical characteristics
2.1
Figure 1.
Electrical characteristics (curves)
Safe operating area Figure 2. Thermal impedance
Figure 3.
Output characterisics
Figure 4.
Transfer characteristics
Figure 5.
Transconductance
Figure 6.
Static drain-source on resistance
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Electrical characteristics Figure 7. Gate charge vs gate-source voltage Figure 8. Capacitance variations
STW18NK80Z
Figure 9.
Normalized gate threshold voltage vs temperature
Figure 10. Normalized on resistance vs temperature
Figure 11. Source-drain diode forward characteristics
Figure 12. Normalized breakdown voltage vs temperature
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STW18NK80Z
Test circuit
3
Test circuit
Figure 14. Gate charge test circuit
Figure 13. Switching times test circuit for resistive load
Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit
9/14
Test circuit Figure 17. Unclamped inductive waveform
STW18NK80Z Figure 18. Switching time waveform
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STW18NK80Z
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
STW18NK80Z
TO-247 MECHANICAL DATA
mm. MIN. 4.85 2.20 1.0 2.0 3.0 0.40 19.85 15.45 5.45 14.20 3.70 18.50 3.55 4.50 5.50 3.65 5.50 0.140 0.177 0.216 14.80 4.30 0.560 0.14 0.728 0.143 0.216 TYP MAX. 5.15 2.60 1.40 2.40 3.40 0.80 20.15 15.75 MIN. 0.19 0.086 0.039 0.079 0.118 0.015 0.781 0.608 0.214 0.582 0.17 inch TYP. MAX. 0.20 0.102 0.055 0.094 0.134 0.03 0.793 0.620
DIM. A A1 b b1 b2 c D E e L L1 L2 oP oR S
12/14
STW18NK80Z
Revision history
5
Revision history
Table 8.
Date 21-Jun-2004 17-Oct-2006
Revision history
Revision 3 4 Complete document New template, no content change Changes
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STW18NK80Z
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