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STW54NK30Z
N-CHANNEL 300V - 0.052 - 54A TO-247 Zener-Protected SuperMESHTM MOSFET
Table 1: General Features
TYPE STW54NK30Z
s s s s s s
Figure 1: Package
ID 54 A Pw 300 W
BVDSS 300 V
RDS(on) < 0.060
TYPICAL RDS(on) = 0.052 EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY
TO-247
3 2 1
DESCRIPTION The SuperMESHTM series is obtained through an extreme optimization of ST's well established strip-based PowerMESHTM layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmeshTM products.
Figure 2: Internal Schematic Diagram
APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING DC CHOPPERs s IDEAL FOR OFF-LINE POWER SUPPLIES, ADAPTORS AND PFC
Table 2: Order Codes
SALES TYPE STW54NK30Z MARKING W54NK30Z PACKAGE TO-247 PACKAGING TUBE
Rev. 1 February 2005 1/10
STW54NK30Z
Table 3: Absolute Maximum ratings
Symbol VDS VDGR VGS ID ID IDM ( ) PTOT VESD(G-S) dv/dt (1) Tj Tstg Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Gate source ESD(HBM-C=100pF, R=1.5K) Peak Diode Recovery voltage slope Operating Junction Temperature Storage Temperature Value 300 300 30 54 34 200 300 2.38 6000 4.5 -55 to 150 Unit V V V A A A W W/C V V/ns C
( ) Pulse width limited by safe operating area (1) ISD 54A, di/dt 200A/s, VDD V(BR)DSS, Tj TJMAX. (*) Limited only by maximum temperature allowed
Table 4: Thermal Data
Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 0.42 30 300 C/W C/W C
Table 5: Avalanche Characteristics
Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) Max Value 54 400 Unit A mJ
Table 6: Gate-Source Zener Diode
Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs= 1mA (Open Drain) Min. 30 Typ. Max. Unit V
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components.
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ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) Table 7: On/Off
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 1 mA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 20V VDS = VGS, ID = 150 A VGS = 10V, ID = 27 A 3 3.75 0.052 Min. 300 1 50 10 4.5 0.060 Typ. Max. Unit V A A A V
Table 8: Dynamic
Symbol gfs (1) Ciss Coss Crss Coss eq. (3) td(on) tr td(off) tf Qg Qgs Qgd Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDS = 15 V, ID = 27 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 25 4960 745 186 550 40 45 116 35 158 30 90 221 Max. Unit S pF pF pF pF ns ns ns ns nC nC nC
VGS = 0V, VDS = 0V to 240 V VDD = 150 V, ID = 27 A RG = 4.7 VGS = 10 V (Resistive Load see, Figure 3) VDD = 240V, ID = 54A, VGS = 10V
Table 9: Source Drain Diode
Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 54 A, VGS = 0 ISD = 54 A, di/dt = 100A/s VDD = 100 V, Tj = 25C (see test circuit, Figure 5) ISD = 54 A, di/dt = 100A/s VDD = 100 V, Tj = 150C (see test circuit, Figure 5) 328 2.8 17.2 416 4.2 20.2 Test Conditions Min. Typ. Max. 54 200 1.6 Unit A A V ns C A ns C A
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS.
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Figure 3: Safe Operating Area Figure 6: Thermal Impedance
Figure 4: Output Characteristics
Figure 7: Transfer Characteristics
Figure 5: Transconductance
Figure 8: Static Drain-source On Resistance
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Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations
Figure 10: Normalized Gate Thereshold Voltage vs Temperature
Figure 13: Normalized On Resistance vs Temperature
Figure 11: Source-Drain Diode Forward Characteristics
Figure 14: Normalized BVdss vs Temperature
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Figure 15: Avalanche Energy vs Starting Tj
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Figure 16: Unclamped Inductive Load Test Circuit Figure 19: Unclamped Inductive Wafeform
Figure 17: Switching Times Test Circuit For Resistive Load
Figure 20: Gate Charge Test Circuit
Figure 18: Test Circuit For Inductive Load Switching and Diode Recovery Times
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TO-247 MECHANICAL DATA
mm. MIN. 4.85 2.20 1.0 2.0 3.0 0.40 19.85 15.45 5.45 14.20 3.70 18.50 3.55 4.50 5.50 3.65 5.50 0.140 0.177 0.216 14.80 4.30 0.560 0.14 0.728 0.143 0.216 TYP MAX. 5.15 2.60 1.40 2.40 3.40 0.80 20.15 15.75 MIN. 0.19 0.086 0.039 0.079 0.118 0.015 0.781 0.608 0.214 0.582 0.17 inch TYP. MAX. 0.20 0.102 0.055 0.094 0.134 0.03 0.793 0.620
DIM. A A1 b b1 b2 c D E e L L1 L2 oP oR S
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Table 10: Revision History
Date 31-Jan-2005 Revision 1 Complete datasheet Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
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