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| PRELIMINARY DATA SHEET For information only DC-DC Converter Control and Synchronous AceFETTM TS12N30CS - 30V Single N-Channel 4.5V Specified AceFETTM General Description Taiwan Semiconductor's new low cost, state of the art AceFETTM lateral MOSFET process technology in chipscale bondwireless packaging minimizes PCB space and RDS(ON) plus provides an ultralow Qg X RDS(ON) figure of merit. Ds D G S Features * 12A, 30V * 12A, 30V RDS(ON) = 6m Qg at 4.5 Volts = 15nC at 4.5 Volts AceFETTM for High Frequency DC-DC Converters * Low profile package: less than 1mm height when mounted on PCB * Occupies only 1/3 the area of SO-8. * Excellent thermal characteristics. * High power and current handling capability. * Lead free solder balls available. Patent Pending D S D S D S S D S D S D D S D S D S S D S D S D D S D S D S S D G Ds S D Bottom: Bump Side Absolute Maximum Ratings Symbol Parameter VDSS VGSS ID PD TJ, TSTG TA=25C unless otherwise noted Ratings 30 +12 6 25 2.2 -55 to +150 Units V V A W C Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed Power Dissipation (Steady State) Operating and Storage Junction Temperature Range Thermal Characteristics RJA RJR RJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Ball Thermal Resistance, Junction-to-Case 1 56 4.5 0.6 C/W 6/19/03 Rev0 PRELIMINARY DATA SHEET Electrical Characteristics Symbol BVDSS IGSS IDSS IDDS RDS (on) TA=25C unless otherwise specified Parameter Drain-Source Breakdown Voltage Gate-Body Leakage Zero Gate Voltage Drain Current Drain to Drain Sense Leakage Static Drain-Source On-Resistance Test Condition VGS = 0 V, ID= 250 uA Min Typ. Max 30 +150 250 250 6 210 1.3 15 0.4 650 1500 220 40 0.75 25 2.5 Units V nA uA uA m m V nC Ohms pF pF pF ns V A mJ TS12N30CS VGS = +12, VDS=0V Tj = 150C, VDS =30V , VGS=0 V Tj = 150C, VDS =30V , VGS=0 V VGS = 4.5 V, ID = 12A VGS = 4.5 V, ID = 0.35A VDS = VGS , ID = 250uA VDS = 30V , VGS = 4.5V, ID=12A VDS = 0V , f = 1MHz VDS = 30V , VGS = 0V, f = 1MHz VDS = 30V , VGS = 0V, f = 1MHz VDS = 30V , VGS = 0V, f = 1MHz If = 12A , di/dt = 100A / us Tj = 150C IS = 12A, VGS = 0V VGS = 4.5V , VDS = 1V RDSDS (on) Drain Sense On-Resistance VGS (th) Qg Rg Coss Ciss Crss trr VSD ID(on) Eas Gate Threshold Voltage Total Gate Charge Gate Resistance Output Capacitance Input Capacitance Reverse transfer capacitance Reverse Recovery time Source-Drain Diode Forward On-Voltage Source-Drain Diode On-State Drain Current Avalanche Energy UIS Single Pulse 10us , VDS> BVDSS 2 6/19/03 Rev0 PRELIMINARY DATA SHEET Dimensional Outline and Pad Layout TS12N30CS SILICON 0.27mm 1.00mm MAX 3.08mm 0.29mm 0.50mm 3.08mm Bump O 0.37mm 0.50mm 0.29mm Bumps are Lead Free solder 96.8 Sn / 2.6 Ag / 0.6 Cu 3 6/19/03 Rev0 PRELIMINARY DATA SHEET Dimensional Outline and Pad Layout TS12N30CS O 0.25mm S D G Ds S D S D S D S D S D S D S D S D S D S D S D S D S D D = Drain Pad Ds = Drain Sense Pad S = Source Pad G = Gate Pad Solder Mask O ~ 0.35mm 0.50mm D S D S D S 0.50mm LAND PATTERN RECOMMENDATION 30XXX MARK ON BACKSIDE OF DIE XXX = Date/Lot Traceability Code 4 6/19/03 Rev0 |
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