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TS8MED3260G
32MB 72-PIN EDO SIMM With 16Mx8 3.3VOLT Features
* * * * * Fast Page Mode with Extended Data Out Single +5.0V 10% power supply. 2,048 cycles refresh. Lower power consumption. CAS before RAS refresh, RAS only refresh, Hidden refresh, Fast Page Mode with EDO, Read_Modify_Write capability. *
Description
The TS8MED3260G is a 8M by 32-bit dynamic RAM module with 16 pcs of 4Mx4 DRAMs assembled on the printed circuit board. The TS8MED3260G is optimized for application to systems which require high density and large capacity along with compact sizing.
Placement
DRAM Status : GM71C17403CJ-60 M5M417405CJ-6 NT5117405BJ-60
B C
HM5117405S-6 TS8MED3260G Access time from /RAS tRAC Access time from /CAS tCAC Random read/write cycle time tRC Hyper page mode cycle time tHPC 60ns 15ns 104ns 25ns
A
Dimensions
Side A D C B B C D G F E H E F G H Millimeters 107.95 0.500 6.35 3.38 2.03 21.60 0.500 10.16 6.35 1.27 0.080 Inches 4.520 0.020 0.250 0.133 0.080 0.850 0.020 0.400 0.250 0.050 0.003
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TS8MED3260G
32MB 72-PIN EDO SIMM With 16Mx8 3.3VOLT
TS8MED3260G-- Block Diagram
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 D3 D2 D1 D0 A0-A10 /RAS /CAS /WE D3 D2 D1 D0 A0-A10 /RAS /CAS /WE DQ28 DQ29 DQ30 DQ31 D3 D2 D1 D0 A0-A10 /RAS /CAS /WE D3 D2 D1 D0 A0-A10 /RAS /CAS /WE DQ0 DQ1 DQ2 DQ3 D3 D2 D1 D0 DQ4 DQ5 DQ6 DQ7 D3 D2 D1 D0
D3 D2 D1 D0
D3 D2 D1 D0
D3 D2 D1 D0
D3 D2 D1 D0
A0-A10 /RAS0 /CAS0 /WE /CAS1 /RAS2 /CAS2 /CAS3 /RAS3
A0-A10 /RAS /CAS /WE
A0-A10 /RAS /CAS /WE
A0-A10 /RAS /CAS /WE
A0-A10 /RAS /CAS /WE
A0-A10 /RAS /CAS /WE
A0-A10 /RAS /CAS /WE
/RAS1
A0-A10 /RAS /CAS /WE
D3 D2 D1 D0
A0-A10 /RAS /CAS /WE
D3 D2 D1 D0
A0-A10 /RAS /CAS /WE
D3 D2 D1 D0
A0-A10 /RAS /CAS /WE
D3 D2 D1 D0
A0-A10 /RAS /CAS /WE
D3 D2 D1 D0
A0-A10 /RAS /CAS /WE
D3 D2 D1 D0
Pinouts
Pin No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name Vss DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 Vcc NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ20 DQ5 DQ21 DQ6 Pin No 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name DQ22 DQ7 DQ23 A7 NC Vcc A8 A9 /RAS3 /RAS2 NC NC NC NC Vss /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 /RAS1 NC /WE NC Pin No 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 Vcc DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC Vss
Pin Identification
Symbol A0 ~ A10 DQ0 ~ DQ31 /RAS0 ~ /RAS3 /CAS0 ~ /CAS3 /WE Vcc Vss NC PD1 ~ PD4 Function Address inputs Common data inputs/outputs Row address strobes Column address strobes Write enable +5.0 Volt power supply Ground No connection Presence detection pin
This technical information is based on industry standard data and tests believed to be reliable. However , Transcend makes no warranties, either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice.
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TS8MED3260G
32MB 72-PIN EDO SIMM With 16Mx8 3.3VOLT
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on Vcc supply to Vss Storage temperature Power dissipation Short circuit current Note: Symbol VIN, VOUT Vcc TSTG PD IOS Value -1.0~+7.0 -1.0~+7.0 -55~+150 16 50 Unit V V C W mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to Vss , TA = 0 to 70) Parameter Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 4.5 0 2.4 -1.0*
2
Typ 5.0 0 -
Max 5.5 0 Vcc+1* 0.8
1
Unit V V V V
Note: 1. Vcc +2.0V/20ns, Pulse width is, measured at Vcc . 2. -2.0V/20ns, Pulse width is measured at Vcc.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH Min -80 -10 2.4 Max 816 32 816 816 16 816 80 10 0.4 Unit mA mA mA mA mA mA uA uA V V
VOL ICC1: Operating Current* (/RAS, /CAS, Address cycling @tRC=min) ICC2: Standby Current (/RAS=/CAS=/W=VIH)
Transcend Information Inc.
TS8MED3260G
32MB 72-PIN EDO SIMM With 16Mx8 3.3VOLT
ICC3: /RAS only Refresh Current* (/CAS=VIH, /RAS cycling @tRC=min) ICC4: Fast Page Mode Current* (/RAS=VIL, /CAS Address cycling: tPC=min) ICC5: Standby Current (/RAS=/CAS=/W=VCC-0.2V) ICC6: /CAS-Before-/RAS Refresh Current* (/RAS and /CAS cycling @tRC=min) LI(L): Input Leakage Current (Any input 0VINVCC+0.5V, all other pins not under test=0V) IO(L): Output Leakage Current (Data Out is disabled, 0VVOUTVCC) VOH: Output High Voltage Level (IOH= -5mA) VOL: Output Low Voltage Level (IOL=4.2mA) Note: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one mode cycle, tPC.
CAPACITANCE (TA = 25C, Vcc = 5V, f = 1MHz)
Item Input capacitance (A0~A10) Input capacitance (/WE) Input capacitance (/RAS0, /RAS2) Input capacitance (/CAS0~/CSA3) Data input/output capacitance (DQ0~DQ31) Symbol CIN1 CIN2 CIN3 CIN4 CDQ Min Max 100 130 35 30 20 Unit pF pF pF pF pF
AC CHARACTERISTICS (0TA70, Vcc=5.0V%, See notes 1, 2)
Test condition: VIH/VIL=2.4V/0.8V, VOH/VOL=2.4V/0.4V, Output loading CL=100pF Parameter Random read or write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS to /CAS delay time Symbol tRC tRAC tCAC tCLZ tRC tOFF tT tRP tRAS tRSH tCSH tCAS tRCD 0 0 3 40 60 15 60 10 20 10K 45 10K 15 50 Min 110 60 15 30 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 4 3,4 3,4,5 3,10 3 6 2 Note
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TS8MED3260G
/RAS to column address delay time /CAS to /RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to /RAS lead time Read command set-up time Read command hold referenced to /CAS Read command hold referenced to /RAS Write command hold time Write command pulse width Write command to /RAS lead time Write command to /CAS lead time Date-in set-up time Date-in hold time Refresh period Write command set-up time /CAS setup time (/CAS-before-/RAS referesh) /CAS hold time (/CAS-before-/RAS referesh) /RAS precharge to /CAS hold time Access time from /CAS precharge Fast page mode cycle time /CAS precharge time (Fast page cycle) /RAS pulse width (Fast page cycle) /W to /RAS precharge time (C-B-R refresh) /W to /RAS hold time (C-B-R refresh) /CAS precharge (C-B-R counter test) Hold time /CAS low to /CAS high tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCSR tCHR tRPC tCPA tPC tCP tRASP tWRP tWRH tCPT tCLCH 40 10 60 10 10 20 5 0 5 10 5 15 5 0 10 0 10 30 0 0 0 10 10 15 10 0 10
32MB 72-PIN EDO SIMM With 16Mx8 3.3VOLT
30 ns ns ns ns ns 10
ns ns ns ns ns ns ns ns ns 32 ns ns ns ns ns 35 ns ns ns 200K ns ns ns ns ns 11 3 7 9 9 8 8
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TS8MED3260G
refresh cycles before proper device operation is achieved.
32MB 72-PIN EDO SIMM With 16Mx8 3.3VOLT
Note: 1. An initial pause of 200us is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS
2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 7. tWCS is non-restrictive operating parameter. It included in the data sheet as electrical characteristics only. If tWCStWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are refernced to the /CAS leading edge in early write cycle. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be me. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. In order to hold the address latched by the first /CAS going low, the parameter Tclch must be met.
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