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VN5016AJ-E
SINGLE CHANNEL HIGH SIDE DRIVER WITH ANALOG CURRENT SENSE FOR AUTOMOTIVE APPLICATIONS
ADVANCE DATA Table 1. General Features TYPE
VN5016AJ-E
Figure 1. Package RDS(on) 16m ID 40A
VCC 41V
OUTPUT CURRENT: 40A 3.0V CMOS COMPATIBLE INPUT CURRENT SENSE DISABLE PROPORTIONAL LOAD CURRENT SENSE UNDERVOLTAGE SHUT-DOWN OVERVOLTAGE CLAMP THERMAL SHUT DOWN CURRENT AND POWER LIMITATION

PowerSSO-12
VERY LOW STAND-BY CURRENT PROTECTION AGAINST LOSS OF GROUND AND LOSS OF VCC VERY LOW ELECTROMAGNETIC SUSCEPTIBILITY OPTIMIZED ELECTROMAGNETIC EMISSION REVERSE BATTERY PROTECTION (*) IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE
DESCRIPTION The VN5016AJ-E is a monolithic device made using STMicroelectronics VIPower technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table).
This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the CURRENT SENSE pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shut-down intervention. Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears.
Table 2. Order Codes
Package PowerSSO-12
Note: (*) See application schematic at page 8
Tube VN5016AJ-E
Tape and Reel VN5016AJTR-E
Rev. 2 January 2005
This is preliminary information on a new product now in development. Details are subject to change without notice.
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Figure 2. Block Diagram
VCC
VCC CLAMP
UNDERVOLTAGE PwCLAMP
DRIVER
OUTPUT ILIM VDSLIM
GND LOGIC INPUT PwrLIM
OVERTEMP. IOUT CS_DIS K CURRENT SENSE
Table 3. Pin Function
Name VCC OUTPUT GND INPUT CURRENT SENSE CS_DIS Battery connection Power output Ground connection. Must be reverse battery protected by an external diode/resistor network Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state Analog current sense pin, delivers a current proportional to the load current Active high CMOS compatible pin, to disable the current sense pin Function
Figure 3. Current and Voltage Conventions
IS
VCC
VF
VCC
ICSD VCSD
IOUT CS_DIS OUTPUT VOUT
IIN INPUT CURRENT SENSE VIN VSENSE GND IGND ISENSE
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Figure 4. Configuration Diagram (Top View) & Suggested Connections For Unused and n.c. Pins
TAB = V cc
VCC GND INPUT CURRENT SENSE CS_DIS VCC
1 2 3 4 5 6
12 11 10 9 8 7
OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT
Connection / Pin Current Sense Floating To Ground Through 1K resistor
N.C. X X
Output X
Input X Through 10K resistor
CS_DIS X Through 10K resistor
Table 4. Absolute Maximum Ratings
Symbol VCC -VCC - IGND IOUT - IOUT IIN ICSD VCSENSE VESD Tj Tstg DC supply voltage Reverse DC supply voltage DC reverse ground pin current DC output current Reverse DC output current DC input current DC current sense disable input current Current sense maximum voltage Electrostatic discharge (R=1.5k; C=100pF) Junction operating temperature Storage temperature Parameter Value 41 -0.3 -200 Internally limited -30 -1 to 10 -1 to 10 VCC-41 +VCC 2000 -40 to 150 -55 to 150 Unit V V mA A A mA mA V V V C C
Table 5. Thermal Data
Symbol Rthj-case Rthj-amb Parameter Thermal resistance junction-case Thermal resistance junction-ambient
0.5cm2
Max Value 2.3 75 (see note 1)
of Cu (at least 35 m thick) connected to TAB.
Unit C/W C/W
Note: 1. When mounted on a standard single-sided FR4 board with
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ELECTRICAL CHARACTERISTICS (8VSymbol VCC VUSD VUSDhyst Parameter Operating supply voltage Undervoltage shutdown Undervoltage Shut-down hysteresis IOUT=5A; Tj=25C RON Vclamp IS On state resistance Clamp Voltage Supply current IOUT=5A; Tj=150C IOUT=5A; VCC=5V; Tj=25C IS=20mA Off State; VCC=13V; Tj=25C; VIN=VOUT=VSENSE=VCSD=0V On State; VCC=13V; VIN=5V; IOUT=0A IL(off) Off state output current VIN=VOUT=0V; VCC=13V; Tj=25C VIN=VOUT=0V; VCC=13V; Tj=125C 0 0 41 46 2(**) 1.5 Test Conditions Min. 4.5 Typ. 13 3 0.5 16 32 20 52 5(**) 3 3 5 Max. 36 4.5 Unit V V V m m m V A mA A
Note: (**) PowerMOS leakage included
Table 7. Switching (VCC=13V)
Symbol td(on) td(off) (dVOUT/dt)on (dVOUT/dt)off WON WOFF Parameter Turn-on delay time Turn-off delay time Turn-on voltage slope Turn-off voltage slope Switching losses energy at turn-on Switching losses energy at turn-off RL=2.6 RL=2.6 RL=2.6 RL=2.6 RL=2.6 RL=2.6 Test Conditions Min. Typ. 15 40 0.3 0.35 TBD TBD Max. Unit s s V/s V/s mJ mJ
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ELECTRICAL CHARACTERISTICS (continued) Table 8. Logic Input
Symbol VIL IIL VIH IIH VI(hyst) VICL VCSDL ICSDL VCSDH ICSDH VCSD(hyst) VCSCL Parameter Input low level voltage Low level input current Input high level voltage High level input current Input hysteresis voltage Input clamp voltage CS_DIS low level voltage Low level CS_DIS current CS_DIS high level voltage High level CS_DIS current CS_DIS hysteresis voltage CS_DIS clamp voltage ICSD=1mA ICSD=-1mA VCSD=2.1V 0.25 5.5 -0.7 TBD VCSD=0.9V 1 2.1 10 IIN=1mA IIN=-1mA VIN=2.1V 0.25 5.5 -0.7 0.9 TBD VIN=0.9V 1 2.1 10 Test Conditions Min. Typ. Max. 0.9 Unit V A V A V V V V A V A V V V
Table 9. Protections and Diagnostics (see note 2)
Symbol IlimH IlimL TTSD TR TRS THYST VDEMAG VON Parameter DC Short circuit current Short circuit current during thermal cycling Shutdown temperature Reset temperature Thermal reset of STATUS Thermal hysteresis (TTSD-TR) Turn-off output voltage clamp Output voltage drop limitation IOUT=2A; VIN=0; L=6mH IOUT=0.3A; Tj= -40C...+150C (see figure 9) VCC-41 VCC=13V 5VNote: 2. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles
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ELECTRICAL CHARACTERISTICS (continued) Table 10. Current Sense (8VSymbol K1 Parameter IOUT/ISENSE Test Conditions IOUT =1.5A; VSENSE=0.5V; VCSD=0V; Tj= -40C...150C IOUT =10A; VSENSE=4V; VCSD=0V; K2 IOUT/ISENSE Tj=-40C Tj=25C...150C IOUT =25A; VSENSE=4V; VCSD=0V; K3 IOUT/ISENSE Tj=-40C Tj=25C...150C IOUT =0A; VSENSE=0V; ISENSE0 Analog sense current Max analog sense output voltage Analog sense output voltage in overtemperature condition Analog sense output current in overtemperature condition Delay Response time from falling edge of CS_DIS pin Delay Response time from rising edge of CS_DIS pin Delay Response time from rising edge of INPUT pin Delay Response time from falling edge of INPUT pin VCSD=5V; VIN=0V; Tj=-40C...150C VCSD=0V; VIN=5V; Tj=-40C...150C VSENSE IOUT =15A; VCSD=0V; RSENSE=3.9K 0 0 5 5 10 A A V TBD TBD 5000 5000 TBD TBD TBD TBD 5000 5000 TBD TBD Min. TBD Typ. 5000 Max. TBD Unit
VSENSEH
VCC=13V; RSENSE=3.9K
9
V
ISENSEH
VCC=13V, VSENSE=5V VSENSE<4V, VSENSE<4V, VSENSE<4V, VSENSE<4V, 1.5A8
mA s s s s
tDSENSE1H tDSENSE1L tDSENSE2H tDSENSE2L
ISENSE=90% of ISENSE max (see fig 5) ISENSE=10% of ISENSE max (see fig 5) ISENSE=90% of ISENSE max (see fig 5) ISENSE=10% of ISENSE max (see fig 5)
50 5 270 100
100 20 600 250
Table 11. Truth Table
CONDITIONS Normal operation Overtemperature Undervoltage Short circuit to GND Short circuit to VCC Negative output voltage clamp INPUT L H L H L H L H L H L OUTPUT L H L L L L L L H H L SENSE (VCSD=0V) (see note 3) 0 Nominal 0 VSENSEH 0 0 0 0 0 < Nominal 0
Note: 3. If the VCSD is high, the SENSE output is at a high impedance.
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Figure 5.
INPUT CS_DIS LOAD CURRENT SENSE CURRENT
tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L
Figure 6. Switching Characteristics
VOUT
80% dVOUT/dt(on) tr 10%
90% dVOUT/dt(off) tf t
INPUT td(on) td(off)
t
Table 12. Electrical Transient Requirements
ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E I -25 V +25 V -25 V +25 V -4 V +26.5 V II -50 V +50 V -50 V +50 V -5 V +46.5 V TEST LEVELS III -75 V +75 V -100 V +75 V -6 V +66.5 V TEST LEVELS RESULTS II III C C C C C C C C C C E E IV -100 V +100 V -150 V +100 V -7 V +86.5 V Delays and Impedance 2 ms 10 0.2 ms 10 0.1 s 50 0.1 s 50 100 ms, 0.01 400 ms, 2
I C C C C C C
IV C C C C C E
CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
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Figure 7. Application Schematic
+5V
VCC Rprot CS_DIS Dld C Rprot Rprot CURRENT SENSE GND RSENSE RGND VGND DGND INPUT OUTPUT
Note: Channel 2 has the same internal circuit as channel 1.
GND PROTECTION REVERSE BATTERY
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / (IS(on)max). 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line.
A resistor (RGND=1k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table.
C I/Os PROTECTION:
If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k. Recommended Rprot value is 10k.
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Figure 8. Waveforms
NORMAL OPERATION INPUT CS_DIS LOAD CURRENT SENSE CURRENT UNDERVOLTAGE
VUSDhyst
VCC INPUT CS_DIS LOAD CURRENT SENSE CURRENT
VUSD
SHORT TO VCC INPUT CS_DIS LOAD VOLTAGE LOAD CURRENT SENSE CURRENT
OVERLOAD OPERATION Tj INPUT CS_DIS LOAD CURRENT SENSE CURRENT
TR TTSD TRS
ILIMH ILIML VSENSEH
current power limitation limitation
thermal cycling SHORTED LOAD NORMAL LOAD
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Figure 9. Vcc-Vout
Tj=150oC Tj=25oC Tj=-40oC
Von Iout
Von/Ron(T)
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PACKAGE MECHANICAL Table 13. PowerSSO-12TM Mechanical Data
Symbol A A1 A2 B C D E e H h L k X Y ddd 5.800 0.250 0.400 0 1.900 3.600 millimeters Min 1.250 0.000 1.100 0.230 0.190 4.800 3.800 0.800 6.200 0.500 1.270 8 2.500 4.200 0.100 Typ Max 1.620 0.100 1.650 0.410 0.250 5.000 4.000
Figure 10. PowerSSO-12TM Package Dimensions
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REVISION HISTORY Table 14. Revision History
Date Oct. 2004 Jan. 2005 Revision 1 2 - First issue. - Minor text changes. Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2004 STMicroelectronics - All rights reserved
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