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(R) P
VNQ600AP
QUAD CHANNEL HIGH SIDE SOLID STATE RELAY
TYPE VNQ600AP
(*) Per each channel
RDS(on) (*) 35m
Ilim 22A
VCC 36 V
DC SHORT CIRCUIT CURRENT: 22A s CMOS COMPATIBLE INPUTS s PROPORTIONAL LOAD CURRENT SENSE s UNDERVOLTAGE & OVERVOLTAGE
s
SO-28 (DOUBLE ISLAND) ORDER CODES
PACKAGE SO-28 TUBE VNQ600AP T&R VNQ600AP13TR
nSHUT-DOWN
OVERVOLTAGE CLAMP THERMAL SHUT-DOWN s CURRENT LIMITATION s VERY LOW STAND-BY POWER DISSIPATION s PROTECTION AGAINST: nLOSS OF GROUND & LOSS OF VCC s REVERSE BATTERY PROTECTION (**)
s s
DESCRIPTION The VNQ600AP is a quad HSD formed by ABSOLUTE MAXIMUM RATING
Symbol VCC -VCC IOUT IR IIN VCSENSE IGND
assembling two VND600 chips in the same SO-28 package. The VND600 is a monolithic device designed in| STMicroelectronics VIPower M0-3 Technology. The VNQ600A is intended for driving any type of multiple loads with one side connected to ground. This device has four independent channels and four analog sense outputs which deliver currents proportional to the outputs currents. Active current limitation combined with thermal shut-down and automatic restart protect the device against overload. Device automatically turns off in case of ground pin disconnection.
Parameter Supply voltage (continuous) Reverse supply voltage (continuous) Output current (continuous), for each channel Reverse output current (continuous), for each channel Input current Current sense maximum voltage Ground current at Tpins < 25C (continuous) Electrostatic Discharge (Human Body Model: R=1.5K; C=100pF) - INPUT - CURRENT SENSE - OUTPUT - VCC Maximum Switching Energy (L=0.11mH; RL=0; Vbat=13.5V; Tjstart=150C; IL=40A) Power dissipation (per island) at Tlead=25C Junction operating temperature Storage temperature
Value 41 -0.3 15 -15 +/- 10 -3 +15 -200 4000 2000 5000 5000 126 6.25 Internally Limited -55 to 150
Unit V V A A mA V V mA V V V V mJ W C C
VESD
EMAX Ptot Tj Tstg
(**) See application schematic at page 9.
April 2004
1/18
VNQ600AP
BLOCK DIAGRAM
VCC 1,2
OVERVOLTAGE UNDERVOLTAGE DEMAG 1
DRIVER 1
OUTPUT 1 ILIM1
INPUT 1 LOGIC INPUT 2 GND 1,2 OVERTEMP. 1 OVERTEMP. 2 IOUT2
DRIVER 2
IOUT1
K
CURRENT SENSE 1 OUTPUT 2
DEMAG 2 ILIM2 K CURRENT SENSE 2
OVERVOLTAGE UNDERVOLTAGE DEMAG 3
DRIVER 3
VCC 3,4
OUTPUT 3 ILIM3
INPUT 3 LOGIC INPUT 4 GND 3,4 OVERTEMP. 3 OVERTEMP. 4 IOUT4
DRIVER 4
IOUT3
K
CURRENT SENSE 3 OUTPUT 4
DEMAG 4 ILIM4 K CURRENT SENSE 4
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VNQ600AP
CURRENT AND VOLTAGE CONVENTIONS
IS1,2 IS3,4 VCC1,2 VCC3,4 IOUT1 OUTPUT1 IOUT2 OUTPUT2 OUTPUT3 IOUT3 IOUT4 OUTPUT4 VOUT4 GND3,4 IGND1,2 VOUT3 VOUT1 VOUT2
VCC1,2 IIN1 VIN1 VSENSE1 VIN2 VSENSE2 VIN3 ISENSE1 IIN2 ISENSE2 IIN3 ISENSE3 INPUT1 CUR. SENSE1 INPUT2 CUR. SENSE2 INPUT3 CUR. SENSE3 INPUT4 CUR. SENSE4 GND1,2
VCC3,4
VSENSE3 IIN4 VIN4 ISENSE4 VSENSE4
IGND3,4
CONNECTION DIAGRAM (TOP VIEW)
VCC1,2 GND 1,2 INPUT2 INPUT1 CURRENT SENSE 1 CURRENT SENSE 2 VCC1,2 VCC3,4 GND 3,4 INPUT4 INPUT3 CURRENT SENSE 3 CURRENT SENSE 4 VCC3,4
1
28
VCC1,2 OUTPUT 1 OUTPUT 1 OUTPUT 1 OUTPUT 2 OUTPUT 2 OUTPUT 2 OUTPUT 3 OUTPUT 3 OUTPUT 3 OUTPUT 4 OUTPUT 4 OUTPUT 4
14
15
VCC3,4
3/18
VNQ600AP
THERMAL DATA (Per island)
Symbol Rthj-lead Rthj-amb Rthj-amb Parameter Thermal resistance Junction-lead Thermal resistance Junction-ambient (one chip ON) Thermal resistance Junction-ambient (two chips ON) Value 20 60 (*) 46 (*) Unit C/W C/W C/W
(*) When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow.
ELECTRICAL CHARACTERISTICS (8VSymbol VCC (**) VUSD (**) VOV (**) RON Vclamp Parameter Operating supply voltage Undervoltage shut-down Overvoltage shut-down On state resistance Clamp Voltage Test Conditions Min 5.5 3 36 Typ 13 4 Max 36 5.5 35 70 41 48 12 12 120 55 40 25 6 50 5 3 Unit V V V m m m V A A mA A A A
IOUT 1,2,3,4=5A; Tj=25C IOUT 1,2,3,4=5A; Tj=150C IOUT 1,2,3,4=3A; VCC=6V ICC=20mA (see note 1) Off State; VCC=13V; VIN=VOUT=VSENSE=0V IS (**) Supply current Off State; VCC=13V; VIN=VOUT=VSENSE=0V; Tj =25C On State; VCC=13V; VIN=5V; IOUT =0A; RSENSE=3.9K; VSENSE=0V IL(off1) IL(off3) IL(off4) Off state output current Off State Output Current Off State Output Current VIN=VOUT=VSENSE=0V VIN=VOUT=VSENSE=0V; VCC=13V; Tj =125C VIN=VOUT=VSENSE=0V; VCC=13V; Tj =25C 0
PROTECTIONS
Symbol Ilim TTSD TR Thyst Vdemag VON
(**) Per island
Parameter DC Short circuit current Thermal shut-down temperature Thermal reset temperature Thermal hysteresis Turn-off output voltage clamp Output voltage drop limitation VCC=13V
Test Conditions 5.5VMin 22
Typ 40
Max 70 70
Unit A A C C
150 135 7 IOUT=2A; L=6mH IOUT=0.5A; Tj= -40C...+150C
175
200
15
C V mV
VCC-41 VCC-48 VCC-55 50
4/18
1
VNQ600AP
ELECTRICAL CHARACTERISTICS (continued) SWITCHING (V CC=13V)
Symbol tD(on) tD(off) (dVOUT /dt)on (dVOUT /dt)off Parameter Turn-on delay time Turn-off delay time Turn-on voltage slope Turn-off voltage slope Test Conditions RL=2.6 channels 1,2,3,4 (see fig. 1) RL=2.6 channels 1,2,3,4 (see fig. 1) RL=2.6 channels 1,2,3,4 (see fig. 1) RL=2.6 channels 1,2,3,4 (see fig. 1) Min Typ 40 40 0.20 0.20 Max Unit s s V/s V/s
CURRENT SENSE (9V < VCC< 16V) (See Fig. 3)
Symbol K1 K2 K3 Parameter IOUT/ISENSE IOUT/ISENSE IOUT/ISENSE Test Conditions IOUT1,2=0.35A; VSENSE=0.5V; Tj= -40C...+150C IOUT=2A; VSENSE=2.5V; Tj=-40C Tj= 25C...+150C IOUT=4A; VSENSE=4V; Tj=-40C Tj= 25C...+150C VCC=5.5V; IOUT1,2=2A; RSENSE=10K VCC>8V; IOUT1,2=4A; RSENSE=10K VSENSEH RVSENSEH tDSENSE Analog sense output voltage in overtemperature condition Analog Sense Output Impedance in Overtemperature Condition Current sense delay response VCC=13V; RSENSE=3.9K VCC=13V; Tj>TTSD; All channels open to 90% ISENSE (see note 2) Min 3100 3750 4000 4000 4100 2 4 5 400 500 Typ 4150 4600 4600 4500 4500 Max 5560 5700 5400 5200 5150 V V V s Unit
VSENSE1,2
Max analog sense output voltage
LOGIC INPUT
Symbol VIL VIH VI(hyst) IIL IIH VICL Parameter Low level input voltage High level input voltage Input hysteresis voltage Low level input current High level input current Input clamp voltage Test Conditions Min 3.25 0.5 20 6 Typ Max 1.25 Unit V V V A A V V
VIN=1.25V VIN=3.25V IIN=1mA IIN= -1mA
65 75 6.8 -0.7
110 8
VCC - OUTPUT DIODE
Symbol VF Parameter Forward on Voltage Test Conditions -IOUT=2.5A; Tj=150C Min Typ Max 0.9 Unit V
Note 1: V clamp and VOV are correlated. Typical difference is 5V. Note 2: current sense signal delay after positive input slope. Note: Sense pin doesn't have to be left floating.
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VNQ600AP
TRUTH TABLE (per channel)
CONDITIONS Normal operation Overtemperature Undervoltage Overvoltage INPUT L H L H L H L H L H H L H L OUTPUT L H L L L L L L L L L H H L SENSE 0 Nominal 0 VSENSEH 0 0 0 0 0 (TjTTSD) VSENSEH 0 < Nominal 0
Short circuit to GND
Short circuit to VCC Negative output voltage clamp
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VNQ600AP
ELECTRICAL TRANSIENT REQUIREMENTS
ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 Class C E Test Levels I -25V +25V -25V +25V -4V +26.5V Test Levels II -50V +50V -50V +50V -5V +46.5V Test Levels III -75V +75V -100V +75V -6V +66.5V Test Levels IV -100V +100V -150V +100V -7V +86.5V Test Levels Result III C C C C C E Test Levels Delays and Impedance 2ms, 10 0.2ms, 10 0.1s, 50 0.1s, 50 100ms, 0.01 400ms, 2 Test Levels Result IV C C C C C E
Test Levels Result I C C C C C C
Test Levels Result II C C C C C E
Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device.
Figure 1: Switching Characteristics (Resistive load R L=2.6)
VOUT
80% dVOUT/dt(on) tr ISENSE 90% 10%
90% dVOUT/dt(off) tf t
INPUT
tDSENSE
t td(off)
td(on)
t
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1
VNQ600AP
Figure 2: Waveforms (per each chip)
NORMAL OPERATION INPUTn LOAD CURRENTn SENSEn
UNDERVOLTAGE VCC INPUTn LOAD CURRENTn SENSEn OVERVOLTAGE
VOV VUSD VUSDhyst
VCC INPUTn LOAD CURRENTn SENSEn
VCC < VOV
VCC > VOV
SHORT TO GROUND INPUTn LOAD CURRENTn LOAD VOLTAGEn SENSEn
SHORT TO VCC INPUTn LOAD VOLTAGEn LOAD CURRENTn SENSEn
OVERTEMPERATURE Tj INPUTn LOAD CURRENTn SENSEn
ISENSE= VSENSEH RSENSE TTSD TR
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VNQ600AP
APPLICATION SCHEMATIC
+5V Rprot INPUT1 VCC1,2 VCC3,4 Dld Rprot Rprot C. SENSE 1 INPUT2 OUTPUT1
C Rprot Rprot INPUT3 Rprot Rprot Rprot C. SENSE 4 GND1,2 GND3,4 C. SENSE 3 INPUT4 OUTPUT4 OUTPUT3 C. SENSE 2 OUTPUT2
RSENSE1,2,3,4 VGND
RGND DGND
Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2.
GND PROTECTION REVERSE BATTERY
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / 2(IS(on)max ). 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device's datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds
and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT line is also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT pin is to leave it unconnected, while unused SENSE pin has to be connected to Ground pin.
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1
VNQ600AP
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table.
C I/Os PROTECTION:
If a ground protection network is used and negative transients are present on the VCC line, the control pins will
be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 6k. Recommended Rprot value is 5k.
Figure 3: IOUT/ISENSE versus IOUT IOUT/ISENSE
6500 6000 5500
max.Tj=25...150C max.Tj=-40C
5000
typical value
4500
min.Tj=25...150C
4000
min.Tj=-40C
3500 3000
0
0.5
1
1.5
2
IOUT (A)
2.5
3
3.5
4
4.5
10/18
VNQ600AP
Off State Output Current
IL(off1) (uA)
5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
High Level Input Current
Iih (uA)
5 4.5
Off state Vcc=36V Vin=Vout=0V
Vin=3.25V
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Input Clamp Voltage
Vicl (V)
8 7.8
Input High Level
Vih (V)
3.6 3.4 3.2
Iin=1mA
7.6 7.4 7.2 7 6.8 6.6
3 2.8 2.6 2.4
6.4 6.2 6 -50 -25 0 25 50 75 100 125 150 175 2.2 2 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Input Low Level
Vil (V)
2.6 2.4 2.2
Input Hysteresis Voltage
Vhyst (V)
1.5 1.4 1.3 1.2
2 1.8 1.6 1.4
1.1 1 0.9 0.8 0.7
1.2 1 -50 -25 0 25 50 75 100 125 150 175
0.6 0.5 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
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VNQ600AP
Overvoltage Shutdown
Vov (V)
50 48 46
ILIM Vs Tcase
Ilim (A)
80 70
Vcc=13V
60
44 42 40 38 36 20 34 32 30 -50 -25 0 25 50 75 100 125 150 175 10 0 -50 -25 0 25 50 75 100 125 150 175 50 40 30
Tc (C)
Tc (C)
Turn-on Voltage Slope
dVout/dt(on) (V/ms)
750 700 650 600 550 500 450 400 350 300 250 -50 -25 0 25 50 75 100 125 150 175
Turn-off Voltage Slope
dVout/dt(off) (V/ms)
500 450
Vcc=13V Rl=2.6Ohm
400 350 300 250 200 150 100 50 0 -50
Vcc=13V Rl=2.6Ohm
-25
0
25
50
75
100
125
150
175
Tc (C)
Tc (C)
On State Resistance Vs Tcase
Ron (mOhm)
100 90 80 70 60 50 40 30
On State Resistance Vs V CC
Ron (mOhm)
80 70
Iout=5A Vcc=8V & 36V
Iout=5A
60 50 40 30 20
Tc= 150C
Tc= 25C
20 10 0 -75 -50 -25 0 25 50 75 100 125 150 175
Tc= - 40C
10 0 5 10 15 20 25 30 35 40
Tc (C)
Vcc (V)
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VNQ600AP
Maximum turn off current versus load inductance
ILMAX (A) 100
A B C
10
1 0.001 0.01 0.1 L(mH )
A = Single Pulse at TJstart=150C B= Repetitive pulse at T Jstart=100C C= Repetitive Pulse at T Jstart=125C Conditions: VCC=13.5V Values are generated with R L=0 In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization
1
10
100
t
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VNQ600AP
SO-28 DOUBLE ISLAND THERMAL DATA
SO-28 Double island PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: 0.5cm2, 3cm2, 6cm2).
Thermal calculation according to the PCB heatsink area
Chip 1 ON OFF ON ON Chip 2 OFF ON ON ON Tjchip1 RthA x Pdchip1 + Tamb RthC x Pdchip2 + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb (RthA x Pdchip1) + RthC x Pdchip2 + Tamb Tjchip2 Note RthC x Pdchip1 + Tamb RthA x Pdchip2 + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb Pdchip1=Pdchip2 (RthA x Pdchip2) + RthC x Pdchip1 + T amb Pdchip1Pdchip2
RthA = Thermal resistance Junction to Ambient with one chip ON RthB = Thermal resistance Junction to Ambient with both chips ON and Pdchip1=Pdchip2 RthC = Mutual thermal resistance
Rthj-amb Vs PCB copper area in open box free air condition
RTHj_am b (C/W) 70 60 50 40 30 20 10 0 1 2 3 4 5 PCB Cu heatsink area (cm ^2)/island 6 7
RthA RthB
RthC
14/18
VNQ600AP
SO-28 Thermal Impedance Junction Ambient Single Pulse
Zth(C/W)
100
0,5 cm ^2/island 3 cm ^2/island 6 cm ^2/island
10
One channel ON Two channels ON on same chip
1
0.1
0.01 0.0001
0.001
0.01
0.1 1 time(s)
10
100
1000
Thermal fitting model of a four channels HSD in SO-28
Pulse calculation formula
Z TH = R TH + Z TH tp ( 1 - )
where
Tj_1
= tp T
0.5 0.05 0.3 3.4 11 15 30 0.001 5.00E-03 1.00E-02 0.2 1.5 5 150 6
C1
C2
C3
C4
C5
C6
Thermal Parameter
R1 Pd1 R2 R3 R4 R5 R6
Tj_2
C13
C14
R13 Pd2
R14
R17
R18
Tj_3
Pd3
C7
C8
C9
C10
C11
C12
R7
R8
R9
R10
R11
R12
Tj_4
C15
C16
R15 Pd4
R16
T_amb
Area/island (cm2) R1=R7=R13=R15 (C/W) R2=R8=R14=R16 (C/W) R3=R9 (C/W) R4=R10 (C/W) R5=R11 (C/W) R6=R12 (C/W) C1=C7=C13=C15 (W.s/C) C2=C8=C14=C16 (W.s/C) C3=C9 (W.s/C) C4=C10 (W.s/C) C5=C11 (W.s/C) C6=C12 (W.s/C) R17=R18 (C/W)
13
8
15/18
VNQ600AP
SO-28 MECHANICAL DATA
DIM. A a1 b b1 C c1 D E e e3 F L S 7.40 0.40 17.7 10.00 1.27 16.51 7.60 1.27 8 (max.) 0.291 0.016 18.1 10.65 0.10 0.35 0.23 0.50 45 (typ.) 0.697 0.393 0.050 0.650 0.299 0.050 0.713 0.419 mm. MIN. TYP MAX. 2.65 0.30 0.49 0.32 0.004 0.013 0.009 0.020 MIN. inch TYP. MAX. 0.104 0.012 0.019 0.012
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2
VNQ600AP
SO-28 TUBE SHIPMENT (no suffix) Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1)
All dimensions are in mm.
A
C B
28 700 532 3.5 13.8 0.6
TAPE AND REEL SHIPMENT (suffix "13TR") REEL DIMENSIONS
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 16.4 60 22.4
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 16 4 12 1.5 1.5 7.5 6.5 2
End
All dimensions are in mm.
Start Top cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min No components Components No components
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VNQ600AP
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States http://www.st.com
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